projects/soc目录下存放了接入ysyxSoC的示例程序。源码中只有一个占位符,能够通过编译但不能正常运行。 要使用该框架,需要先按照 ysyx SoC 的 readme 完成 命名规范 和 CPU 内部修改 两个步骤,得到 ysyx_21xxxx.v,
最近更新: 2年前Assembler and example programs for the CHUNGUS 2 Minecraft CPU. 这是一个红石CPU的汇编语言工具。CHUNGUS即Computational Humongous Unconventional Number and Graphic...
最近更新: 2年前现已开源存档,并制作了一个全新的数字电路教学存档,都放到github上,地址在https://github.com/Alpha21016/Minecraft-Digital-Circuit
最近更新: 2年前本项目基于RISC-V指令集架构,借助RISC-V Rocket Chip平台设计SoC,并通过协处理器(Rocket Custom Coprocessor,RoCC) 接口,采用高级语言Chisel定制Cordic算法片上加速器,实现自定义指令以完成正余弦函数值计算。注:依赖的rocketc...
最近更新: 2年多前This is a simple riscv verilog implementation. It can be built successfully using Quartus 20.1 Lite and/or Verilator. It is also passed the riscv-a...
最近更新: 2年多前Zhou Fan (范舟) This project is a RISC-V CPU with 5-stage pipeline implemented in Verilog HDL, which is a course project of Computer Architecture, A...
最近更新: 2年多前The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
最近更新: 2年多前Open-source high-performance RISC-V processor
最近更新: 2年多前This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core. For more information on Rocket Chip, please con...
最近更新: 接近3年前Next, you'll need to build an instance of the Berkeley Bootloader(BBL) that contains your linux image as a payload. BBL is provided alongside the p...
最近更新: 接近3年前