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From 3ba40f66bac4e90b8b02f0839837e64cc3ca041b Mon Sep 17 00:00:00 2001
From: cuijianying <cuijianying@kylinos.cn>
Date: Thu, 19 Oct 2023 11:23:19 +0800
Subject: [PATCH 12/12] add config supporting physical pci device for ft2004
board [KEYWORDS] [TO SOLVE] [TEST SUGGESTION] none
[SUBMIT BY] cuijianying
[REVIEW BY] cuijianying
[TEST BY] cuijianying
Signed-off-by: cuijianying <cuijianying@kylinos.cn>
---
configs/arm64/dts/ft2004-pcidev.dts | 126 ++++++++++++
configs/arm64/ft2004-guest-pcidev.c | 161 +++++++++++++++
configs/arm64/ft2004-main-pcidev.c | 290 ++++++++++++++++++++++++++++
3 files changed, 577 insertions(+)
create mode 100644 configs/arm64/dts/ft2004-pcidev.dts
create mode 100644 configs/arm64/ft2004-guest-pcidev.c
create mode 100644 configs/arm64/ft2004-main-pcidev.c
diff --git a/configs/arm64/dts/ft2004-pcidev.dts b/configs/arm64/dts/ft2004-pcidev.dts
new file mode 100644
index 00000000..bd134c56
--- /dev/null
+++ b/configs/arm64/dts/ft2004-pcidev.dts
@@ -0,0 +1,126 @@
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,ft-2004";
+ interrupt-parent = <0x1>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ model = "FT-2000/4-D4-DSK Development Board";
+
+ hypervisor {
+ compatible = "jailhouse,cell";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ numa-node-id = <0x0>;
+ clocks = <0x2 0x1>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ numa-node-id = <0x0>;
+ clocks = <0x2 0x1>;
+ };
+ };
+
+ interrupt-controller@29900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x3>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+ interrupt-controller;
+ reg = <0x0 0x29900000 0x0 0x20000 0x0 0x29980000 0x0 0x80000 0x0 0x29c00000 0x0 0x10000 0x0 0x29c10000 0x0 0x10000 0x0 0x29c20000 0x0 0x10000>;
+ interrupts = <0x1 0x9 0x4>;
+ phandle = <0x1>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x1 0xd 0x8 0x1 0xe 0x8 0x1 0xb 0x8 0x1 0xa 0x8>;
+ clock-frequency = <0x2dc6c00>;
+ };
+
+ clocks {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x6>;
+ };
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x3>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0x4>;
+ };
+ };
+
+ pcie {
+ compatible = "pci-host-ecam-generic";
+ linux,pci-domain = <0x0>;
+ device_type = "pci";
+ #address-cells = <0x3>;
+ #size-cells = <0x2>;
+ #interrupt-cells = <0x1>;
+ reg = <0x0 0x40000000 0x0 0x10000000>;
+ #msi-parent = <0x4>;
+ bus-range = <0x0 0xff>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x1c 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x1d 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x1e 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x1f 0x4>;
+ ranges = <0x1000000 0x0 0x0 0x0 0x50000000 0x0 0xf00000 0x2000000 0x0 0x58000000 0x0 0x58000000 0x0 0x28000000 0x3000000 0x10 0x0 0x10 0x0 0x10 0x0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ dma-coherent;
+ ranges;
+
+ uart@28000000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x28000000 0x0 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x2>;
+ reg-io-width = <0x4>;
+ interrupts = <0x0 0x6 0x4>;
+ clocks = <0x3 0x3>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+ };
+};
diff --git a/configs/arm64/ft2004-guest-pcidev.c b/configs/arm64/ft2004-guest-pcidev.c
new file mode 100644
index 00000000..66fd3abd
--- /dev/null
+++ b/configs/arm64/ft2004-guest-pcidev.c
@@ -0,0 +1,161 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for linux-demo inmate on Phytium FT2000/4
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[20];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[1];
+ struct jailhouse_pci_capability pci_caps[7];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "ft2004-guest-pcidev",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .num_pci_caps = ARRAY_SIZE(config.pci_caps),
+
+ .vpci_irq_base = 102,
+
+ .console = {
+ .address = 0x28000000,
+ .type = JAILHOUSE_CON_TYPE_PL011,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },
+ },
+
+ .cpus = {
+ 0xc,
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory regions */
+ {
+ .phys_start = 0xb1000000,
+ .virt_start = 0xb1000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xb1001000,
+ .virt_start = 0xb1001000,
+ .size = 0x9000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xb100a000,
+ .virt_start = 0xb100a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xb100c000,
+ .virt_start = 0xb100c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xb100e000,
+ .virt_start = 0xb100e000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* UART0 */ {
+ .phys_start = 0x28000000,
+ .virt_start = 0x28000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* RAM */ {
+ .phys_start = 0xb1100000,
+ .virt_start = 0,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+ /* RAM */ {
+ .phys_start = 0xb2000000,
+ .virt_start = 0xb2000000,
+ .size = 0x1d000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA |
+ JAILHOUSE_MEM_LOADABLE,
+ },
+ /* communication region */ {
+ .virt_start = 0x80000000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ /* I210 0000:02:00:0 */ {
+ .phys_start = 0x58100000,
+ .virt_start = 0x58000000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* I210 0000:02:00:0 */ {
+ .phys_start = 0x58300000,
+ .virt_start = 0x58100000,
+ .size = 0x4000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ },
+
+ .irqchips = {
+ /* GIC */ {
+ .address = 0x29900000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 1 << (38 - 32) | 1 << (60 - 32),
+ 0,
+ 0,
+ 1 << (102 + 32 - 128),
+ },
+ },
+ },
+
+ .pci_devices = {
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE,
+ .domain = 0,
+ .bdf = 0x2 << 8,
+ .caps_start = 0,
+ .num_caps = 7,
+ .num_msi_vectors = 1,
+ .msi_64bits = 1,
+ .msi_maskable = 1,
+ .num_msix_vectors = 5,
+ .msix_region_size = 0x4000,
+ .msix_address = 0x58300000,
+ .bar_mask={0xfff00000, 0x00000000, 0x00000000, 0xffffc000, 0x00000000, 0x00000000, },
+ },
+ },
+
+ .pci_caps = {
+ {.id=PCI_CAP_ID_PM, .start=0x40, .len=8, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSI, .start=0x50, .len=32, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_MSIX, .start=0x70, .len=12, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_CAP_ID_EXP, .start=0xa0, .len=60, .flags=JAILHOUSE_PCICAPS_WRITE},
+ {.id=PCI_EXT_CAP_ID_ERR, .start=0x100, .len=64, .flags=0},
+ {.id=PCI_EXT_CAP_ID_DSN, .start=0x140, .len=12, .flags=0},
+ {.id=PCI_EXT_CAP_ID_TPH, .start=0x1a0, .len=2, .flags=0},
+ },
+};
diff --git a/configs/arm64/ft2004-main-pcidev.c b/configs/arm64/ft2004-main-pcidev.c
new file mode 100644
index 00000000..d3aa4e6c
--- /dev/null
+++ b/configs/arm64/ft2004-main-pcidev.c
@@ -0,0 +1,290 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for Phytium FT2000/4
+ *
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_system header;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[26];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {
+ .header = {
+ .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
+ .hypervisor_memory = {
+ .phys_start = 0xb0000000,
+ .size = 0x01000000,
+ },
+ .debug_console = {
+ .address = 0x28000000,
+ .size = 0x1000,
+ .type = JAILHOUSE_CON_TYPE_PL011,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },
+ .platform_info = {
+ .pci_mmconfig_base = 0x40000000,
+ .pci_mmconfig_end_bus = 5,
+ .pci_is_virtual = 0,
+ .pci_domain = 1,
+
+ .arm = {
+ .gic_version = 3,
+ .gicd_base = 0x29900000,
+ .gicr_base = 0x29980000,
+ .gicc_base = 0x29c00000,
+ .gich_base = 0x29c10000,
+ .gicv_base = 0x29c20000,
+ .maintenance_irq = 25,
+ },
+ },
+ .root_cell = {
+ .name = "ft2004-main-pcidev",
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+
+ .vpci_irq_base = 100,
+ },
+ },
+
+ .cpus = {
+ 0xf,
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory regions */
+ {
+ .phys_start = 0xb1000000,
+ .virt_start = 0xb1000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ {
+ .phys_start = 0xb1001000,
+ .virt_start = 0xb1001000,
+ .size = 0x9000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ {
+ .phys_start = 0xb100a000,
+ .virt_start = 0xb100a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ {
+ .phys_start = 0xb100c000,
+ .virt_start = 0xb100c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ {
+ .phys_start = 0xb100e000,
+ .virt_start = 0xb100e000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ /* Main memory */
+ {
+ .phys_start = 0x80000000,
+ .virt_start = 0x80000000,
+ .size = 0x80000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* Main memory */
+ {
+ .phys_start = 0x2000000000,
+ .virt_start = 0x2000000000,
+ .size = 0x380000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* UART 0-3 */
+ {
+ .phys_start = 0x28000000,
+ .virt_start = 0x28000000,
+ .size = 0x4000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* GPIO 0-1 */
+ {
+ .phys_start = 0x28004000,
+ .virt_start = 0x28004000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* I2C 0-1 */
+ {
+ .phys_start = 0x28006000,
+ .virt_start = 0x28006000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* Watchdog 0 */
+ {
+ .phys_start = 0x2800a000,
+ .virt_start = 0x2800a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* Watchdog 1 */
+ {
+ .phys_start = 0x28016000,
+ .virt_start = 0x28016000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* SPI 0 */
+ {
+ .phys_start = 0x2800c000,
+ .virt_start = 0x2800c000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* SPI 1 */
+ {
+ .phys_start = 0x28013000,
+ .virt_start = 0x28013000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* QSPI */
+ {
+ .phys_start = 0x28014000,
+ .virt_start = 0x28014000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* HDA */
+ {
+ .phys_start = 0x28206000,
+ .virt_start = 0x28206000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* CAN 0-2 and SDCI*/
+ {
+ .phys_start = 0x28207000,
+ .virt_start = 0x28207000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* ETH0 */
+ {
+ .phys_start = 0x2820c000,
+ .virt_start = 0x2820c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* ETH1 */
+ {
+ .phys_start = 0x28210000,
+ .virt_start = 0x28210000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* Mailbox */
+ {
+ .phys_start = 0x2a000000,
+ .virt_start = 0x2a000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* SRAM */
+ {
+ .phys_start = 0x2a006000,
+ .virt_start = 0x2a006000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* GIC ITS */
+ {
+ .phys_start = 0x29920000,
+ .virt_start = 0x29920000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PCIe ECAM */
+ {
+ .phys_start = 0x40000000,
+ .virt_start = 0x40000000,
+ .size = 0x10000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PCIe IO */
+ {
+ .phys_start = 0x50000000,
+ .virt_start = 0x50000000,
+ .size = 0x8000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PCIe Mem32 */
+ {
+ .phys_start = 0x58000000,
+ .virt_start = 0x58000000,
+ .size = 0x28000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PCIe Mem64 */
+ {
+ .phys_start = 0x1000000000,
+ .virt_start = 0x1000000000,
+ .size = 0x1000000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ },
+
+ .irqchips = {
+ /* GIC */
+ {
+ .address = 0x29900000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ },
+ },
+
+ .pci_devices = {
+ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 1,
+ .bdf = 0 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 0,
+ .shmem_dev_id = 0,
+ .shmem_peers = 3,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
+ },
+ },
+};
--
2.25.1
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