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From a5cc6ff306c30cffa2ecbbafab9276c6fe9181c6 Mon Sep 17 00:00:00 2001
From: zhangyoujing <zhangyoujing@kylinos.cn>
Date: Fri, 11 Aug 2023 14:18:37 +0800
Subject: [PATCH 08/12] add Phytium PC ft2004 cell configures and dts for igb
[KEYWORDS] intel igb [TO SOLVE] igb configures and dts [TEST SUGGESTION] igb
[SUBMIT BY] zhangyoujing [REVIEW BY] zhangyoujing [TEST BY] zhangyoujing
---
configs/arm64/dts/ft2004-AMA0-igb.dts | 135 ++++
configs/arm64/ft2004-PC-guest-igb.c | 174 +++++
configs/arm64/ft2004-PC-main-igb.c | 1009 +++++++++++++++++++++++++
3 files changed, 1318 insertions(+)
create mode 100755 configs/arm64/dts/ft2004-AMA0-igb.dts
create mode 100644 configs/arm64/ft2004-PC-guest-igb.c
create mode 100644 configs/arm64/ft2004-PC-main-igb.c
diff --git a/configs/arm64/dts/ft2004-AMA0-igb.dts b/configs/arm64/dts/ft2004-AMA0-igb.dts
new file mode 100755
index 00000000..d1955aa4
--- /dev/null
+++ b/configs/arm64/dts/ft2004-AMA0-igb.dts
@@ -0,0 +1,135 @@
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,ft-2004";
+ interrupt-parent = <0x01>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ model = "FT-2000/4-D4-DSK Development Board";
+
+ hypervisor {
+ compatible = "jailhouse,cell";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ cpus {
+ #address-cells = <0x02>;
+ #size-cells = <0x00>;
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x100>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x00 0x101>;
+ enable-method = "psci";
+ numa-node-id = <0x00>;
+ clocks = <0x02 0x01>;
+ };
+ };
+
+ interrupt-controller@29900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x03>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ interrupt-controller;
+ reg = <0x00 0x29900000 0x00 0x20000 0x00 0x29980000 0x00 0x80000 0x00 0x29c00000 0x00 0x10000 0x00 0x29c10000 0x00 0x10000 0x00 0x29c20000 0x00 0x10000>;
+ interrupts = <0x01 0x09 0x04>;
+ phandle = <0x01>;
+
+ gic-its@29920000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ reg = <0x00 0x29920000 0x00 0x20000>;
+ phandle = <0x05>;
+ };
+/**/
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
+ clock-frequency = <0x2dc6c00>;
+ };
+
+ clocks {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x06>;
+ };
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x03>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0x04>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ dma-coherent;
+ ranges;
+
+ uart@28001000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x28001000 0x00 0x1000>;
+ baud = <0x1c200>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ interrupts = <0x00 0x07 0x04>;
+ clocks = <0x03 0x03>;
+ clock-names = "uartclk\0apb_pclk";
+ };
+
+ pcie {
+ compatible = "pci-host-ecam-generic";
+ linux,pci-domain = <0x00>;
+ device_type = "pci";
+ #address-cells = <0x03>;
+ #size-cells = <0x02>;
+ #interrupt-cells = <0x01>;
+ reg = <0x00 0x40000000 0x00 0x10000000>;
+ msi-parent = <0x05>;
+ bus-range = <0x0 0xff>;
+ interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+ interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x1c 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x00 0x00 0x1d 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x00 0x00 0x1e 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x00 0x00 0x1f 0x04>;
+ ranges = <0x1000000 0x00 0x00 0x00 0x50000000 0x00 0xf00000 0x2000000 0x00 0x58000000 0x00 0x58000000 0x00 0x28000000 0x3000000 0x10 0x00 0x10 0x00 0x10 0x00>;
+ };
+/**/
+ };
+};
diff --git a/configs/arm64/ft2004-PC-guest-igb.c b/configs/arm64/ft2004-PC-guest-igb.c
new file mode 100644
index 00000000..2b93c7d3
--- /dev/null
+++ b/configs/arm64/ft2004-PC-guest-igb.c
@@ -0,0 +1,174 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for demo inmate on Phytium FT2000/4
+ *
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[6];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[1];
+ struct jailhouse_pci_capability pci_caps[7];
+} __attribute__((packed)) config = {
+ .cell =
+ {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "linux",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .num_pci_caps = ARRAY_SIZE(config.pci_caps),
+ .vpci_irq_base = 101,
+
+ .console =
+ {
+ .address = 0x28001000,
+ .type = JAILHOUSE_CON_TYPE_PL011,
+ .flags =
+ JAILHOUSE_CON_ACCESS_MMIO | JAILHOUSE_CON_REGDIST_4,
+ },
+ },
+
+ .cpus =
+ {
+ 0xC,
+ },
+
+ .irqchips =
+ {
+ {
+ .address = 0x29900000,
+ .pin_base = 32,
+ .pin_bitmap =
+ {
+ 1 << (39 - 32),
+ 0,
+ 0,
+ 1 << (101 + 32 - 128),
+ },
+ },
+ },
+
+ .mem_regions = {
+ /* UART */ {
+ .phys_start = 0x28001000,
+ .virt_start = 0x28001000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* RAM */
+ {
+ .phys_start = 0x92000000,
+ .virt_start = 0,
+ .size = 0x1000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+
+ /* RAM */
+ {
+ .phys_start = 0x93000000,
+ .virt_start = 0x93000000,
+ .size = 0x1d000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA |
+ JAILHOUSE_MEM_LOADABLE,
+ },
+
+ /* GICR_PROPBASER GICR_PENDING {
+ .phys_start = 0x2140300000,
+ .virt_start = 0x2140300000,
+ .size = 0x50000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },*/
+
+ /* communication region */
+ {
+ .virt_start = 0x80000000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ /* MemRegion: 58300000-583fffff : 0000:05:00.0 */
+ {
+ .phys_start = 0x58300000,
+ .virt_start = 0x58000000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* MemRegion: 58502000-58503fff : 0000:05:00.0 */
+ {
+ .phys_start = 0x58502000,
+ .virt_start = 0x58102000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+#if 0
+#endif
+ },
+
+ .pci_devices =
+ {
+ /* PCIDevice: 0000:05:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE,
+ .domain = 0x0,
+ .bdf = 0x500,
+ .caps_start = 0,
+ .num_caps = 7,
+ .num_msi_vectors = 1,
+ .msi_64bits = 1,
+ .msi_maskable = 1,
+ .num_msix_vectors = 5,
+ .msix_region_size = 0x4000,
+ .msix_address = 0x58500000,
+ .bar_mask =
+ {
+ 0xfff00000,
+ 0x00000000,
+ 0x00000000,
+ 0xffff8000,
+ 0x00000000,
+ 0x00000000,
+ },
+ },
+ },
+ .pci_caps =
+ {
+ /* PCIDevice: 0000:05:00.0 */
+ {.id = PCI_CAP_ID_PM,
+ .start = 0x40,
+ .len = 8,
+ .flags = JAILHOUSE_PCICAPS_WRITE},
+ {.id = PCI_CAP_ID_MSI,
+ .start = 0x50,
+ .len = 32,
+ .flags = JAILHOUSE_PCICAPS_WRITE},
+ {.id = PCI_CAP_ID_MSIX,
+ .start = 0x70,
+ .len = 12,
+ .flags = JAILHOUSE_PCICAPS_WRITE},
+ {.id = PCI_CAP_ID_EXP,
+ .start = 0xa0,
+ .len = 60,
+ .flags = JAILHOUSE_PCICAPS_WRITE},
+ {.id = PCI_EXT_CAP_ID_ERR, .start = 0x100, .len = 64, .flags = 0},
+ {.id = PCI_EXT_CAP_ID_DSN, .start = 0x140, .len = 12, .flags = 0},
+ {.id = PCI_EXT_CAP_ID_TPH, .start = 0x1a0, .len = 2, .flags = 0},
+ },
+#if 0
+#endif
+};
diff --git a/configs/arm64/ft2004-PC-main-igb.c b/configs/arm64/ft2004-PC-main-igb.c
new file mode 100644
index 00000000..4204d8eb
--- /dev/null
+++ b/configs/arm64/ft2004-PC-main-igb.c
@@ -0,0 +1,1009 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (c) Siemens AG, 2014-2017
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ *
+ * Alternatively, you can use or redistribute this file under the following
+ * BSD license:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Configuration for Greatwall GW-001M1A-FTF
+ * created with '/usr/local/libexec/jailhouse/jailhouse config create gh2.c'
+ *
+ * NOTE: This config expects the following to be appended to your kernel cmdline
+ * "memmap=0x5200000$0x2000000000"
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_system header;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[37];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[13];
+ struct jailhouse_pci_capability pci_caps[48];
+} __attribute__((packed)) config =
+ {
+ .header =
+ {
+ .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
+ .hypervisor_memory =
+ {
+ .phys_start = 0x90000000,
+ .size = 0x01000000,
+ },
+ /**/
+ .debug_console =
+ {
+ .address = 0x28001000,
+ .size = 0x1000,
+ .type = JAILHOUSE_CON_TYPE_PL011,
+ .flags =
+ JAILHOUSE_CON_ACCESS_MMIO | JAILHOUSE_CON_REGDIST_4,
+ },
+
+ .platform_info =
+ {
+ .pci_mmconfig_base = 0x40000000,
+ //.pci_mmconfig_end_bus = 0,
+ .pci_mmconfig_end_bus = 6,
+ //.pci_is_virtual = 1,
+ .pci_is_virtual = 0,
+ .pci_domain = 1,
+ .arm =
+ {
+ .gic_version = 3,
+ .gicd_base = 0x29900000,
+ .gicr_base = 0x29980000,
+ .gicc_base = 0x29c00000,
+ .gich_base = 0x29c10000,
+ .gicv_base = 0x29c20000,
+ //.gic_its_base = 0x29920000,
+ .maintenance_irq = 25,
+ },
+ },
+ .root_cell =
+ {
+ .name = "RootCell",
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .num_pci_caps = ARRAY_SIZE(config.pci_caps),
+ .vpci_irq_base = 100,
+ },
+ },
+
+ .cpus =
+ {
+ 0x000000000000000f,
+ },
+
+ .mem_regions =
+ {
+ /* MemRegion: 28000000-28000fff : ARMH0011:01 */
+ {
+ .phys_start = 0x28000000,
+ .virt_start = 0x28000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 28001000-28001fff : ARMH0011:00 */
+ {
+ .phys_start = 0x28001000,
+ .virt_start = 0x28001000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 28004000-28004fff : FTGP0001:00 */
+ {
+ .phys_start = 0x28004000,
+ .virt_start = 0x28004000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 28006000-28006fff : FTI20001:00 */
+ {
+ .phys_start = 0x28006000,
+ .virt_start = 0x28006000,
+ .size = 0x2000, /*GHADD: 0x1000 -> 0x2000*/
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 2800a000-2800afff : sbsa-gwdt.0 */
+ {
+ .phys_start = 0x2800a000,
+ .virt_start = 0x2800a000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 2800b000-2800bfff : sbsa-gwdt.0 */
+ {
+ .phys_start = 0x2800b000,
+ .virt_start = 0x2800b000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 28016000-28016fff : sbsa-gwdt.1 */
+ {
+ .phys_start = 0x28016000,
+ .virt_start = 0x28016000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 28017000-28017fff : sbsa-gwdt.1 */
+ {
+ .phys_start = 0x28017000,
+ .virt_start = 0x28017000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 28206000-28206fff : FTHD0001:00 */
+ {
+ .phys_start = 0x28206000,
+ .virt_start = 0x28206000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 28207c00-28207cff : FTSD0001:00 */
+ {
+ .phys_start = 0x28207c00,
+ .virt_start = 0x28207c00,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 2820c000-2820dfff : FTGM0001:00 */
+ {
+ .phys_start = 0x2820c000,
+ .virt_start = 0x2820c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 28210000-28211fff : FTGM0001:01 */
+ {
+ .phys_start = 0x28210000,
+ .virt_start = 0x28210000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 2a000000-2a000fff : FTMB0001:00 */
+ {
+ .phys_start = 0x2a000000,
+ .virt_start = 0x2a000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 2a006000-2a007fff : FTSH0001:00 */
+ {
+ .phys_start = 0x2a006000,
+ .virt_start = 0x2a006000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+
+ /* gic its */
+ {
+ .phys_start = 0x29920000,
+ .virt_start = 0x29920000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+#if 0
+#endif
+ /* MemRegion: 40000000-4fffffff : PCI ECAM */
+ {
+ .phys_start = 0x40000000,
+ .virt_start = 0x40000000,
+ .size = 0x10000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 50000000-57ffffff : PCI ECAM */
+ {
+ /*GHADD: PCIe IO*/
+ .phys_start = 0x50000000,
+ .virt_start = 0x50000000,
+ .size = 0x8000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+
+ /* MemRegion: 58000000-5803ffff : 0000:02:00.0 */
+ {
+ .phys_start = 0x58000000,
+ .virt_start = 0x58000000,
+ .size = 0x40000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 58040000-5805ffff : 0000:02:00.0 */
+ {
+ .phys_start = 0x58040000,
+ .virt_start = 0x58040000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 58060000-58063fff : 0000:02:00.1 */
+ {
+ .phys_start = 0x58060000,
+ .virt_start = 0x58060000,
+ .size = 0x4000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 58100000-5810ffff : 0000:03:00.0 */
+ {
+ .phys_start = 0x58100000,
+ .virt_start = 0x58100000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 58110000-581107ff : ahci */
+ {
+ .phys_start = 0x58110000,
+ .virt_start = 0x58110000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 58200000-58202fff : nvme */
+ {
+ .phys_start = 0x58200000,
+ .virt_start = 0x58200000,
+ .size = 0x3000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 58203000-58203fff : nvme */
+ {
+ .phys_start = 0x58203000,
+ .virt_start = 0x58203000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 58300000-583fffff : igb */
+ {
+ .phys_start = 0x58300000,
+ .virt_start = 0x58300000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 58500000-58503fff : igb */
+ {
+ .phys_start = 0x58500000,
+ .virt_start = 0x58500000,
+ .size = 0x4000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 58600000-58601fff : xhci-hcd */
+ {
+ .phys_start = 0x58600000,
+ .virt_start = 0x58600000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 80000000-8fffffff : System RAM */
+ {
+ .phys_start = 0x80000000,
+ .virt_start = 0x80000000,
+ .size = 0x80000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
+ },
+ /* MemRegion: 1000000000-100fffffff : 0000:02:00.0 */
+ {
+ .phys_start = 0x1000000000,
+ .virt_start = 0x1000000000,
+ .size = 0x10000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 1010001000-10103fffff : 0000:00:00.0 */
+ {
+ .phys_start = 0x1010001000,
+ .virt_start = 0x1010001000,
+ .size = 0x3ff000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 1010401000-10107fffff : 0000:00:01.0 */
+ {
+ .phys_start = 0x1010401000,
+ .virt_start = 0x1010401000,
+ .size = 0x3ff000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 1010801000-1010bfffff : 0000:00:02.0 */
+ {
+ .phys_start = 0x1010801000,
+ .virt_start = 0x1010801000,
+ .size = 0x3ff000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 1010c01000-1010ffffff : 0000:00:03.0 */
+ {
+ .phys_start = 0x1010c01000,
+ .virt_start = 0x1010c01000,
+ .size = 0x3ff000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 1011001000-10113fffff : 0000:00:04.0 */
+ {
+ .phys_start = 0x1011001000,
+ .virt_start = 0x1011001000,
+ .size = 0x3ff000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 1011401000-10117fffff : 0000:00:05.0 */
+ {
+ .phys_start = 0x1011401000,
+ .virt_start = 0x1011401000,
+ .size = 0x3ff000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* MemRegion: 2000000000-217fffffff : System RAM */
+ {
+ .phys_start = 0x2000000000,
+ .virt_start = 0x2000000000,
+ .size = 0x180000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
+ },
+ /* MemRegion: 2000600000-20051fffff : JAILHOUSE Inmate Memory */
+ {
+ .phys_start = 0x2000600000,
+ .virt_start = 0x2000600000,
+ .size = 0x4c00000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ },
+
+ .irqchips =
+ {
+ {
+ .address = 0x29900000,
+ .pin_base = 32,
+ .pin_bitmap = {0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff},
+
+ },
+ },
+
+ .pci_devices =
+ {
+ /* PCIDevice: 00:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE,
+ .domain = 0x0,
+ .bdf = 0x0,
+ .bar_mask =
+ {
+ 0xffc00000,
+ 0xffffffff,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ },
+ .caps_start = 0,
+ .num_caps = 8,
+ .num_msi_vectors = 1,
+ .msi_64bits = 1,
+ .msi_maskable = 1,
+ .num_msix_vectors = 1,
+ .msix_region_size = 0x1000,
+ .msix_address = 0x1010000000,
+ },
+ /* PCIDevice: 00:01.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE,
+ .domain = 0x0,
+ .bdf = 0x8,
+ .bar_mask =
+ {
+ 0xffc00000,
+ 0xffffffff,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ },
+ .caps_start = 0,
+ .num_caps = 8,
+ .num_msi_vectors = 1,
+ .msi_64bits = 1,
+ .msi_maskable = 1,
+ .num_msix_vectors = 1,
+ .msix_region_size = 0x1000,
+ .msix_address = 0x1010400000,
+ },
+ /* PCIDevice: 00:02.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE,
+ .domain = 0x0,
+ .bdf = 0x10,
+ .bar_mask =
+ {
+ 0xffc00000,
+ 0xffffffff,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ },
+ .caps_start = 0,
+ .num_caps = 8,
+ .num_msi_vectors = 1,
+ .msi_64bits = 1,
+ .msi_maskable = 1,
+ .num_msix_vectors = 1,
+ .msix_region_size = 0x1000,
+ .msix_address = 0x1010800000,
+ },
+ /* PCIDevice: 00:03.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE,
+ .domain = 0x0,
+ .bdf = 0x18,
+ .bar_mask =
+ {
+ 0xffc00000,
+ 0xffffffff,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ },
+ .caps_start = 0,
+ .num_caps = 8,
+ .num_msi_vectors = 1,
+ .msi_64bits = 1,
+ .msi_maskable = 1,
+ .num_msix_vectors = 1,
+ .msix_region_size = 0x1000,
+ .msix_address = 0x1010c00000,
+ },
+ /* PCIDevice: 00:04.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE,
+ .domain = 0x0,
+ .bdf = 0x20,
+ .bar_mask =
+ {
+ 0xffc00000,
+ 0xffffffff,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ },
+ .caps_start = 0,
+ .num_caps = 8,
+ .num_msi_vectors = 1,
+ .msi_64bits = 1,
+ .msi_maskable = 1,
+ .num_msix_vectors = 1,
+ .msix_region_size = 0x1000,
+ .msix_address = 0x1011000000,
+ },
+ /* PCIDevice: 00:05.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_BRIDGE,
+ .domain = 0x0,
+ .bdf = 0x28,
+ .bar_mask =
+ {
+ 0xffc00000,
+ 0xffffffff,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ },
+ .caps_start = 0,
+ .num_caps = 8,
+ .num_msi_vectors = 1,
+ .msi_64bits = 1,
+ .msi_maskable = 1,
+ .num_msix_vectors = 1,
+ .msix_region_size = 0x1000,
+ .msix_address = 0x1011400000,
+ },
+ /* PCIDevice: 02:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE,
+ .domain = 0x0,
+ .bdf = 0x200,
+ .bar_mask =
+ {
+ 0xf0000000,
+ 0xffffffff,
+ 0xfffc0000,
+ 0xffffffff,
+ 0xffffff00,
+ 0x00000000,
+ },
+ .caps_start = 8,
+ .num_caps = 8,
+ .num_msi_vectors = 1,
+ .msi_64bits = 1,
+ .msi_maskable = 0,
+ .num_msix_vectors = 0,
+ .msix_region_size = 0x0,
+ .msix_address = 0x0,
+ },
+ /* PCIDevice: 02:00.1 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE,
+ .domain = 0x0,
+ .bdf = 0x201,
+ .bar_mask =
+ {
+ 0xffffc000,
+ 0xffffffff,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ },
+ .caps_start = 16,
+ .num_caps = 6,
+ .num_msi_vectors = 1,
+ .msi_64bits = 1,
+ .msi_maskable = 0,
+ .num_msix_vectors = 0,
+ .msix_region_size = 0x0,
+ .msix_address = 0x0,
+ },
+ /* PCIDevice: 03:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE,
+ .domain = 0x0,
+ .bdf = 0x300,
+ .bar_mask =
+ {
+ 0xfffffff8,
+ 0xfffffffc,
+ 0xfffffff8,
+ 0xfffffffc,
+ 0xffffffe0,
+ 0xfffff800,
+ },
+ .caps_start = 22,
+ .num_caps = 5,
+ .num_msi_vectors = 1,
+ .msi_64bits = 0,
+ .msi_maskable = 0,
+ .num_msix_vectors = 0,
+ .msix_region_size = 0x0,
+ .msix_address = 0x0,
+ },
+ /* PCIDevice: 04:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE,
+ .domain = 0x0,
+ .bdf = 0x400,
+ .bar_mask =
+ {
+ 0xffffc000,
+ 0xffffffff,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ },
+ .caps_start = 27,
+ .num_caps = 8,
+ .num_msi_vectors = 8,
+ .msi_64bits = 1,
+ .msi_maskable = 1,
+ .num_msix_vectors = 16,
+ .msix_region_size = 0x1000,
+ .msix_address = 0x58202000,
+ },
+ /* PCIDevice: 06:00.0
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE,
+ .domain = 0x0,
+ .bdf = 0x600,
+ .bar_mask = {
+ 0xffffe000, 0xffffffff, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000,
+ },
+ .caps_start = 35,
+ .num_caps = 6,
+ .num_msi_vectors = 8,
+ .msi_64bits = 1,
+ .msi_maskable = 0,
+ .num_msix_vectors = 8,
+ .msix_region_size = 0x1000,
+ .msix_address = 0x58301000,
+ },*/
+ /* PCIDevice: 0000:05:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE,
+ .domain = 0x0,
+ .bdf = 0x500,
+ .caps_start = 35,
+ .num_caps = 7,
+ .num_msi_vectors = 1,
+ .msi_64bits = 1,
+ .msi_maskable = 1,
+ //.venid = 0x8086,
+ //.devid = 0x1533,
+ .num_msix_vectors = 5,
+ .msix_region_size = 0x2000,
+ .msix_address = 0x58500000,
+ .bar_mask =
+ {
+ 0xfff00000,
+ 0x00000000,
+ 0x00000000,
+ 0xffffc000,
+ 0x00000000,
+ 0x00000000,
+ },
+ },
+ /* PCIDevice: 0000:06:00.0 */
+ {
+ .type = JAILHOUSE_PCI_TYPE_DEVICE,
+ .domain = 0x0,
+ .bdf = 0x600,
+ .caps_start = 42,
+ .num_caps = 6,
+ .num_msi_vectors = 8,
+ .msi_64bits = 1,
+ .msi_maskable = 0,
+ //.venid = 0x1912,
+ //.devid = 0x14,
+ .num_msix_vectors = 8,
+ .msix_region_size = 0x1000,
+ .msix_address = 0x58601000,
+ .bar_mask =
+ {
+ 0xffffe000,
+ 0xffffffff,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ },
+ },
+ },
+
+ .pci_caps =
+ {
+ /* PCIDevice: 00:00.0 */
+ /* PCIDevice: 00:01.0 */
+ /* PCIDevice: 00:02.0 */
+ /* PCIDevice: 00:03.0 */
+ /* PCIDevice: 00:04.0 */
+ /* PCIDevice: 00:05.0 */
+ {
+ .id = PCI_CAP_ID_PM,
+ .start = 0x80,
+ .len = 0x8,
+ .flags = JAILHOUSE_PCICAPS_WRITE,
+ },
+ {
+ .id = PCI_CAP_ID_MSI,
+ .start = 0x90,
+ .len = 0x18,
+ .flags = JAILHOUSE_PCICAPS_WRITE,
+ },
+ {
+ .id = PCI_CAP_ID_MSIX,
+ .start = 0xb0,
+ .len = 0xc,
+ .flags = JAILHOUSE_PCICAPS_WRITE,
+ },
+ {
+ .id = PCI_CAP_ID_EXP,
+ .start = 0xc0,
+ .len = 0x3c,
+ .flags = 0,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x100,
+ .len = 0x40,
+ .flags = 0,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_TPH | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x274,
+ .len = 0x4,
+ .flags = 0,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x300,
+ .len = 0x10,
+ .flags = 0,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_L1SS | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x900,
+ .len = 0x4,
+ .flags = 0,
+ },
+ /* PCIDevice: 02:00.0 */
+ {
+ .id = PCI_CAP_ID_VNDR,
+ .start = 0x48,
+ .len = 0x2,
+ .flags = 0,
+ },
+ {
+ .id = PCI_CAP_ID_PM,
+ .start = 0x50,
+ .len = 0x8,
+ .flags = JAILHOUSE_PCICAPS_WRITE,
+ },
+ {
+ .id = PCI_CAP_ID_EXP,
+ .start = 0x58,
+ .len = 0x3c,
+ .flags = 0,
+ },
+ {
+ .id = PCI_CAP_ID_MSI,
+ .start = 0xa0,
+ .len = 0xe,
+ .flags = JAILHOUSE_PCICAPS_WRITE,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x100,
+ .len = 0x14,
+ .flags = 0,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x150,
+ .len = 0x40,
+ .flags = 0,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_REBAR | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x200,
+ .len = 0x4,
+ .flags = 0,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x270,
+ .len = 0x10,
+ .flags = 0,
+ },
+ /* PCIDevice: 02:00.1 */
+ {
+ .id = PCI_CAP_ID_VNDR,
+ .start = 0x48,
+ .len = 0x2,
+ .flags = 0,
+ },
+ {
+ .id = PCI_CAP_ID_PM,
+ .start = 0x50,
+ .len = 0x8,
+ .flags = JAILHOUSE_PCICAPS_WRITE,
+ },
+ {
+ .id = PCI_CAP_ID_EXP,
+ .start = 0x58,
+ .len = 0x3c,
+ .flags = 0,
+ },
+ {
+ .id = PCI_CAP_ID_MSI,
+ .start = 0xa0,
+ .len = 0xe,
+ .flags = JAILHOUSE_PCICAPS_WRITE,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x100,
+ .len = 0x14,
+ .flags = 0,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x150,
+ .len = 0x40,
+ .flags = 0,
+ },
+ /* PCIDevice: 03:00.0 */
+ {
+ .id = PCI_CAP_ID_PM,
+ .start = 0x40,
+ .len = 0x8,
+ .flags = JAILHOUSE_PCICAPS_WRITE,
+ },
+ {
+ .id = PCI_CAP_ID_MSI,
+ .start = 0x50,
+ .len = 0xa,
+ .flags = JAILHOUSE_PCICAPS_WRITE,
+ },
+ {
+ .id = PCI_CAP_ID_EXP,
+ .start = 0x70,
+ .len = 0x3c,
+ .flags = 0,
+ },
+ {
+ .id = PCI_CAP_ID_SATA,
+ .start = 0xe0,
+ .len = 0x2,
+ .flags = 0,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x100,
+ .len = 0x40,
+ .flags = 0,
+ },
+ /* PCIDevice: 04:00.0 */
+ {
+ .id = PCI_CAP_ID_PM,
+ .start = 0x40,
+ .len = 0x8,
+ .flags = JAILHOUSE_PCICAPS_WRITE,
+ },
+ {
+ .id = PCI_CAP_ID_MSI,
+ .start = 0x50,
+ .len = 0x18,
+ .flags = JAILHOUSE_PCICAPS_WRITE,
+ },
+ {
+ .id = PCI_CAP_ID_EXP,
+ .start = 0x70,
+ .len = 0x3c,
+ .flags = 0,
+ },
+ {
+ .id = PCI_CAP_ID_MSIX,
+ .start = 0xb0,
+ .len = 0xc,
+ .flags = JAILHOUSE_PCICAPS_WRITE,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x100,
+ .len = 0x40,
+ .flags = 0,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x158,
+ .len = 0x10,
+ .flags = 0,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_LTR | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x178,
+ .len = 0x8,
+ .flags = 0,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_L1SS | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x180,
+ .len = 0x4,
+ .flags = 0,
+ },
+ /* PCIDevice: 06:00.0
+ {
+ .id = PCI_CAP_ID_PM,
+ .start = 0x50,
+ .len = 0x8,
+ .flags = JAILHOUSE_PCICAPS_WRITE,
+ },
+ {
+ .id = PCI_CAP_ID_MSI,
+ .start = 0x70,
+ .len = 0xe,
+ .flags = JAILHOUSE_PCICAPS_WRITE,
+ },
+ {
+ .id = PCI_CAP_ID_MSIX,
+ .start = 0x90,
+ .len = 0xc,
+ .flags = JAILHOUSE_PCICAPS_WRITE,
+ },
+ {
+ .id = PCI_CAP_ID_EXP,
+ .start = 0xa0,
+ .len = 0x3c,
+ .flags = 0,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x100,
+ .len = 0x40,
+ .flags = 0,
+ },
+ {
+ .id = PCI_EXT_CAP_ID_LTR | JAILHOUSE_PCI_EXT_CAP,
+ .start = 0x150,
+ .len = 0x8,
+ .flags = 0,
+ },*/
+ /* PCIDevice: 0000:05:00.0 */
+ {.id = PCI_CAP_ID_PM,
+ .start = 0x40,
+ .len = 8,
+ .flags = JAILHOUSE_PCICAPS_WRITE},
+ {.id = PCI_CAP_ID_MSI,
+ .start = 0x50,
+ .len = 10,
+ .flags = JAILHOUSE_PCICAPS_WRITE},
+ {.id = PCI_CAP_ID_MSIX,
+ .start = 0x70,
+ .len = 12,
+ .flags = JAILHOUSE_PCICAPS_WRITE},
+ {.id = PCI_CAP_ID_EXP,
+ .start = 0xa0,
+ .len = 60,
+ .flags = JAILHOUSE_PCICAPS_WRITE},
+ {.id = PCI_EXT_CAP_ID_ERR,
+ .start = 0x100,
+ .len = 64,
+ .flags = 0},
+ {.id = PCI_EXT_CAP_ID_DSN,
+ .start = 0x140,
+ .len = 12,
+ .flags = 0},
+ {.id = PCI_EXT_CAP_ID_TPH,
+ .start = 0x1a0,
+ .len = 2,
+ .flags = 0},
+ /* PCIDevice: 0000:06:00.0 */
+ {.id = PCI_CAP_ID_PM,
+ .start = 0x50,
+ .len = 8,
+ .flags = JAILHOUSE_PCICAPS_WRITE},
+ {.id = PCI_CAP_ID_MSI,
+ .start = 0x70,
+ .len = 10,
+ .flags = JAILHOUSE_PCICAPS_WRITE},
+ {.id = PCI_CAP_ID_MSIX,
+ .start = 0x90,
+ .len = 12,
+ .flags = JAILHOUSE_PCICAPS_WRITE},
+ {.id = PCI_CAP_ID_EXP,
+ .start = 0xa0,
+ .len = 60,
+ .flags = JAILHOUSE_PCICAPS_WRITE},
+ {.id = PCI_EXT_CAP_ID_ERR,
+ .start = 0x100,
+ .len = 64,
+ .flags = 0},
+ {.id = PCI_EXT_CAP_ID_LTR,
+ .start = 0x150,
+ .len = 8,
+ .flags = 0},
+ },
+};
--
2.25.1
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