codes for van Emde Boas Tree

Timsort and mergesort implement

Three Verilog codes file to implement simple state machine by output 1s

Verilog codes to implment ALU into FPGA board

Implement a Seq_array task to store an array starting at memory address 0x80. The array should be initialized to contain the first 32 elements of the Fibonacci sequence

Off-Line-Minimum(m, n)： 对于 i = 1 到 n 确定 j，使得 i 在 K_j 中 如果 j 不等于 m + 1 提取的[j] = i 设 l 是集合 K_l 存在的大于 j 的最小值 K_l = union( K_j, K_l), 销毁 K_j 返回 extracted