/*
 * Copyright 2024 Hangzhou Yingyi Technology Co., Ltd
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *    http://www.apache.org/licenses/LICENSE-2.0

 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include <uk/arch/lcpu.h>
#include <uk/arch/limits.h>
#include <uk/asm.h>
#include <uk/reloc.h>

ENTRY(start_mmu)
	/* Load ttbr0, pagetable starts from _end */
	ur_ldr  x27, arm64_bpt_l3_pt0
	msr ttbr0_el1, x27
	isb

	/* Clear the Monitor Debug System control register */
	msr mdscr_el1, xzr

	/* Invalidate the TLB to avoid stale one */
	tlbi vmalle1
	dsb nsh

	ldr x2, =MAIR_INIT_ATTR
	msr mair_el1, x2

#ifdef CONFIG_PAGING
	/* Set up TCR_EL1. The platform must provide a
	 * configuration compatible with the paging API.
	 */
	ldr x2, =TCR_INIT_FLAGS
	msr tcr_el1, x2
#else /* CONFIG_PAGING */
	/* Get VIRT_BITS from id_aa64mmfr0_el1.PARange */
	mrs x3, id_aa64mmfr0_el1
	ur_ldr  x5, tcr_ips_bits
	ubfx x4, x3, #0, #4
	ldrb w4, [x5, x4]
	cmp x4, #52
	b.lt setup_tcr_el1
	/*
	 * We currently do not provide 5-level page tables used in
	 * implementing 52-bit virtual addresing with 4K granularity, so we
	 * enforce the max VA to 48-bit for PARange >= 52.
	 */
	mov x4, #48
setup_tcr_el1:
	/* Setup TCR_EL1_TxSZ(64 - VIRT_BITS) for TCR_INIT_FLAGS */
	mov x5, #64
	sub x5, x5, x4
	mov x4, x5
	lsl x5, x5, #TCR_EL1_T1SZ_SHIFT
	orr x5, x4, x5
	ldr x2, =TCR_INIT_FLAGS
	orr x2, x5, x2
	bfi x2, x3, #32, #3
	msr tcr_el1, x2
#endif /* CONFIG_PAGING */

	/* Setup SCTLR */
	ldr x2, =SCTLR_SET_BITS
	ldr x3, =SCTLR_CLEAR_BITS
	mrs x1, sctlr_el1
	bic x1, x1, x3	/* Clear the required bits */
	orr x1, x1, x2	/* Set the required bits */
	msr sctlr_el1, x1
	isb

	ret
END(start_mmu)

ENTRY(clear_bss)
clear_bss_start:
	// Clear bss
	ldr     x1, =__bss_start
	ldr     w2, =__bss_size
clear_bss_loop:
	cbz     w2, clear_bss_done
	str     xzr, [x1], #8
	sub     w2, w2, #1
	cbnz    w2, clear_bss_loop
clear_bss_done:
	ret
END(clear_bss)