import modules as mods
from modules import *
from hdllinker import VerilogLinker
import re
from con import *
# 定义连接器
test_axis_con =  (
    {
        "input": r"^is_",
        "output": r"^m_",
    },
    # bus接口定义
    [],
    # 匹配规则
    r"(?=.*axis_)(?!.*dcp).*",
    # 连接器名称
    "inner"
)
test_top_out_axis_con =  (
    # 连接器定义
    {
        "input": r"^m_",
        "output": r"^im_",
    },
    # bus接口定义
    [],
    # 匹配信号的规则
    r"(?=.*axis_)(?!.*dcp).*",
    # 连接器名称
    "top"
)

hdll = VerilogLinker()
# 定义模块参数
AXIS_TDEST_WIDTH = 8
AXIS_TID_WIDTH = 8
AXI_ADDR_WIDTH = 16
AXI_DATA_WIDTH = 32
DATA_WIDTH = 16

AXIS_SLAVE_NUM = 3
AXI_SLAVE_NUM = 2
# 参数设置

# top模块设置
# dcp2axisl模块设置
pars = dcp2axisl.parameter
pars.SLAVE_DCP_ADDR_BYTE["value"] = 2
pars.SLAVE_DCP_LEN_BYTE["value"] = 4
pars.AXI_ADDR_WIDTH["value"] = AXI_ADDR_WIDTH
pars.AXI_DATA_WIDTH["value"] = AXI_DATA_WIDTH
pars.AXI_TDEST_WIDTH["value"] = AXIS_TDEST_WIDTH
pars.AXI_TID_WIDTH["value"] = AXIS_TID_WIDTH

# drm_base_proc_wrapper模块设置
pars = drm_base_proc_wrapper.parameter
pars.AXI_ARADDR_WIDTH["value"] = AXI_ADDR_WIDTH
pars.AXI_AWADDR_WIDTH["value"] = AXI_ADDR_WIDTH
pars.AXI_RDATA_WIDTH["value"] = AXI_DATA_WIDTH
pars.AXI_WDATA_WIDTH["value"] = AXI_DATA_WIDTH
pars.AXIS_TID_WIDTH["value"] = AXIS_TID_WIDTH
pars.DATA_WIDTH["value"] = DATA_WIDTH
pars.COMP_FIR_LEN["value"] = 256
pars.INTP_STAGE["value"] = 6
pars.PHASE_WIDTH["value"] = 24

# am_proc_wrapper模块设置
pars = am_proc_wrapper.parameter
pars.DATA_WIDTH["value"] = 18
pars.AXI_ARADDR_WIDTH["value"] = AXI_ADDR_WIDTH
pars.AXI_AWADDR_WIDTH["value"] = AXI_ADDR_WIDTH
pars.AXI_RDATA_WIDTH["value"] = AXI_DATA_WIDTH
pars.AXI_WDATA_WIDTH["value"] = AXI_DATA_WIDTH
pars.DATA_WIDTH["value"] = DATA_WIDTH

# axi_interconnect模块设置
pars = axi_interconnect.parameter
pars.AXI_ARADDR_WIDTH["value"] = AXI_ADDR_WIDTH
pars.AXI_AWADDR_WIDTH["value"] = AXI_ADDR_WIDTH
pars.AXI_RDATA_WIDTH["value"] = AXI_DATA_WIDTH
pars.AXI_WDATA_WIDTH["value"] = AXI_DATA_WIDTH
pars.SLAVE_NUM["value"] = AXI_SLAVE_NUM

# axis_interconnect模块设置
pars = axis_interconnect.parameter
pars.AXIS_TID_WIDTH["value"] = AXIS_TID_WIDTH
pars.AXIS_TDEST_WIDTH["value"] = AXIS_TDEST_WIDTH
pars.SLAVE_NUM["value"] = AXIS_SLAVE_NUM

# sig_mix_wrapper模块设置
pars = mix_sig_wrapper.parameter
pars.DATA_WIDTH["value"] = DATA_WIDTH
pars.AXI_ARADDR_WIDTH["value"] = AXI_ADDR_WIDTH
pars.AXI_AWADDR_WIDTH["value"] = AXI_ADDR_WIDTH
pars.AXI_RDATA_WIDTH["value"] = AXI_DATA_WIDTH
pars.AXI_WDATA_WIDTH["value"] = AXI_DATA_WIDTH

# axis_afifo模块设置
pars = axis_afifo.parameter
pars.CDC_STAGES["value"] = 5
pars.DEPTH_WIDTH["value"] = 10
pars.DATA_WIDTH["value"] = DATA_WIDTH

# fft_wrapper模块设置
pars = fft_wrapper.parameter
pars.DATA_WIDTH["value"] = DATA_WIDTH
pars.AXI_ARADDR_WIDTH["value"] = AXI_ADDR_WIDTH
pars.AXI_AWADDR_WIDTH["value"] = AXI_ADDR_WIDTH
pars.AXI_RDATA_WIDTH["value"] = AXI_DATA_WIDTH
pars.AXI_WDATA_WIDTH["value"] = AXI_DATA_WIDTH

# 注册并更新参数
hdll += mods

# clk 连接
hdll.setTop("top")\
- "bus" \
+ (top.input.clk , dcp2axisl.input.clk) \
+ (top.input.clk , drm_base_proc_wrapper.input.clk) \
+ (top.input.clk , axi_interconnect.input.clk) \
+ (top.input.clk , axis_interconnect.input.clk) \
+ (top.input.clk , mix_sig_wrapper.input.clk) \
+ (top.input.clk , fft_wrapper.input.clk) \
+ (top.input.clk , axis_afifo.input.m_clk) \
+ (top.input.clk , axis_afifo.input.s_clk)

# rst 连接
hdll \
+ (top.input.rst, dcp2axisl.input.rst) \
+ (top.input.rst, drm_base_proc_wrapper.input.rst) \
+ (top.input.rst, axi_interconnect.input.rst) \
+ (top.input.rst, axis_interconnect.input.rst) \
+ (top.input.rst, mix_sig_wrapper.input.rst) \
+ (top.input.rst, fft_wrapper.input.rst) \
+ (top.input.rst, axis_afifo.input.rst)

# top -> dcp2axisl
hdll \
%   (top , dcp2axisl , top_in_axis_con)
# dcp2axisl -> axi_interconnect
hdll \
% (dcp2axisl , axi_interconnect , axi_con)

# dcp2axisl -> axis_interconnect
hdll \
% (dcp2axisl , axis_interconnect , inter_axis_con)

# axi_interconnect -> drm_base_proc_wrapper
hdll \
% (axi_interconnect , drm_base_proc_wrapper , axi_con)

# axi_interconnect -> am_proc_wrapper
hdll \
% (axi_interconnect , am_proc_wrapper , axi_con)

# axis_interconnect -> drm_base_proc_wrapper am_proc_wrapper 
hdll \
% (axis_interconnect , fft_wrapper , test_axis_con) \
% (axis_interconnect , drm_base_proc_wrapper , inter_axis_con) \
% (axis_interconnect , am_proc_wrapper , inter_axis_con)

# fft_wrapper -> axis_afifo
hdll \
+ (fft_wrapper.output.im_axis_tdata , axis_afifo.input.s_axis_fifo_tdata)  \
+ (fft_wrapper.output.im_axis_tvalid , axis_afifo.input.s_axis_fifo_tvalid)  \
+ (fft_wrapper.input.im_axis_tready , axis_afifo.output.s_axis_fifo_tready)  \
    
# axis_affio -> drm_base_proc_wrapper
hdll \
+ (axis_afifo.output.m_axis_fifo_tdata , drm_base_proc_wrapper.input.is_axis_tdata)  \
+ (axis_afifo.output.m_axis_fifo_tvalid , drm_base_proc_wrapper.input.is_axis_tvalid)  \
+ (drm_base_proc_wrapper.output.is_axis_tready , axis_afifo.input.m_axis_fifo_tready)  \

# drm_base_proc_wrapper -> mix_sig_wrapper
hdll \
% (drm_base_proc_wrapper , mix_sig_wrapper , inner_axis_con) \

# am_proc_wrapper -> mix_sig_wrapper
hdll \
% (am_proc_wrapper , mix_sig_wrapper , inner_axis_con)

# sig_mix_wrapper -> top
hdll \
% (mix_sig_wrapper , top , test_top_out_axis_con)




# 编译连接
context , log = hdll.create()
if "ERROR" in log:
    print(log)
else:
    with open("../top.sv",'w') as f:
        f.write(context)
        print("Generate top.sv success!")