<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.8.0" version="1.0">
  This file is intended to be loaded by Logisim-evolution v3.8.0(https://github.com/logisim-evolution/).

  <lib desc="#Wiring" name="0">
    <tool name="Pin">
      <a name="appearance" val="classic"/>
    </tool>
  </lib>
  <lib desc="#Gates" name="1"/>
  <lib desc="#Plexers" name="2"/>
  <lib desc="#Arithmetic" name="3"/>
  <lib desc="#Memory" name="4"/>
  <lib desc="#I/O" name="5"/>
  <lib desc="#TTL" name="6"/>
  <lib desc="#TCL" name="7"/>
  <lib desc="#Base" name="8"/>
  <lib desc="#BFH-Praktika" name="9"/>
  <lib desc="#Input/Output-Extra" name="10"/>
  <lib desc="#Soc" name="11"/>
  <main name="lsu"/>
  <options>
    <a name="gateUndefined" val="ignore"/>
    <a name="simlimit" val="1000"/>
    <a name="simrand" val="0"/>
  </options>
  <mappings>
    <tool lib="8" map="Button2" name="Poke Tool"/>
    <tool lib="8" map="Button3" name="Menu Tool"/>
    <tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
  </mappings>
  <toolbar>
    <tool lib="8" name="Poke Tool"/>
    <tool lib="8" name="Edit Tool"/>
    <tool lib="8" name="Wiring Tool"/>
    <tool lib="8" name="Text Tool"/>
    <sep/>
    <tool lib="0" name="Pin"/>
    <tool lib="0" name="Pin">
      <a name="facing" val="west"/>
      <a name="output" val="true"/>
    </tool>
    <sep/>
    <tool lib="1" name="NOT Gate"/>
    <tool lib="1" name="AND Gate"/>
    <tool lib="1" name="OR Gate"/>
    <tool lib="1" name="XOR Gate"/>
    <tool lib="1" name="NAND Gate"/>
    <tool lib="1" name="NOR Gate"/>
    <sep/>
    <tool lib="4" name="D Flip-Flop"/>
    <tool lib="4" name="Register"/>
  </toolbar>
  <circuit name="lsu">
    <a name="appearance" val="custom"/>
    <a name="circuit" val="lsu"/>
    <a name="circuitnamedboxfixedsize" val="true"/>
    <a name="simulationFrequency" val="2048000.0"/>
    <appear>
      <rect height="4" stroke="none" width="10" x="50" y="58"/>
      <rect height="4" stroke="none" width="10" x="50" y="78"/>
      <rect height="4" stroke="none" width="10" x="50" y="98"/>
      <rect height="3" stroke="none" width="10" x="50" y="119"/>
      <rect height="3" stroke="none" width="10" x="50" y="139"/>
      <rect height="3" stroke="none" width="10" x="50" y="159"/>
      <rect height="4" stroke="none" width="10" x="50" y="178"/>
      <rect height="3" stroke="none" width="10" x="50" y="199"/>
      <rect height="3" stroke="none" width="10" x="50" y="219"/>
      <rect height="3" stroke="none" width="10" x="50" y="239"/>
      <rect height="3" stroke="none" width="10" x="50" y="259"/>
      <rect height="4" stroke="none" width="10" x="260" y="58"/>
      <rect height="4" stroke="none" width="10" x="260" y="78"/>
      <rect height="3" stroke="none" width="10" x="260" y="99"/>
      <rect height="4" stroke="none" width="10" x="260" y="118"/>
      <rect height="3" stroke="none" width="10" x="260" y="139"/>
      <rect height="4" stroke="none" width="10" x="260" y="158"/>
      <rect height="4" stroke="none" width="10" x="260" y="178"/>
      <rect height="20" stroke="none" width="200" x="60" y="270"/>
      <rect fill="none" height="240" stroke="#000000" stroke-width="2" width="200" x="60" y="50"/>
      <text dominant-baseline="alphabetic" fill="#ffffff" font-family="Courier 10 Pitch" font-size="14" font-weight="bold" text-anchor="middle" x="160" y="284">lsu</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="end" x="255" y="164">lsu_out</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="end" x="255" y="124">m_r_addr</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="204">m_w_ready</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="124">enable</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="64">rt</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="end" x="255" y="84">m_w_addr</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="164">d_m_w_e</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="end" x="255" y="104">m_w_v</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="224">m_r_ready</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="264">clk</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="end" x="255" y="184">lus_state</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="end" x="255" y="144">m_r_v</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="184">core_state</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="144">d_m_r_e</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="end" x="255" y="64">mem_w_data</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="84">rs</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="104">mem_r_data</text>
      <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="244">reset</text>
      <circ-anchor facing="east" x="270" y="60"/>
      <circ-port dir="in" pin="1090,770" x="50" y="100"/>
      <circ-port dir="in" pin="470,1110" x="50" y="200"/>
      <circ-port dir="in" pin="470,1150" x="50" y="220"/>
      <circ-port dir="in" pin="500,1280" x="50" y="240"/>
      <circ-port dir="in" pin="500,1330" x="50" y="260"/>
      <circ-port dir="in" pin="590,930" x="50" y="140"/>
      <circ-port dir="in" pin="590,970" x="50" y="160"/>
      <circ-port dir="in" pin="600,1010" x="50" y="180"/>
      <circ-port dir="in" pin="770,910" x="50" y="120"/>
      <circ-port dir="in" pin="960,300" x="50" y="80"/>
      <circ-port dir="in" pin="970,170" x="50" y="60"/>
      <circ-port dir="out" pin="1250,560" x="270" y="120"/>
      <circ-port dir="out" pin="1250,770" x="270" y="160"/>
      <circ-port dir="out" pin="1260,1160" x="270" y="180"/>
      <circ-port dir="out" pin="1260,170" x="270" y="60"/>
      <circ-port dir="out" pin="1260,300" x="270" y="80"/>
      <circ-port dir="out" pin="1260,390" x="270" y="100"/>
      <circ-port dir="out" pin="1260,690" x="270" y="140"/>
    </appear>
    <comp lib="0" loc="(1030,1250)" name="Tunnel">
      <a name="facing" val="east"/>
      <a name="label" val="clk"/>
    </comp>
    <comp lib="0" loc="(1080,1250)" name="Tunnel">
      <a name="label" val="reset"/>
    </comp>
    <comp lib="0" loc="(1090,770)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="label" val="mem_read_data"/>
      <a name="width" val="8"/>
    </comp>
    <comp lib="0" loc="(1120,810)" name="Tunnel">
      <a name="facing" val="east"/>
      <a name="label" val="clk"/>
    </comp>
    <comp lib="0" loc="(1230,870)" name="Tunnel">
      <a name="label" val="reset"/>
    </comp>
    <comp lib="0" loc="(1240,1090)" name="Tunnel">
      <a name="label" val="lsu_state"/>
      <a name="width" val="2"/>
    </comp>
    <comp lib="0" loc="(1250,560)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="facing" val="west"/>
      <a name="label" val="mem_read_address"/>
      <a name="output" val="true"/>
      <a name="width" val="8"/>
    </comp>
    <comp lib="0" loc="(1250,770)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="facing" val="west"/>
      <a name="label" val="lsu_out"/>
      <a name="output" val="true"/>
      <a name="width" val="8"/>
    </comp>
    <comp lib="0" loc="(1260,1160)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="facing" val="west"/>
      <a name="label" val="lus_state"/>
      <a name="output" val="true"/>
      <a name="width" val="2"/>
    </comp>
    <comp lib="0" loc="(1260,170)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="facing" val="west"/>
      <a name="label" val="mem_write_data"/>
      <a name="output" val="true"/>
      <a name="width" val="8"/>
    </comp>
    <comp lib="0" loc="(1260,300)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="facing" val="west"/>
      <a name="label" val="mem_write_address"/>
      <a name="output" val="true"/>
      <a name="width" val="8"/>
    </comp>
    <comp lib="0" loc="(1260,390)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="facing" val="west"/>
      <a name="label" val="mem_write_valid"/>
      <a name="output" val="true"/>
    </comp>
    <comp lib="0" loc="(1260,690)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="facing" val="west"/>
      <a name="label" val="mem_read_valid"/>
      <a name="output" val="true"/>
    </comp>
    <comp lib="0" loc="(470,1110)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="label" val="mem_write_ready"/>
    </comp>
    <comp lib="0" loc="(470,1150)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="label" val="mem_read_ready"/>
    </comp>
    <comp lib="0" loc="(500,1280)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="label" val="reset"/>
    </comp>
    <comp lib="0" loc="(500,1330)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="label" val="clk"/>
    </comp>
    <comp lib="0" loc="(560,1280)" name="Tunnel">
      <a name="label" val="reset"/>
    </comp>
    <comp lib="0" loc="(560,1330)" name="Tunnel">
      <a name="label" val="clk"/>
    </comp>
    <comp lib="0" loc="(590,750)" name="Tunnel">
      <a name="facing" val="east"/>
      <a name="label" val="lsu_state"/>
      <a name="width" val="2"/>
    </comp>
    <comp lib="0" loc="(590,930)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="label" val="decoded_mem_read_enable"/>
    </comp>
    <comp lib="0" loc="(590,970)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="label" val="decoded_mem_write_enable"/>
    </comp>
    <comp lib="0" loc="(600,1010)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="label" val="core_state"/>
      <a name="width" val="3"/>
    </comp>
    <comp lib="0" loc="(640,1190)" name="Constant">
      <a name="value" val="0x3"/>
      <a name="width" val="2"/>
    </comp>
    <comp lib="0" loc="(640,1240)" name="Constant">
      <a name="value" val="0x0"/>
      <a name="width" val="2"/>
    </comp>
    <comp lib="0" loc="(740,1150)" name="Constant">
      <a name="value" val="0x2"/>
      <a name="width" val="2"/>
    </comp>
    <comp lib="0" loc="(770,910)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="label" val="enable"/>
    </comp>
    <comp lib="0" loc="(790,1070)" name="Bit Extender">
      <a name="in_width" val="1"/>
      <a name="out_width" val="2"/>
      <a name="type" val="zero"/>
    </comp>
    <comp lib="0" loc="(960,300)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="label" val="rs"/>
      <a name="width" val="8"/>
    </comp>
    <comp lib="0" loc="(970,170)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="label" val="rt"/>
      <a name="width" val="8"/>
    </comp>
    <comp lib="1" loc="(550,1130)" name="OR Gate"/>
    <comp lib="1" loc="(730,410)" name="AND Gate"/>
    <comp lib="1" loc="(740,950)" name="OR Gate"/>
    <comp lib="1" loc="(760,710)" name="AND Gate"/>
    <comp lib="1" loc="(760,770)" name="AND Gate">
      <a name="inputs" val="3"/>
    </comp>
    <comp lib="1" loc="(810,460)" name="AND Gate"/>
    <comp lib="1" loc="(860,930)" name="AND Gate"/>
    <comp lib="1" loc="(870,720)" name="OR Gate"/>
    <comp lib="1" loc="(900,410)" name="OR Gate"/>
    <comp lib="2" loc="(600,720)" name="Decoder">
      <a name="select" val="2"/>
    </comp>
    <comp lib="2" loc="(620,1040)" name="Decoder">
      <a name="select" val="3"/>
      <a name="selloc" val="tr"/>
    </comp>
    <comp lib="2" loc="(730,1230)" name="Multiplexer">
      <a name="selloc" val="tr"/>
      <a name="width" val="2"/>
    </comp>
    <comp lib="2" loc="(810,1180)" name="Multiplexer">
      <a name="selloc" val="tr"/>
      <a name="width" val="2"/>
    </comp>
    <comp lib="2" loc="(990,1160)" name="Multiplexer">
      <a name="enable" val="true"/>
      <a name="select" val="2"/>
      <a name="selloc" val="tr"/>
      <a name="width" val="2"/>
    </comp>
    <comp lib="4" loc="(1050,1130)" name="Register">
      <a name="appearance" val="logisim_evolution"/>
      <a name="label" val="lsu_state_reg"/>
      <a name="width" val="2"/>
    </comp>
    <comp lib="4" loc="(1140,140)" name="Register">
      <a name="appearance" val="logisim_evolution"/>
      <a name="label" val="mem_write_data_reg"/>
    </comp>
    <comp lib="4" loc="(1140,270)" name="Register">
      <a name="appearance" val="logisim_evolution"/>
      <a name="label" val="mem_write_address_reg"/>
    </comp>
    <comp lib="4" loc="(1140,530)" name="Register">
      <a name="appearance" val="logisim_evolution"/>
      <a name="label" val="mem_read_address_reg"/>
    </comp>
    <comp lib="4" loc="(1150,740)" name="Register">
      <a name="appearance" val="logisim_evolution"/>
      <a name="label" val="lsu_out_reg"/>
    </comp>
    <comp lib="4" loc="(900,360)" name="Register">
      <a name="appearance" val="logisim_evolution"/>
      <a name="label" val="mem_write_valid_reg"/>
      <a name="width" val="1"/>
    </comp>
    <comp lib="4" loc="(900,660)" name="Register">
      <a name="appearance" val="logisim_evolution"/>
      <a name="label" val="mem_read_valid_reg"/>
      <a name="width" val="1"/>
    </comp>
    <wire from="(1000,1070)" to="(1000,1180)"/>
    <wire from="(1000,1180)" to="(1050,1180)"/>
    <wire from="(1000,190)" to="(1000,320)"/>
    <wire from="(1000,190)" to="(1140,190)"/>
    <wire from="(1000,320)" to="(1140,320)"/>
    <wire from="(1000,930)" to="(1000,1070)"/>
    <wire from="(1030,1200)" to="(1030,1250)"/>
    <wire from="(1030,1200)" to="(1050,1200)"/>
    <wire from="(1030,300)" to="(1030,560)"/>
    <wire from="(1030,300)" to="(1140,300)"/>
    <wire from="(1030,560)" to="(1140,560)"/>
    <wire from="(1080,1220)" to="(1080,1250)"/>
    <wire from="(1090,770)" to="(1150,770)"/>
    <wire from="(1110,1160)" to="(1170,1160)"/>
    <wire from="(1120,210)" to="(1120,340)"/>
    <wire from="(1120,210)" to="(1140,210)"/>
    <wire from="(1120,340)" to="(1120,460)"/>
    <wire from="(1120,340)" to="(1140,340)"/>
    <wire from="(1120,460)" to="(1120,600)"/>
    <wire from="(1120,600)" to="(1120,760)"/>
    <wire from="(1120,600)" to="(1140,600)"/>
    <wire from="(1120,760)" to="(1120,810)"/>
    <wire from="(1120,810)" to="(1150,810)"/>
    <wire from="(1170,1090)" to="(1170,1160)"/>
    <wire from="(1170,1090)" to="(1240,1090)"/>
    <wire from="(1170,1160)" to="(1260,1160)"/>
    <wire from="(1170,230)" to="(1220,230)"/>
    <wire from="(1170,360)" to="(1220,360)"/>
    <wire from="(1170,620)" to="(1220,620)"/>
    <wire from="(1180,830)" to="(1220,830)"/>
    <wire from="(1200,170)" to="(1260,170)"/>
    <wire from="(1200,300)" to="(1260,300)"/>
    <wire from="(1200,560)" to="(1250,560)"/>
    <wire from="(1210,770)" to="(1250,770)"/>
    <wire from="(1220,230)" to="(1220,360)"/>
    <wire from="(1220,360)" to="(1220,510)"/>
    <wire from="(1220,510)" to="(1220,620)"/>
    <wire from="(1220,620)" to="(1220,830)"/>
    <wire from="(1220,830)" to="(1220,870)"/>
    <wire from="(1220,870)" to="(1230,870)"/>
    <wire from="(470,1110)" to="(480,1110)"/>
    <wire from="(470,1150)" to="(490,1150)"/>
    <wire from="(480,1110)" to="(500,1110)"/>
    <wire from="(480,440)" to="(480,1110)"/>
    <wire from="(480,440)" to="(760,440)"/>
    <wire from="(490,1150)" to="(500,1150)"/>
    <wire from="(490,790)" to="(490,1150)"/>
    <wire from="(490,790)" to="(710,790)"/>
    <wire from="(500,1280)" to="(560,1280)"/>
    <wire from="(500,1330)" to="(560,1330)"/>
    <wire from="(550,1130)" to="(790,1130)"/>
    <wire from="(590,750)" to="(600,750)"/>
    <wire from="(590,930)" to="(680,930)"/>
    <wire from="(590,970)" to="(650,970)"/>
    <wire from="(600,1010)" to="(620,1010)"/>
    <wire from="(600,720)" to="(600,750)"/>
    <wire from="(620,1010)" to="(620,1040)"/>
    <wire from="(620,690)" to="(680,690)"/>
    <wire from="(620,700)" to="(670,700)"/>
    <wire from="(640,1070)" to="(750,1070)"/>
    <wire from="(640,1100)" to="(710,1100)"/>
    <wire from="(640,1190)" to="(690,1190)"/>
    <wire from="(640,1240)" to="(700,1240)"/>
    <wire from="(650,390)" to="(650,970)"/>
    <wire from="(650,390)" to="(680,390)"/>
    <wire from="(650,970)" to="(690,970)"/>
    <wire from="(670,480)" to="(670,700)"/>
    <wire from="(670,480)" to="(760,480)"/>
    <wire from="(670,700)" to="(700,700)"/>
    <wire from="(680,430)" to="(680,690)"/>
    <wire from="(680,690)" to="(710,690)"/>
    <wire from="(680,730)" to="(680,770)"/>
    <wire from="(680,730)" to="(710,730)"/>
    <wire from="(680,770)" to="(680,930)"/>
    <wire from="(680,770)" to="(710,770)"/>
    <wire from="(680,930)" to="(690,930)"/>
    <wire from="(690,1190)" to="(690,1220)"/>
    <wire from="(690,1190)" to="(780,1190)"/>
    <wire from="(690,1220)" to="(700,1220)"/>
    <wire from="(700,700)" to="(700,750)"/>
    <wire from="(700,750)" to="(710,750)"/>
    <wire from="(710,1100)" to="(710,1210)"/>
    <wire from="(730,1230)" to="(850,1230)"/>
    <wire from="(730,410)" to="(780,410)"/>
    <wire from="(740,1150)" to="(760,1150)"/>
    <wire from="(740,950)" to="(810,950)"/>
    <wire from="(760,1150)" to="(760,1170)"/>
    <wire from="(760,1150)" to="(950,1150)"/>
    <wire from="(760,1170)" to="(780,1170)"/>
    <wire from="(760,710)" to="(780,710)"/>
    <wire from="(760,770)" to="(800,770)"/>
    <wire from="(770,910)" to="(810,910)"/>
    <wire from="(780,320)" to="(1000,320)"/>
    <wire from="(780,320)" to="(780,390)"/>
    <wire from="(780,390)" to="(780,410)"/>
    <wire from="(780,390)" to="(850,390)"/>
    <wire from="(780,580)" to="(1140,580)"/>
    <wire from="(780,580)" to="(780,690)"/>
    <wire from="(780,690)" to="(780,700)"/>
    <wire from="(780,690)" to="(900,690)"/>
    <wire from="(780,700)" to="(780,710)"/>
    <wire from="(780,700)" to="(820,700)"/>
    <wire from="(790,1070)" to="(920,1070)"/>
    <wire from="(790,1130)" to="(790,1160)"/>
    <wire from="(800,740)" to="(800,770)"/>
    <wire from="(800,740)" to="(820,740)"/>
    <wire from="(800,770)" to="(860,770)"/>
    <wire from="(810,1180)" to="(830,1180)"/>
    <wire from="(810,460)" to="(830,460)"/>
    <wire from="(830,1160)" to="(830,1180)"/>
    <wire from="(830,1160)" to="(950,1160)"/>
    <wire from="(830,430)" to="(830,460)"/>
    <wire from="(830,430)" to="(850,430)"/>
    <wire from="(850,1170)" to="(850,1230)"/>
    <wire from="(850,1170)" to="(950,1170)"/>
    <wire from="(850,390)" to="(900,390)"/>
    <wire from="(860,770)" to="(860,790)"/>
    <wire from="(860,790)" to="(1150,790)"/>
    <wire from="(860,930)" to="(1000,930)"/>
    <wire from="(870,720)" to="(900,720)"/>
    <wire from="(900,430)" to="(900,460)"/>
    <wire from="(900,460)" to="(1120,460)"/>
    <wire from="(900,710)" to="(900,720)"/>
    <wire from="(900,730)" to="(900,760)"/>
    <wire from="(900,760)" to="(1120,760)"/>
    <wire from="(920,1070)" to="(920,1140)"/>
    <wire from="(920,1140)" to="(950,1140)"/>
    <wire from="(930,450)" to="(930,510)"/>
    <wire from="(930,510)" to="(1220,510)"/>
    <wire from="(930,750)" to="(930,870)"/>
    <wire from="(930,870)" to="(1220,870)"/>
    <wire from="(960,300)" to="(1030,300)"/>
    <wire from="(960,390)" to="(1260,390)"/>
    <wire from="(960,690)" to="(1260,690)"/>
    <wire from="(970,1090)" to="(1170,1090)"/>
    <wire from="(970,1090)" to="(970,1140)"/>
    <wire from="(970,170)" to="(1140,170)"/>
    <wire from="(980,1070)" to="(1000,1070)"/>
    <wire from="(980,1070)" to="(980,1140)"/>
    <wire from="(990,1160)" to="(1050,1160)"/>
  </circuit>
</project>