Running: D:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o D:/Jayvee/H_264_Decoder/IQIT_TEST_isim_beh.exe -prj D:/Jayvee/H_264_Decoder/IQIT_TEST_beh.prj work.IQIT_TEST work.glbl 
ISim P.20131013 (signature 0x8ef4fb42)
Number of CPUs detected in this system: 2
Turning on mult-threading, number of parallel sub-compilation jobs: 4 
Determining compilation order of HDL files
Analyzing Verilog file "D:/Jayvee/H_264_Decoder/mod6.v" into library work
Analyzing Verilog file "D:/Jayvee/H_264_Decoder/Vij_lut.v" into library work
Analyzing Verilog file "D:/Jayvee/H_264_Decoder/IQ_shift.v" into library work
Analyzing Verilog file "D:/Jayvee/H_264_Decoder/div6.v" into library work
Analyzing Verilog file "D:/Jayvee/H_264_Decoder/butterfly.v" into library work
Analyzing Verilog file "D:/Jayvee/H_264_Decoder/IT_BUT_ARRAY.v" into library work
Analyzing Verilog file "D:/Jayvee/H_264_Decoder/IT_4X4REG.v" into library work
Analyzing Verilog file "D:/Jayvee/H_264_Decoder/IQ_control.v" into library work
Analyzing Verilog file "D:/Jayvee/H_264_Decoder/IQ_calc.v" into library work
Analyzing Verilog file "D:/Jayvee/H_264_Decoder/IT_output_reg.v" into library work
Analyzing Verilog file "D:/Jayvee/H_264_Decoder/IT_module.v" into library work
Analyzing Verilog file "D:/Jayvee/H_264_Decoder/IT_input_mux.v" into library work
Analyzing Verilog file "D:/Jayvee/H_264_Decoder/IQ_module.v" into library work
Analyzing Verilog file "D:/Jayvee/H_264_Decoder/IQIT_control.v" into library work
Analyzing Verilog file "D:/Jayvee/H_264_Decoder/IQIT_module.v" into library work
Analyzing Verilog file "D:/Jayvee/H_264_Decoder/IQIT_TEST.v" into library work
Analyzing Verilog file "D:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 102128 KB
Fuse CPU Usage: 390 ms
Compiling module IQIT_control
Compiling module IT_4X4Reg
Compiling module IQIT_output_reg
Compiling module div6
Compiling module mod6
Compiling module Vij_lut(Pos_iv=0,Pos_jv=0)
Compiling module IQ_control(Pos_ic=0,Pos_jc=0)
Compiling module IQ_shift
Compiling module IQ_calc
Compiling module IQ_module(Pos_i=0,Pos_j=0)
Compiling module Vij_lut(Pos_iv=0,Pos_jv=1)
Compiling module IQ_control(Pos_ic=0,Pos_jc=1)
Compiling module IQ_module(Pos_i=0,Pos_j=1)
Compiling module Vij_lut(Pos_iv=0,Pos_jv=2)
Compiling module IQ_control(Pos_ic=0,Pos_jc=2)
Compiling module IQ_module(Pos_i=0,Pos_j=2)
Compiling module Vij_lut(Pos_iv=0,Pos_jv=3)
Compiling module IQ_control(Pos_ic=0,Pos_jc=3)
Compiling module IQ_module(Pos_i=0,Pos_j=3)
Compiling module Vij_lut(Pos_iv=1,Pos_jv=0)
Compiling module IQ_control(Pos_ic=1,Pos_jc=0)
Compiling module IQ_module(Pos_i=1,Pos_j=0)
Compiling module Vij_lut(Pos_iv=1,Pos_jv=1)
Compiling module IQ_control(Pos_ic=1,Pos_jc=1)
Compiling module IQ_module(Pos_i=1,Pos_j=1)
Compiling module Vij_lut(Pos_iv=1,Pos_jv=2)
Compiling module IQ_control(Pos_ic=1,Pos_jc=2)
Compiling module IQ_module(Pos_i=1,Pos_j=2)
Compiling module Vij_lut(Pos_iv=1,Pos_jv=3)
Compiling module IQ_control(Pos_ic=1,Pos_jc=3)
Compiling module IQ_module(Pos_i=1,Pos_j=3)
Compiling module Vij_lut(Pos_iv=2,Pos_jv=0)
Compiling module IQ_control(Pos_ic=2,Pos_jc=0)
Compiling module IQ_module(Pos_i=2,Pos_j=0)
Compiling module Vij_lut(Pos_iv=2,Pos_jv=1)
Compiling module IQ_control(Pos_ic=2,Pos_jc=1)
Compiling module IQ_module(Pos_i=2,Pos_j=1)
Compiling module Vij_lut(Pos_iv=2,Pos_jv=2)
Compiling module IQ_control(Pos_ic=2,Pos_jc=2)
Compiling module IQ_module(Pos_i=2,Pos_j=2)
Compiling module Vij_lut(Pos_iv=2,Pos_jv=3)
Compiling module IQ_control(Pos_ic=2,Pos_jc=3)
Compiling module IQ_module(Pos_i=2,Pos_j=3)
Compiling module Vij_lut(Pos_iv=3,Pos_jv=0)
Compiling module IQ_control(Pos_ic=3,Pos_jc=0)
Compiling module IQ_module(Pos_i=3,Pos_j=0)
Compiling module Vij_lut(Pos_iv=3,Pos_jv=1)
Compiling module IQ_control(Pos_ic=3,Pos_jc=1)
Compiling module IQ_module(Pos_i=3,Pos_j=1)
Compiling module Vij_lut(Pos_iv=3,Pos_jv=2)
Compiling module IQ_control(Pos_ic=3,Pos_jc=2)
Compiling module IQ_module(Pos_i=3,Pos_j=2)
Compiling module Vij_lut(Pos_iv=3,Pos_jv=3)
Compiling module IQ_control(Pos_ic=3,Pos_jc=3)
Compiling module IQ_module(Pos_i=3,Pos_j=3)
Compiling module butterfly
Compiling module IT_BUT_ARRAY
Compiling module IT_module
Compiling module IQIT_input_mux
Compiling module IQIT_module
Compiling module IQIT_TEST
Compiling module glbl
Time Resolution for simulation is 1ps.
Waiting for 31 sub-compilation(s) to finish...
Compiled 62 Verilog Units
Built simulation executable D:/Jayvee/H_264_Decoder/IQIT_TEST_isim_beh.exe
Fuse Memory Usage: 107744 KB
Fuse CPU Usage: 1278 ms