`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:31:29 12/04/2013 
// Design Name: 
// Module Name:    IT_control 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
// 反变换控制模块,
// 可能出现的问题：IT_4X4Reg,的写信号和数据输入信号不知道会不会造成时间不一致（时钟传输延时）而导致写入错误。
//////////////////////////////////////////////////////////////////////////////////
module IT_control(
    Rst,//异步复位信号(低电平有效)
    OneD_clk,//行变换时钟
    //OneD_state,//行变换使能（高电平有效）
    TwoD_clk,//列变换时钟
    //TwoD_state,//列变换使能（高电平有效）
    i_Blk,//变换块编号（-1~25）
    DCT_or_HDT,//DCT变换还是Hadaman变换（0--DCT，1--HDT）
    //Input_mux,//输入数据选择器
    Output_load,//输出寄存器选择(0--4X4直流Luma_DCR,1--4X4交流变换结果OneDR，2--2X2直流Cb_DCR，3--2X2直流Cr_DCR)
    Cycle_num,//运算周期计数输出
    //Reg_clr,//同步清零信号(高电平有效)
    //Reg_w,//同步写信号(高电平有效)
    Num//写入行号（列号）
    );
    input Rst;
    input OneD_clk;
    //input OneD_state;
    input TwoD_clk;
    //input TwoD_state;
    input [4:0] i_Blk;
    
    output DCT_or_HDT;
    output [2:0] Cycle_num;
    //output Reg_clr;
    //output Reg_w;
    output [1:0] Num;
    //output [2:0] Input_mux;
    output [1:0] Output_load;
    
    wire Num;
    reg [2:0] Cycle_num;
    reg DCT_or_HDT;
    //reg [2:0] Cycle_num_t;
    reg [1:0] Output_load;
    reg [2:0] OneD_counter;
    reg [2:0] TwoD_counter;
    
    always @(posedge OneD_clk or negedge Rst) begin
        if(!Rst) begin
            OneD_counter <= 0;
        end
        else begin
            if((Output_load==2'b00)||(Output_load==2'b01)) begin//4X4要4次行变换
                OneD_counter <= (OneD_counter == 0)?3'b100:(OneD_counter-1);
            end
            else begin //2x2块时只要一个周期
                OneD_counter <= (OneD_counter == 0)?3'b001:(OneD_counter-1);
            end            
        end
    end
    
    always @(posedge TwoD_clk or negedge Rst) begin
        if(!Rst) begin
            TwoD_counter <= 0;
        end
        else begin
            TwoD_counter <= (TwoD_counter == 0)? 3'b100:(TwoD_counter - 1);
        end
    end
    
    always @(Cycle_num or OneD_counter or TwoD_counter) begin
        if((OneD_counter==0)&&(TwoD_counter==0))
            Cycle_num = 0;
        else if((OneD_counter==4)&&(TwoD_counter==0))
            Cycle_num = 0;
        else if((OneD_counter==3)&&(TwoD_counter==0))
            Cycle_num = 1;
        else if((OneD_counter==2)&&(TwoD_counter==0))
            Cycle_num = 2;
        else if((OneD_counter==1)&&(TwoD_counter==0))
            Cycle_num = 3;
        else if((OneD_counter==0)&&(TwoD_counter==4))
            Cycle_num = 4;
        else if((OneD_counter==0)&&(TwoD_counter==3))
            Cycle_num = 5;
        else if((OneD_counter==0)&&(TwoD_counter==2))
            Cycle_num = 6;
        else if((OneD_counter==0)&&(TwoD_counter==1))
            Cycle_num = 7;
        else 
            Cycle_num = 0;
        
    end
    //根据块号决定进行DCT变换还是Hadaman变换
    //决定Output_load块数据类型
    always @(i_Blk or DCT_or_HDT) begin
        case(i_Blk) 
        5'b11111: begin
            DCT_or_HDT = 1;
            Output_load = 0;
        end    
        0,1,2,3,4,5,6,7,8,9,10,11,12,
        13,14,15: begin
            DCT_or_HDT = 0;
            Output_load = 1;
        end
        16,17: begin
            Output_load = 2;
            DCT_or_HDT = 1;
        end
        18,19,20,21,22,23,24,25: begin
            DCT_or_HDT = 0;
            Output_load = 3;
        end
        default: begin
            DCT_or_HDT = 0;
            Output_load = 0;
        end
        endcase
    end
    
    assign Num = (Cycle_num>3'd3)?(Cycle_num-3'd4):Cycle_num;
    //assign Cycle_num = Cycle_num_t;
    
endmodule