`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:08:53 12/09/2013
// Design Name:   IQ_module
// Module Name:   D:/Jayvee/H_264_Decoder/IQ_module_test.v
// Project Name:  H_264_Decoder
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: IQ_module
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module IQ_module_test;

	// Inputs
	reg rescale_clk;
	reg rescale_state;
	reg Luma_or_Chro;
	reg isDirect;
	reg DC_or_AC;
	reg [5:0] QP;
	reg [15:0] Input;
    reg Rst;
    reg [4:0] cnt;
	// Outputs
	wire [15:0] Output;

	// Instantiate the Unit Under Test (UUT)
	IQ_module uut (
		.rescale_clk(rescale_clk), 
		.rescale_state(rescale_state), 
		.Luma_or_Chro(Luma_or_Chro), 
		.isDirect(isDirect), 
		.DC_or_AC(DC_or_AC), 
		.QP(QP), 
		.Input(Input), 
		.Output(Output)
	);

	initial begin
		// Initialize Inputs
		rescale_clk = 0;
		rescale_state = 0;
		Luma_or_Chro = 0;
		isDirect = 0;
		DC_or_AC = 0;
		QP = 0;
		Input = 0;
        cnt = 0;
        Rst = 0;
		// Wait 100 ns for global reset to finish
		#100;
        #10 Rst = 1;
		// Add stimulus here

	end
      
    always #20   rescale_clk = ~rescale_clk;
    
    always @(posedge rescale_clk or negedge Rst) begin
        if(!Rst) begin
            cnt <= 0;
        end
        else begin
            case(cnt)
            0:begin
                rescale_state <= 1;
                Luma_or_Chro <= 0;
                isDirect <= 0;
                DC_or_AC <= 1;
                QP <= 1;
                Input <= 374;
                cnt <= cnt + 1;
            end
            1:begin
                rescale_state <= 1;
                Luma_or_Chro <= 0;
                isDirect <= 1;
                DC_or_AC <= 1;
                QP <= 1;
                Input <= 374;
                cnt <= cnt + 1;
            end
            2:begin
                rescale_state <= 1;
                Luma_or_Chro <= 0;
                isDirect <= 1;
                DC_or_AC <= 1;
                QP <= 1;
                Input <= 374;
                cnt <= cnt;
            end
            endcase
        end
    end
      
endmodule