H.264_Decoder
/
IQIT_control.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    15:55:27 12/05/2013
// Design Name:
// Module Name:    IQIT_control
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module IQIT_control(
    Clk,//时钟
    Rst,//复位信号
    i_Blk,//块号
    Sig_start,//开始信号
    Sig_done,//完成信号
    isChroDC,//判断是否是2X2色度DC块（0--不是2X2块，1--是）
    Input_mux,//输出输入选择(0--4X4Level0_15,1--直流量+交流)
    rescale_clk,//输出反量化门控时钟
    gClk_it,//输出反变换门控时钟
    Output_load,//寄存器选择(0--4X4直流Luma_DCR,1--4X4OneDR，2--2X2直流Cb_DCR，3--2X2直流Cr_DCR)
    Luma_or_Chro,//（0--Luma，1--Chro）
    DC_or_AC,//（0--DC,1--AC）
    Reg_w,//写寄存器信号（高电平有效）
    //Reg_clr,//寄存器清零信号
    DCT_or_HDT,//（0--DCT,1--HDT）
    isDirect_it,//反变换直通（0--不直通，1--直通）
    isDirect_iq,//反量化直通（0--不直通，1--直通）
    rescale_state//量化使能
    //DEBUG
    ,
    current_state
    //
    );
    input Clk,Rst;
    input [4:0] i_Blk;
    input Sig_start;

    output Sig_done;
    output isChroDC;
    output Input_mux;
    output [1:0] Output_load;
    output Luma_or_Chro;
    output DC_or_AC;
    output Reg_w;
    //output Reg_clr;
    output DCT_or_HDT;
    output isDirect_it;
    output isDirect_iq;
    output rescale_state;
    output rescale_clk;
    output gClk_it;
    //DEBUG
    output [5:0] current_state;
    //
    reg isChroDC;
    reg Sig_done;
    reg rescale_state;
    reg DCT_or_HDT;
    reg Luma_or_Chro;
    reg DC_or_AC;
    //reg Reg_clr;
    reg Reg_w;
    reg isDirect_it;
    reg isDirect_iq;
    reg [1:0] Output_load;
    reg [5:0] current_state;
    reg [5:0] next_state;
    reg Input_mux;
    reg l_gClk_it_en;
    reg l_rescale_en;
    reg IDCT_flag;
    wire gClk_it;
    wire rescale_clk;
    wire gClk_it_en;
    wire rescale_en;

    parameter IDLE = 6'b000001;//空闲状态
    //parameter INIT = 4'b0010;
    parameter IHDT = 6'b000010;//反HDT变换状态
    parameter IQ = 6'b000100;//反量化状态
    parameter IDCT = 6'b001000;//反DCT变换
    parameter REG_WRITE = 6'b010000;//寄存器写入开始状态
    //parameter REG_W_DONE = 4'b0110;//寄存器写入结束状态
    parameter DONE = 6'b100000;//解码完成信号

    assign gClk_it_en = ((current_state==IHDT)||(current_state==IDCT)||(current_state==IQ))?1:0;
    assign rescale_en = (current_state==IQ)?1:0;
    //门控时钟产生电路
    always @(Clk or gClk_it_en) begin
        if (!Clk) l_gClk_it_en <= gClk_it_en;
        //else l_gClk_it_en <= 0;
    end
    assign gClk_it = Clk & l_gClk_it_en;

    always @ (Clk or rescale_en) begin
		if (!Clk) l_rescale_en <= rescale_en;
        //else l_rescale_en <= 0;
    end
	and gc_rescale (rescale_clk,Clk,l_rescale_en);

    always @(posedge Clk or negedge Rst) begin
		if(!Rst) begin
			current_state <= IDLE;
		end
		else begin
			current_state <= next_state;
		end
	end

    always @(i_Blk or Luma_or_Chro) begin
        case(i_Blk)
        5'b11111,0,1,2,3,4,5,6,7,8,9,10,
        11,12,13,14,15:begin
            Luma_or_Chro = 0;
        end
        16,17,18,19,20,21,22,23,24,25:begin
            Luma_or_Chro = 1;
        end
        default:Luma_or_Chro = 0;
        endcase
    end

    always @(i_Blk or DC_or_AC or isChroDC) begin
        case(i_Blk)
        5'b11111:begin
            DC_or_AC = 0;
            isChroDC = 0;
        end
        16,17:begin
            DC_or_AC = 0;
            isChroDC = 1;
        end
        0,1,2,3,4,5,6,7,8,9,10,
        11,12,13,14,15,18,19,20,
        21,22,23,24,25:begin
            DC_or_AC = 1;
            isChroDC = 0;
        end
        default: begin
            isChroDC = 0;
            DC_or_AC = 0;
        end
        endcase
    end

    always @(i_Blk or Output_load) begin
        case(i_Blk)
        5'b11111:begin
            Output_load = 0;
        end
        0,1,2,3,4,5,6,7,8,9,10,
        11,12,13,14,15:begin
            Output_load = 1;
        end
        16:begin
            Output_load = 2;
        end
        17:begin
            Output_load = 3;
        end
        18,19,20,21,22,23,24,25:begin
            Output_load = 1;
        end
        default:Output_load = 1;
        endcase
    end

    always @(current_state or next_state or Sig_done or Sig_start or i_Blk or IDCT_flag or isDirect_it or isDirect_iq) begin
        case(current_state)
        IDLE:begin
            if(Sig_start==1'b1) begin
                case(i_Blk)
                5'b11111,16,17: begin
                    next_state = IHDT;
                    isDirect_it = 0;
                    isDirect_iq = 0;
                end
                0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,
                18,19,20,21,22,23,24,25:begin
                    next_state = IQ;
                    isDirect_it = 1;
                    isDirect_iq = 0;
                end
                default: begin
                    next_state = IDLE;
                    isDirect_it = 0;
                    isDirect_iq = 0;
                end
                endcase
            end
            else begin
                next_state = IDLE;
                isDirect_it = 0;
                isDirect_iq = 0;
            end
        end
        //INIT:begin

        //end
        IHDT:begin
            next_state = IQ;
        end
        IQ:begin
            next_state = REG_WRITE;
        end
        IDCT:begin
            isDirect_iq = 1;
            next_state = REG_WRITE;
        end
        REG_WRITE:begin
            case(i_Blk)
            5'b11111,16,17:begin
                next_state = DONE;
            end
            0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,18,19,
            20,21,22,23,24,25:begin
                if(IDCT_flag==1'b0) begin//未进行IDCT
                    next_state = IDCT;
                    isDirect_it = 0;
                end
                else
                    next_state = DONE;
            end
            default:next_state = IDLE;
            endcase
        end
        DONE:begin
            next_state = IDLE;
        end
        default:begin
            next_state = IDLE;
        end
        endcase
    end

    always @(posedge Clk or negedge Rst) begin
    	if(!Rst) begin
        	Sig_done <= 0;
            Reg_w <= 0;
            Input_mux <= 0;
            DCT_or_HDT <= 1;
            //isDirect_it <= 0;
            //isDirect_iq <= 0;
            rescale_state <= 0;
            IDCT_flag <= 0;
        end
        else begin
        	case(next_state)
            IDLE:begin
                Sig_done <= 0;
                Reg_w <= 0;
                Input_mux <= 0;
                DCT_or_HDT <= 1;
                //isDirect_it <= 0;
                //isDirect_iq <= 0;
                rescale_state <= 0;
                IDCT_flag <= 0;
            end
            //INIT:begin

            //end
            IHDT:begin
                Input_mux <= 0;
                DCT_or_HDT <= 1;
                //isDirect_it <= 0;
                //isDirect_iq <= 0;
                rescale_state <= 1;
            end
            IQ:begin
                rescale_state <= 1;
                //case(i_Blk)
                //5'b11111,16,17:begin
                //    isDirect_it <= 0;
                //    isDirect_iq <= 0;
                //end
                //default:begin
                //    isDirect_it <= 1;
                //    isDirect_iq <= 0;
                //end
                //endcase

            end
            IDCT:begin
                rescale_state <= 0;
                Input_mux <= 1;
                DCT_or_HDT <= 0;
                //isDirect_it <= 0;
                //isDirect_iq <= 1;
                IDCT_flag <= 1;
            end
            REG_WRITE:begin
                Reg_w <= 1;
            end
            DONE:begin
                Reg_w <= 0;
                Sig_done <= 1;
                IDCT_flag <= 0;
            end
            default:begin
                Input_mux <= 0;
                Sig_done <= 0;
                IDCT_flag <= 0;
            end
            endcase
        end
    end


endmodule