H.264_Decoder
/
IQIT_TEST.v

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:   19:14:41 12/08/2013
// Design Name:   IQIT_module
// Module Name:   C:/Users/Jayvee/Desktop/H_264_Decoder/IQIT_TEST.v
// Project Name:  H_264_Decoder
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: IQIT_module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module IQIT_TEST;

	// Inputs
	reg Clk;
	reg Rst;
	reg [4:0] i_Blk;
	reg [5:0] QP;
	reg Sig_start;
	reg [15:0] Input_0;
	reg [15:0] Input_1;
	reg [15:0] Input_2;
	reg [15:0] Input_3;
	reg [15:0] Input_4;
	reg [15:0] Input_5;
	reg [15:0] Input_6;
	reg [15:0] Input_7;
	reg [15:0] Input_8;
	reg [15:0] Input_9;
	reg [15:0] Input_10;
	reg [15:0] Input_11;
	reg [15:0] Input_12;
	reg [15:0] Input_13;
	reg [15:0] Input_14;
	reg [15:0] Input_15;

	// Outputs
	wire Sig_done;
	wire [15:0] Luma_DCR0;
	wire [15:0] Luma_DCR1;
	wire [15:0] Luma_DCR2;
	wire [15:0] Luma_DCR3;
	wire [15:0] Luma_DCR4;
	wire [15:0] Luma_DCR5;
	wire [15:0] Luma_DCR6;
	wire [15:0] Luma_DCR7;
	wire [15:0] Luma_DCR8;
	wire [15:0] Luma_DCR9;
	wire [15:0] Luma_DCR10;
	wire [15:0] Luma_DCR11;
	wire [15:0] Luma_DCR12;
	wire [15:0] Luma_DCR13;
	wire [15:0] Luma_DCR14;
	wire [15:0] Luma_DCR15;
	wire [15:0] Cr_DCR0;
	wire [15:0] Cr_DCR1;
	wire [15:0] Cr_DCR2;
	wire [15:0] Cr_DCR3;
	wire [15:0] Cb_DCR0;
	wire [15:0] Cb_DCR1;
	wire [15:0] Cb_DCR2;
	wire [15:0] Cb_DCR3;
	wire [15:0] OneDR0;
	wire [15:0] OneDR1;
	wire [15:0] OneDR2;
	wire [15:0] OneDR3;
	wire [15:0] OneDR4;
	wire [15:0] OneDR5;
	wire [15:0] OneDR6;
	wire [15:0] OneDR7;
	wire [15:0] OneDR8;
	wire [15:0] OneDR9;
	wire [15:0] OneDR10;
	wire [15:0] OneDR11;
	wire [15:0] OneDR12;
	wire [15:0] OneDR13;
	wire [15:0] OneDR14;
	wire [15:0] OneDR15;
    //DEBUG
    wire [15:0] IT_Output_0,IT_Output_1,IT_Output_2,IT_Output_3,IT_Output_4,IT_Output_5,IT_Output_6,IT_Output_7;
	wire [15:0] IT_Output_8,IT_Output_9,IT_Output_10,IT_Output_11,IT_Output_12,IT_Output_13,IT_Output_14,IT_Output_15;
    wire [15:0] IQ_Output_0,IQ_Output_1,IQ_Output_2,IQ_Output_3,IQ_Output_4,IQ_Output_5,IQ_Output_6,IQ_Output_7;
	wire [15:0] IQ_Output_8,IQ_Output_9,IQ_Output_10,IQ_Output_11,IQ_Output_12,IQ_Output_13,IQ_Output_14,IQ_Output_15;
    wire isDirect_iq;
	wire isDirect_it;
    wire [5:0] current_state;
    wire Luma_or_Chro;
    wire Reg_w;
    //
	// Instantiate the Unit Under Test (UUT)
	IQIT_module uut (
		.Clk(Clk),
		.Rst(Rst),
		.i_Blk(i_Blk),
		.QP(QP),
		.Sig_start(Sig_start),
		.Sig_done(Sig_done),
		.Input_0(Input_0),
		.Input_1(Input_1),
		.Input_2(Input_2),
		.Input_3(Input_3),
		.Input_4(Input_4),
		.Input_5(Input_5),
		.Input_6(Input_6),
		.Input_7(Input_7),
		.Input_8(Input_8),
		.Input_9(Input_9),
		.Input_10(Input_10),
		.Input_11(Input_11),
		.Input_12(Input_12),
		.Input_13(Input_13),
		.Input_14(Input_14),
		.Input_15(Input_15),
		.Luma_DCR0(Luma_DCR0),
		.Luma_DCR1(Luma_DCR1),
		.Luma_DCR2(Luma_DCR2),
		.Luma_DCR3(Luma_DCR3),
		.Luma_DCR4(Luma_DCR4),
		.Luma_DCR5(Luma_DCR5),
		.Luma_DCR6(Luma_DCR6),
		.Luma_DCR7(Luma_DCR7),
		.Luma_DCR8(Luma_DCR8),
		.Luma_DCR9(Luma_DCR9),
		.Luma_DCR10(Luma_DCR10),
		.Luma_DCR11(Luma_DCR11),
		.Luma_DCR12(Luma_DCR12),
		.Luma_DCR13(Luma_DCR13),
		.Luma_DCR14(Luma_DCR14),
		.Luma_DCR15(Luma_DCR15),
		.Cr_DCR0(Cr_DCR0),
		.Cr_DCR1(Cr_DCR1),
		.Cr_DCR2(Cr_DCR2),
		.Cr_DCR3(Cr_DCR3),
		.Cb_DCR0(Cb_DCR0),
		.Cb_DCR1(Cb_DCR1),
		.Cb_DCR2(Cb_DCR2),
		.Cb_DCR3(Cb_DCR3),
		.OneDR0(OneDR0),
		.OneDR1(OneDR1),
		.OneDR2(OneDR2),
		.OneDR3(OneDR3),
		.OneDR4(OneDR4),
		.OneDR5(OneDR5),
		.OneDR6(OneDR6),
		.OneDR7(OneDR7),
		.OneDR8(OneDR8),
		.OneDR9(OneDR9),
		.OneDR10(OneDR10),
		.OneDR11(OneDR11),
		.OneDR12(OneDR12),
		.OneDR13(OneDR13),
		.OneDR14(OneDR14),
		.OneDR15(OneDR15)
        //DEBUG
        ,
        .IT_Output_0(IT_Output_0),
    .IT_Output_1(IT_Output_1),
    .IT_Output_2(IT_Output_2),
    .IT_Output_3(IT_Output_3),
    .IT_Output_4(IT_Output_4),
    .IT_Output_5(IT_Output_5),
    .IT_Output_6(IT_Output_6),
    .IT_Output_7(IT_Output_7),
    .IT_Output_8(IT_Output_8),
    .IT_Output_9(IT_Output_9),
    .IT_Output_10(IT_Output_10),
    .IT_Output_11(IT_Output_11),
    .IT_Output_12(IT_Output_12),
    .IT_Output_13(IT_Output_13),
    .IT_Output_14(IT_Output_14),
    .IT_Output_15(IT_Output_15)
    ,
    .isDirect_iq(isDirect_iq),
	.isDirect_it(isDirect_it)
    ,
    .IQ_Output_0(IQ_Output_0),
    .IQ_Output_1(IQ_Output_1),
    .IQ_Output_2(IQ_Output_2),
    .IQ_Output_3(IQ_Output_3),
    .IQ_Output_4(IQ_Output_4),
    .IQ_Output_5(IQ_Output_5),
    .IQ_Output_6(IQ_Output_6),
    .IQ_Output_7(IQ_Output_7),
    .IQ_Output_8(IQ_Output_8),
    .IQ_Output_9(IQ_Output_9),
    .IQ_Output_10(IQ_Output_10),
    .IQ_Output_11(IQ_Output_11),
    .IQ_Output_12(IQ_Output_12),
    .IQ_Output_13(IQ_Output_13),
    .IQ_Output_14(IQ_Output_14),
    .IQ_Output_15(IQ_Output_15),
    .current_state(current_state),
    .Luma_or_Chro(Luma_or_Chro),
    .Reg_w(Reg_w)
    //
	);
    reg [8:0] cnt;
    reg [8:0] i_Blk_cnt;
	initial begin
		// Initialize Inputs
		Clk = 0;
		Rst = 0;
        cnt=0;
		i_Blk = 0;
        i_Blk_cnt = 0;
		QP = 13;
		Sig_start = 0;
		Input_0 = 0;
		Input_1 = 0;
		Input_2 = 0;
		Input_3 = 0;
		Input_4 = 0;
		Input_5 = 0;
		Input_6 = 0;
		Input_7 = 0;
		Input_8 = 0;
		Input_9 = 0;
		Input_10 = 0;
		Input_11 = 0;
		Input_12 = 0;
		Input_13 = 0;
		Input_14 = 0;
		Input_15 = 0;

		// Wait 100 ns for global reset to finish
		#100;
        #10 Rst =1 ;
		// Add stimulus here

	end

    always #20 Clk=~Clk;

        always @(posedge Clk or negedge Rst) begin
            if(!Rst) begin
                cnt <=0;
                i_Blk_cnt <= 0;
                QP <= 13;
            end
            else begin
                case(cnt)
                0:begin//lumaֱ
                    i_Blk <= 5'b11111;
                    Sig_start <= 1;
                    Input_0 <= 1;
                    Input_1 <= 2;
                    Input_2 <= 3;
                    Input_3 <= 4;
                    Input_4 <= 5;
                    Input_5 <= 6;
                    Input_6 <= 7;
                    Input_7 <= 8;
                    Input_8 <= 9;
                    Input_9 <= 10;
                    Input_10 <= 11;
                    Input_11 <= 12;
                    Input_12 <= 13;
                    Input_13 <= 14;
                    Input_14 <= 15;
                    Input_15 <= 16;
                    cnt <= cnt + 1;
                end
                1:begin
                    Sig_start <= 0;
                    if(Sig_done==1'b1) begin
                        cnt <= cnt+1;
                    end
                    else begin
                        cnt <= cnt;
                    end
                end
                2:begin//luma
                    i_Blk <= i_Blk_cnt;
                    Sig_start <= 1;
                    Input_0 <= 1;
                    Input_1 <= 2;
                    Input_2 <= 3;
                    Input_3 <= 4;
                    Input_4 <= 5;
                    Input_5 <= 6;
                    Input_6 <= 7;
                    Input_7 <= 8;
                    Input_8 <= 9;
                    Input_9 <= 10;
                    Input_10 <= 11;
                    Input_11 <= 12;
                    Input_12 <= 13;
                    Input_13 <= 14;
                    Input_14 <= 15;
                    Input_15 <= 16;
                    cnt <= cnt + 1;
                end
                3:begin
                    Sig_start <= 0;
                    if(Sig_done==1'b1) begin
                        if(i_Blk_cnt==15)
                            cnt <= 4;
                        else
                            cnt <= 2;
                        i_Blk_cnt <= i_Blk_cnt + 1;
                    end
                    else begin
                        cnt <= cnt;
                    end
                end
                4:begin//2X2DC
                    i_Blk <= i_Blk_cnt;
                    Sig_start <= 1;
                    Input_0 <= 1;
                    Input_1 <= 2;
                    Input_2 <= 3;
                    Input_3 <= 4;
                    Input_4 <= 0;
                    Input_5 <= 0;
                    Input_6 <= 0;
                    Input_7 <= 0;
                    Input_8 <= 0;
                    Input_9 <= 0;
                    Input_10 <= 0;
                    Input_11 <= 0;
                    Input_12 <= 0;
                    Input_13 <= 0;
                    Input_14 <= 0;
                    Input_15 <= 0;
                    cnt <= cnt + 1;
                end
                5:begin
                    Sig_start <= 0;
                    if(Sig_done==1'b1) begin
                        if(i_Blk_cnt==17)
                            cnt <= 6;
                        else
                            cnt <= 4;
                        i_Blk_cnt <= i_Blk_cnt + 1;
                    end
                    else begin
                        cnt <= cnt;
                    end
                end
                6:begin
                    i_Blk <= i_Blk_cnt;
                    Sig_start <= 1;
                    Input_0 <= 1;
                    Input_1 <= 2;
                    Input_2 <= 3;
                    Input_3 <= 4;
                    Input_4 <= 5;
                    Input_5 <= 6;
                    Input_6 <= 7;
                    Input_7 <= 8;
                    Input_8 <= 9;
                    Input_9 <= 10;
                    Input_10 <= 11;
                    Input_11 <= 12;
                    Input_12 <= 13;
                    Input_13 <= 14;
                    Input_14 <= 15;
                    Input_15 <= 16;
                    cnt <= cnt + 1;
                end
                7:begin
                    Sig_start <= 0;
                    if(Sig_done==1'b1) begin
                        if(i_Blk_cnt==25)
                            cnt <= 8;
                        else
                            cnt <= 6;
                        i_Blk_cnt <= i_Blk_cnt + 1;
                    end
                    else begin
                        cnt <= cnt;
                    end
                end
                8:begin
                    i_Blk <= 5'b11111;
                    i_Blk_cnt <= 0;
                    Sig_start <= 1;
                    Input_0 <= 11;
                    Input_1 <= 22;
                    Input_2 <= 33;
                    Input_3 <= 44;
                    Input_4 <= 55;
                    Input_5 <= 66;
                    Input_6 <= 77;
                    Input_7 <= 88;
                    Input_8 <= 99;
                    Input_9 <= 11;
                    Input_10 <= 21;
                    Input_11 <= 22;
                    Input_12 <= 23;
                    Input_13 <= 24;
                    Input_14 <= 25;
                    Input_15 <= 26;
                    cnt <= cnt + 1;
                end
                9:begin
                    Sig_start <= 0;
                    if(Sig_done==1'b1) begin
                        cnt <= 10;
                    end
                    else begin
                        cnt <= cnt;
                    end
                end
                10:begin
                    i_Blk <= i_Blk_cnt;
                    Sig_start <= 1;
                    Input_0 <= 11;
                    Input_1 <= 22;
                    Input_2 <= 33;
                    Input_3 <= 44;
                    Input_4 <= 55;
                    Input_5 <= 66;
                    Input_6 <= 7;
                    Input_7 <= 8;
                    Input_8 <= 9;
                    Input_9 <= 11;
                    Input_10 <= 21;
                    Input_11 <= 22;
                    Input_12 <= 23;
                    Input_13 <= 24;
                    Input_14 <= 25;
                    Input_15 <= 26;
                    cnt <= cnt + 1;
                end
                11:begin
                    Sig_start <= 0;
                    if(Sig_done==1'b1) begin
                        if(i_Blk_cnt==15)
                            cnt <= 12;
                        else
                            cnt <= 10;
                        i_Blk_cnt <= i_Blk_cnt + 1;
                    end
                    else begin
                        cnt <= cnt;
                    end
                end
                12:begin
                    i_Blk <= i_Blk_cnt;
                    Sig_start <= 1;
                    Input_0 <= 11;
                    Input_1 <= 22;
                    Input_2 <= 33;
                    Input_3 <= 44;
                    cnt <= cnt + 1;
                end
                13:begin
                    Sig_start <= 0;
                    if(Sig_done==1'b1) begin
                        cnt <= 14;
                        i_Blk_cnt <= i_Blk_cnt + 1;
                    end
                    else begin
                        cnt <= cnt;
                    end
                end
                14:begin
                    i_Blk <= i_Blk_cnt;
                    Sig_start <= 1;
                    Input_0 <= 11;
                    Input_1 <= 2;
                    Input_2 <= 33;
                    Input_3 <= 4;
                    cnt <= cnt + 1;
                end
                15:begin
                    Sig_start <= 0;
                    if(Sig_done==1'b1) begin
                        cnt <= 16;
                        i_Blk_cnt <= i_Blk_cnt + 1;
                    end
                    else begin
                        cnt <= cnt;
                    end
                end
                16:begin
                    i_Blk <= i_Blk_cnt;
                    Sig_start <= 1;
                    Input_0 <= 1;
                    Input_1 <= 2;
                    Input_2 <= 33;
                    Input_3 <= 4;
                    Input_4 <= 55;
                    Input_5 <= 6;
                    Input_6 <= 77;
                    Input_7 <= 8;
                    Input_8 <= 9;
                    Input_9 <= 11;
                    Input_10 <= 1;
                    Input_11 <= 22;
                    Input_12 <= 23;
                    Input_13 <= 4;
                    Input_14 <= 25;
                    Input_15 <= 6;
                    cnt <= cnt + 1;
                end
                17:begin
                    Sig_start <= 0;
                    if(Sig_done==1'b1) begin
                        if(i_Blk_cnt==25)
                            cnt <= 18;
                        else
                            cnt <= 16;
                        i_Blk_cnt <= i_Blk_cnt + 1;
                    end
                    else begin
                        cnt <= cnt;
                    end
                end
                18:begin
                    cnt <= cnt;
                end
                default:begin
                    cnt <= cnt;
                end
                endcase
            end

        end

endmodule