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(qemu) info lapic dumping local APIC state for CPU 0 LVT0 0x00010000 active-hi edge masked Fixed (vec 0) LVT1 0x00010000 active-hi edge masked Fixed (vec 0) LVTPC 0x00010000 active-hi edge masked Fixed (vec 0) LVTERR 0x00000033 active-hi edge Fixed (vec 51) LVTTHMR 0x00010000 active-hi edge masked Fixed (vec 0) LVTT 0x00020020 active-hi edge periodic Fixed (vec 32) Timer DCR=0xb (divide by 1) initial_count = 10000000 current_count = 7172266 SPIV 0x0000013f APIC enabled, focus=off, spurious vec 63 ICR 0x00088500 physical level de-assert all-self ICR2 0x00000000 ESR 0x00000000 ISR (none) IRR 32 APR 0x00 TPR 0x00 DFR 0x0f LDR 0x00 PPR 0x00 (qemu) info pic pic1: irr=40 imr=ff isr=00 hprio=0 irq_base=70 rr_sel=0 elcr=0c fnm=0 pic0: irr=15 imr=ff isr=00 hprio=0 irq_base=08 rr_sel=0 elcr=00 fnm=0 ioapic0: ver=0x20 id=0x00 sel=0x00 pin 0 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 1 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 2 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 3 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 4 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 5 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 6 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 7 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 8 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 9 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 10 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 11 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 12 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 13 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 14 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 15 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 16 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 17 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 18 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 19 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 20 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 21 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 22 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 23 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical IRR (none) Remote IRR (none) (qemu)
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