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From 928442c4184ceb115665da2040accc7e6c716b79 Mon Sep 17 00:00:00 2001
From: Yangyang Li <liyangyang20@huawei.com>
Date: Tue, 13 Sep 2022 20:09:27 +0800
Subject: [PATCH 2/2] libhns: Add the parsing of mac type in RoH mode
driver inclusion
category: feature
bugzilla: https://gitee.com/src-openeuler/rdma-core/issues/I9FFIU
------------------------------------------------------------------
After parsing the mac type as RoH mode, the user driver
needs to set the dmac field of ud wqe to 0xFF, the hardware
will recognize this field, and increase the recognition of
the IP field in RoH mode, which is used for the CM link
building function in user mode.
Signed-off-by: Yangyang Li <liyangyang20@huawei.com>
Signed-off-by: Guofeng Yue <yueguofeng@hisilicon.com>
---
providers/hns/hns_roce_u.c | 34 +++++++++++++++++++++++++++++++-
providers/hns/hns_roce_u.h | 6 ++++++
providers/hns/hns_roce_u_hw_v2.c | 4 ++++
3 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/providers/hns/hns_roce_u.c b/providers/hns/hns_roce_u.c
index f9abe2f..7a3d1a2 100644
--- a/providers/hns/hns_roce_u.c
+++ b/providers/hns/hns_roce_u.c
@@ -95,6 +95,38 @@ static const struct verbs_context_ops hns_common_ops = {
.alloc_parent_domain = hns_roce_u_alloc_pad,
};
+static struct {
+ uint32_t device_id;
+ enum hns_device_link_type link_type;
+} device_link_types[] = {
+ {0xA222, HNS_DEV_LINK_TYPE_ETH},
+ {0xA223, HNS_DEV_LINK_TYPE_ETH},
+ {0xA224, HNS_DEV_LINK_TYPE_ETH},
+ {0xA225, HNS_DEV_LINK_TYPE_ETH},
+ {0xA226, HNS_DEV_LINK_TYPE_ETH},
+ {0xA228, HNS_DEV_LINK_TYPE_ETH},
+ {0xA22F, HNS_DEV_LINK_TYPE_ETH},
+ {0xA227, HNS_DEV_LINK_TYPE_HCCS},
+ {0xA22C, HNS_DEV_LINK_TYPE_HCCS},
+ {0xA22D, HNS_DEV_LINK_TYPE_HCCS}
+};
+
+static int get_link_type(uint32_t device_id,
+ enum hns_device_link_type *link_type)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(device_link_types); i++) {
+ if (device_id == device_link_types[i].device_id) {
+ *link_type = device_link_types[i].link_type;
+ return 0;
+ }
+ }
+
+ return ENOENT;
+}
+
+
static uint32_t calc_table_shift(uint32_t entry_count, uint32_t size_shift)
{
uint32_t count_shift = hr_ilog32(entry_count);
@@ -303,7 +335,7 @@ static int set_context_attr(struct hns_roce_device *hr_dev,
context->max_srq_wr = dev_attrs.max_srq_wr;
context->max_srq_sge = dev_attrs.max_srq_sge;
- return 0;
+ return get_link_type(dev_attrs.vendor_part_id, &hr_dev->link_type);
}
static void ucontext_set_cmd(struct hns_roce_alloc_ucontext *cmd,
diff --git a/providers/hns/hns_roce_u.h b/providers/hns/hns_roce_u.h
index 691bf61..5eedb81 100644
--- a/providers/hns/hns_roce_u.h
+++ b/providers/hns/hns_roce_u.h
@@ -161,12 +161,18 @@ enum {
#define HNS_ROCE_SRQ_TABLE_BITS 8
#define HNS_ROCE_SRQ_TABLE_SIZE BIT(HNS_ROCE_SRQ_TABLE_BITS)
+enum hns_device_link_type {
+ HNS_DEV_LINK_TYPE_ETH,
+ HNS_DEV_LINK_TYPE_HCCS,
+};
+
struct hns_roce_device {
struct verbs_device ibv_dev;
int page_size;
const struct hns_roce_u_hw *u_hw;
int hw_version;
uint8_t congest_cap;
+ enum hns_device_link_type link_type;
};
struct hns_roce_buf {
diff --git a/providers/hns/hns_roce_u_hw_v2.c b/providers/hns/hns_roce_u_hw_v2.c
index 15d9108..b2d452b 100644
--- a/providers/hns/hns_roce_u_hw_v2.c
+++ b/providers/hns/hns_roce_u_hw_v2.c
@@ -1377,6 +1377,7 @@ static inline void enable_wqe(struct hns_roce_qp *qp, void *sq_wqe,
static int set_ud_wqe(void *wqe, struct hns_roce_qp *qp, struct ibv_send_wr *wr,
unsigned int nreq, struct hns_roce_sge_info *sge_info)
{
+ struct hns_roce_device *hr_dev = to_hr_dev(qp->verbs_qp.qp.context->device);
struct hns_roce_ah *ah = to_hr_ah(wr->wr.ud.ah);
struct hns_roce_ud_sq_wqe *ud_sq_wqe = wqe;
int ret = 0;
@@ -1401,6 +1402,9 @@ static int set_ud_wqe(void *wqe, struct hns_roce_qp *qp, struct ibv_send_wr *wr,
if (ret)
return ret;
+ if (hr_dev->link_type == HNS_DEV_LINK_TYPE_HCCS)
+ ud_sq_wqe->dmac[0] = 0xF0;
+
ret = fill_ud_data_seg(ud_sq_wqe, qp, wr, sge_info);
if (ret)
return ret;
--
2.33.0
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