From 6747635a4423fc0844230bc66112853856b9fe97 Mon Sep 17 00:00:00 2001
From: mou bingquan <moubingquan@huawei.com>
Date: Wed, 18 Oct 2023 09:52:39 +0800
Subject: [PATCH] hikptool : Querying the SerDes Relationship of the PCIe

This function is used to query the macro corresponding to the
port of the PCIe. It is a type of SerDes multiplexing relationship.
---
 pcie/func_lib/pcie_func/pcie_statistics.c | 30 +++++++++++++++++++++++
 pcie/func_lib/pcie_func/pcie_statistics.h | 10 ++++++++
 2 files changed, 40 insertions(+)

diff --git a/pcie/func_lib/pcie_func/pcie_statistics.c b/pcie/func_lib/pcie_func/pcie_statistics.c
index 308a142..128e7f7 100644
--- a/pcie/func_lib/pcie_func/pcie_statistics.c
+++ b/pcie/func_lib/pcie_func/pcie_statistics.c
@@ -25,6 +25,10 @@ static const char *g_global_width_name[GLOBAL_WIDTH_TABLE_SIZE] = {
 	"PCIE_WIDTH_X1", "PCIE_WIDTH_X2", "PCIE_WIDTH_X4", "PCIE_WIDTH_X8", "PCIE_WIDTH_X16"
 };
 
+static const char *g_global_ndie_name[] = {
+	"Ndie_A", "Ndie_B"
+};
+
 static int port_distribution_rsp_data_check(const struct hikp_cmd_ret *cmd_ret, uint32_t *port_num)
 {
 	size_t rsp_data_size, expect_data_size;
@@ -58,6 +62,29 @@ static int port_distribution_rsp_data_check(const struct hikp_cmd_ret *cmd_ret,
 	return 0;
 }
 
+static int pcie_portid_serdes_relation(const struct pcie_macro_info *macro_info,
+					uint32_t macro_num, uint32_t ndie_id)
+{
+	uint32_t i, j;
+
+	if (ndie_id >= HIKP_ARRAY_SIZE(g_global_ndie_name)) {
+		Info("PCIe Base", "ndie_id [%u]: %s\n", ndie_id, "UNKNOWN_NDIE");
+		return -1;
+	}
+
+	if (macro_num >= MAX_MACRO_ONEPORT) {
+		Info("PCIe Base", "macro_num [%u] exceeds the maximum array length\n", macro_num);
+		return -1;
+	}
+
+	Info("PCIe Base", "\tndie_id: %s\n", g_global_ndie_name[ndie_id]);
+	for (i = 0; i < macro_num; i++) {
+		for (j = macro_info[i].lane_s; j <= macro_info[i].lane_e; j++)
+			Info("PCIe Base", "\t\tmacro %d \t lane: %d\n", macro_info[i].id, j);
+	}
+	return 0;
+}
+
 int pcie_port_distribution_get(uint32_t chip_id)
 {
 	struct hikp_cmd_header req_header;
@@ -86,6 +113,9 @@ int pcie_port_distribution_get(uint32_t chip_id)
 		}
 		Info("PCIe Base", "port_id[%u] %s\n", port_info->info_pair[i].port_id,
 			g_global_width_name[port_info->info_pair[i].port_width]);
+		pcie_portid_serdes_relation(port_info->info_pair[i].macro_info,
+					    port_info->info_pair[i].macro_num,
+					    port_info->info_pair[i].ndie_id);
 	}
 free_cmd_ret:
 	free(cmd_ret);
diff --git a/pcie/func_lib/pcie_func/pcie_statistics.h b/pcie/func_lib/pcie_func/pcie_statistics.h
index 2a3cc66..3e3916b 100644
--- a/pcie/func_lib/pcie_func/pcie_statistics.h
+++ b/pcie/func_lib/pcie_func/pcie_statistics.h
@@ -17,6 +17,7 @@
 #include "pcie_common_api.h"
 
 #define GLOBAL_WIDTH_TABLE_SIZE 5
+#define MAX_MACRO_ONEPORT 3
 
 union mac_test_cnt {
 	/* Define the struct bits */
@@ -88,9 +89,18 @@ union dfx_dcrc_err_num {
 	unsigned int u32;
 };
 
+struct pcie_macro_info {
+	uint32_t id;
+	uint32_t lane_s;
+	uint32_t lane_e;
+};
+
 struct pcie_info_distribution_pair {
 	uint32_t port_id;
 	uint32_t port_width;
+	uint32_t ndie_id;
+	uint32_t macro_num;
+	struct pcie_macro_info macro_info[MAX_MACRO_ONEPORT];
 };
 
 struct pcie_port_info {
-- 
2.33.0