/*
 * Autogenerated by xlsx-irqmapgen
 * Generated by xlsx-irqmapgen 2018-12-06
 * ./irqmapgen.py --sheetname=Interrupts_Map --prefixname=_IRQ --basename-column=A --irqno-column=E --start-irq-column=F --start-row=2 --end-row=131 /home/edgar/Everest_Interrupts_Map.xlsx
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:

 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#define RESERVED_IRQ_0					0
#define RESERVED_IRQ_1					1
#define RESERVED_IRQ_2					2
#define RESERVED_IRQ_3					3
#define RESERVED_IRQ_4					4
#define RESERVED_IRQ_5					5
#define RESERVED_IRQ_6					6
#define RESERVED_IRQ_7					7
#define RPU0_PERF_MON_IRQ_0				8
#define RPU1_PERF_MON_IRQ_0				9
#define evento0_rpu_pl_IRQ_0				9
#define evento1_rpu_pl_IRQ_0				9
#define rpu_psm_lockstep_err_IRQ_0			9
#define rpu_psm_ccf_err_IRQ_0				9
#define rpu_psm_dbgrstreq0_IRQ_0			9
#define rpu_psm_dbgrstreq1_IRQ_0			9
#define crl_pll_lock_IRQ_0				9
#define OCMINTR_IRQ_0					10
#define ocm_psm_uncorrectable_err_IRQ_0			10
#define LPD_APB_INT_IRQ_0				10
#define IPI_APB_IRQ_0					10
#define USB2_APB_IRQ_0					10
#define CRL_INT_IRQ_0					10
#define AFI4_APB_IRQ_0					10
#define IOU_NS_APB_IRQ_0				10
#define IOU_S_APB_IRQ_0					10
#define LPD_NS_APB_IRQ_0				10
#define LPD_S_APB_IRQ_0					10
#define RPU0_ECC_IRQ_0					11
#define RPU1_ECC_IRQ_0					12
#define GPIO_IRQ_0					13
#define I2C0_IRQ_0					14
#define I2C1_IRQ_0					15
#define SPI0_IRQ_0					16
#define SPI1_IRQ_0					17
#define UART0_IRQ_0					18
#define UART1_IRQ_0					19
#define CAN0_IRQ_0					20
#define CAN1_IRQ_0					21
#define USB2_IRQ_0					22
#define USB2_IRQ_1					23
#define USB2_IRQ_2					24
#define USB2_IRQ_3					25
#define USB2_2_IRQ_0					26
#define IPI_PMC_IRQ_0					27
#define IPI_PMC_NOBUF_IRQ_0				28
#define IPI_PSM_IRQ_0					29
#define IPI0_IRQ_0					30
#define IPI1_IRQ_0					31
#define IPI2_IRQ_0					32
#define IPI3_IRQ_0					33
#define IPI4_IRQ_0					34
#define IPI5_IRQ_0					35
#define IPI6_IRQ_0					36
#define TTC0_IRQ_0					37
#define TTC0_IRQ_1					38
#define TTC0_IRQ_2					39
#define TTC1_IRQ_0					40
#define TTC1_IRQ_1					41
#define TTC1_IRQ_2					42
#define TTC2_IRQ_0					43
#define TTC2_IRQ_1					44
#define TTC2_IRQ_2					45
#define TTC3_IRQ_0					46
#define TTC3_IRQ_1					47
#define TTC3_IRQ_2					48
#define WWDT_IRQ_0					49
#define PSM_MB_IRQ_0					50
#define XPPU_IRQ_0					51
#define INT_LPD_IRQ_0					52
#define AMS_IRQ_0					53
#define RESERVED_2_IRQ_0				54
#define RESERVED_3_IRQ_0				55
#define GEM0_IRQ_0					56
#define GEM0_WAKE_IRQ_0					57
#define GEM1_IRQ_0					58
#define GEM1_WAKE_IRQ_0					59
#define ADMA_IRQ_0					60
#define ADMA_IRQ_1					61
#define ADMA_IRQ_2					62
#define ADMA_IRQ_3					63
#define ADMA_IRQ_4					64
#define ADMA_IRQ_5					65
#define ADMA_IRQ_6					66
#define ADMA_IRQ_7					67
#define XMPU_OCM_IRQ_0					68
#define WWDT_RST_PENDING_IRQ_0				69
#define GWDT_WS0_IRQ_0					70
#define GWDT_WS1_IRQ_0					71
#define CPM_MISC_IRQ_0					72
#define CPM_CORR_IRQ_0					73
#define USB2_PME_IRQ_0					74
#define CPM_UNCORR_IRQ_0				75
#define RESERVED_4_IRQ_0				76
#define RESERVED_4_IRQ_1				77
#define OCM2_IRQ_0					78
#define OCM2_UNCORR_IRQ_0				79
#define RESERVED_5_IRQ_0				80
#define RESERVED_5_IRQ_1				81
#define RESERVED_5_IRQ_2				82
#define RESERVED_5_IRQ_3				83
#define PL_PS_GRP0_IRQ_0				84
#define PL_PS_GRP0_IRQ_1				85
#define PL_PS_GRP0_IRQ_2				86
#define PL_PS_GRP0_IRQ_3				87
#define PL_PS_GRP0_IRQ_4				88
#define PL_PS_GRP0_IRQ_5				89
#define PL_PS_GRP0_IRQ_6				90
#define PL_PS_GRP0_IRQ_7				91
#define PL_PS_GRP1_IRQ_0				92
#define PL_PS_GRP1_IRQ_1				93
#define PL_PS_GRP1_IRQ_2				94
#define PL_PS_GRP1_IRQ_3				95
#define PL_PS_GRP1_IRQ_4				96
#define PL_PS_GRP1_IRQ_5				97
#define PL_PS_GRP1_IRQ_6				98
#define PL_PS_GRP1_IRQ_7				99
#define FP_WDT_IRQ_0					100
#define FPD_APB_INT_IRQ_0				100
#define AFI0_APB_IRQ_0					100
#define AFI2_APB_IRQ_0					100
#define SLCR_SECURE_FPD_APB_IRQ_0			100
#define SLCR_FPD_APB_IRQ_0				100
#define CRF_int_IRQ_0					100
#define SysMon_interrupt_IRQ_0				101
#define XMPU_FPD_IRQ_0					102
#define APU_L2ERR_IRQ_0					103
#define APU_EXTERR_IRQ_0				104
#define APU_REGS_IRQ_0					105
#define INTF_PPD_CCI_IRQ_0				106
#define INTF_FPD_SMMU_IRQ_0				107
#define FPD_GWDT_WS0_IRQ_0				108
#define FPD_WWDT_RST_PENDING_IRQ_0			109
#define FPD_GWDT_WS1_IRQ_0				110
#define RESERVED_6_IRQ_0				111
#define RESERVED_6_IRQ_1				112
#define RESERVED_6_IRQ_2				113
#define RESERVED_6_IRQ_3				114
#define RESERVED_6_IRQ_4				115
#define RESERVED_6_IRQ_5				116
#define RESERVED_6_IRQ_6				117
#define RESERVED_6_IRQ_7				118
#define RESERVED_6_IRQ_8				119
#define CFU_CRITICAL_IRQ_0				119
#define CFU_IRQ_0					120
#define CFRAME_SEU_IRQ_0				121
#define CFRAME_IRQ_0					121
#define PMC_APB_IRQ_0					121
#define CRP_IRQ_0					121
#define PMC_IOU_SEC_SLCR_IRQ_0				121
#define PMC_IOU_SLCR_IRQ_0				121
#define BBRAM_APB_IRQ_0					121
#define RTC_APB_IRQ_0					121
#define CRP_CLKMON_IRQ_0				121
#define GPIO_PMC_IRQ_0					122
#define I2C_PMC_IRQ_0					123
#define OSPI_IRQ_0					124
#define QSPI_IRQ_0					125
#define SD0_IRQ_0					126
#define SDO_WKUP_IRQ_0					127
#define SD1_IRQ_0					128
#define SD1_WKUP_IRQ_0					129
#define PMC_DEBUG_IRQ_0					130
#define PMC_DMA0_IRQ_0					131
#define PMC_DMA1_IRQ_0					132
#define INT_PMC_IRQ_0					132
#define PMC_INT_IRQ_0					133
#define XPPU_PMC_IRQ_0					134
#define XMPU_PRAM_IRQ_0					135
#define SBI_IRQ_0					136
#define AES_IRQ_0					137
#define ECDSA_RSA_IRQ_0					138
#define EFUSE_IRQ_0					139
#define SHA_IRQ_0					140
#define TRNG_IRQ_0					141
#define RTC_ALARM_IRQ_0					142
#define RTC_SECONDS_IRQ_0				143
#define SYSMON_IRQ_0					144
#define SYSMON_IRQ_1					145
#define NPI_IRQ_IRQ_0					146
#define NPI_IRQ_IRQ_1					147
#define NPI_IRQ_IRQ_2					148
#define NPI_IRQ_IRQ_3					149
#define NPI_IRQ_IRQ_4					150
#define NPI_IRQ_IRQ_5					151
#define NPI_IRQ_IRQ_6					152
#define NPI_IRQ_IRQ_7					153
#define NPI_IRQ_IRQ_8					154
#define NPI_IRQ_IRQ_9					155
#define NPI_IRQ_IRQ_10					156
#define NPI_IRQ_IRQ_11					157
#define PRAM_IRQ_IRQ_0					158