/*
 * ZynqMP Ultra96 board device tree
 *
 * Copyright (c) 2019, Xilinx Inc
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the <organization> nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include "zynqmp.dtsh"

/dts-v1/;

#include "zynqmp-arm.dtsi"
#include "zynqmp-memory-regions.dtsi"

/ {
	model = "ZynqMP Ultra96 RevA";
	compatible = "xlnx,zynqmp-ultra96", "xlnx,zynqmp";
};

&ps7_qspi_0 {
	qspi-flash@0 {
		compatible = "n25q128a13";
		spi-max-frequency = <108000000>;
		reg = <0>;
		partition@0 {
			label = "qspi-fsbl-uboot";
			reg = <0x0 0x1000000>;
		};
	};
};

/* Add I2C devices */

/* SPI devices are WiFi/Bluetooth chip.
 * Add this if QEMU supports it
 */

/* Add DP clock when it is finalised */

/* Hack in the si570 clock for DP testing
 * This is not actually on the board
 */

&amba {
	i2c1: i2c1@0xFF030000 {
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <I2C_CLOCKS>;
		compatible = "xlnx,ps7-i2c-1.00.a", "cdns,i2c-r1p10";
		interrupts = <I2C1_IRQ_0>;
		reg = <BASE_ADDR(I2C1) 0x1000>;
		i2cswitch@74 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "nxp,pca9548";
			reg = <0x74>;
			i2c@2 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <2>;
				si570_1: clock-generator@5d {
					compatible = "silabs,si57x";
					reg = <0x5d>;
					temperature-stability=<50>;
				};
			};
		};
	};
};

&iou_slcr_0 {
	mio-bank0-1.8v = <1>;
	mio-bank1-1.8v = <1>;
	mio-bank2-1.8v = <1>;
};