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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 10:33:17 December 02, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# neopixel_led_controller_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:11:22 MARCH 25, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/top.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/regfile.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/rst_syn.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sys_ctl.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/edge2en.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/spi_slave.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/channel_ctl.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/channel_out.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/waveform_ctl.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/waveform_gen.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/segment_led.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/fps_counter.sv
set_global_assignment -name QIP_FILE ip/pll/pll.qip
set_global_assignment -name QIP_FILE ip/ram/ram256.qip
set_global_assignment -name QSYS_FILE ip/clk/globalclk.qsys
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_J5 -to clk_i
set_location_assignment PIN_P15 -to rst_n_i
set_location_assignment PIN_R14 -to dc_i
set_location_assignment PIN_P12 -to spi_sclk_i
set_location_assignment PIN_R11 -to spi_mosi_i
set_location_assignment PIN_R9 -to spi_cs_n_i
set_location_assignment PIN_P9 -to spi_miso_o
set_location_assignment PIN_E2 -to segment_led_1_o[8]
set_location_assignment PIN_L1 -to segment_led_1_o[7]
set_location_assignment PIN_G5 -to segment_led_1_o[6]
set_location_assignment PIN_F5 -to segment_led_1_o[5]
set_location_assignment PIN_G2 -to segment_led_1_o[4]
set_location_assignment PIN_J2 -to segment_led_1_o[3]
set_location_assignment PIN_K2 -to segment_led_1_o[2]
set_location_assignment PIN_D2 -to segment_led_1_o[1]
set_location_assignment PIN_E1 -to segment_led_1_o[0]
set_location_assignment PIN_B1 -to segment_led_2_o[8]
set_location_assignment PIN_R2 -to segment_led_2_o[7]
set_location_assignment PIN_C2 -to segment_led_2_o[6]
set_location_assignment PIN_C1 -to segment_led_2_o[5]
set_location_assignment PIN_N1 -to segment_led_2_o[4]
set_location_assignment PIN_P1 -to segment_led_2_o[3]
set_location_assignment PIN_P2 -to segment_led_2_o[2]
set_location_assignment PIN_A2 -to segment_led_2_o[1]
set_location_assignment PIN_A3 -to segment_led_2_o[0]
set_location_assignment PIN_C8 -to neopixel_code_o[15]
set_location_assignment PIN_B7 -to neopixel_code_o[14]
set_location_assignment PIN_D7 -to neopixel_code_o[13]
set_location_assignment PIN_E7 -to neopixel_code_o[12]
set_location_assignment PIN_B6 -to neopixel_code_o[11]
set_location_assignment PIN_A7 -to neopixel_code_o[10]
set_location_assignment PIN_A5 -to neopixel_code_o[9]
set_location_assignment PIN_B4 -to neopixel_code_o[8]
set_location_assignment PIN_R5 -to neopixel_code_o[7]
set_location_assignment PIN_L7 -to neopixel_code_o[6]
set_location_assignment PIN_P4 -to neopixel_code_o[5]
set_location_assignment PIN_L6 -to neopixel_code_o[4]
set_location_assignment PIN_R3 -to neopixel_code_o[3]
set_location_assignment PIN_M5 -to neopixel_code_o[2]
set_location_assignment PIN_P3 -to neopixel_code_o[1]
set_location_assignment PIN_M4 -to neopixel_code_o[0]
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
# Compiler Assignments
# ====================
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name MUX_RESTRUCTURE OFF
set_global_assignment -name TOP_LEVEL_ENTITY neopixel_led_controller
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE 10M08SCM153C8G
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION ON
set_global_assignment -name AUTO_GLOBAL_CLOCK ON
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (SystemVerilog)"
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
# start EDA_TEST_BENCH_SETTINGS(test)
# -----------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test -section_id test
# end EDA_TEST_BENCH_SETTINGS(test)
# ---------------------------------
# start EDA_TEST_BENCH_SETTINGS(test_top)
# ---------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_top
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_top -section_id test_top
set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_top.sv -section_id test_top
# end EDA_TEST_BENCH_SETTINGS(test_top)
# -------------------------------------
# start EDA_TEST_BENCH_SETTINGS(test_regfile)
# -------------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_regfile
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_regfile -section_id test_regfile
set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_regfile.sv -section_id test_regfile
# end EDA_TEST_BENCH_SETTINGS(test_regfile)
# -----------------------------------------
# start EDA_TEST_BENCH_SETTINGS(test_rst_syn)
# -------------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_rst_syn
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_rst_syn -section_id test_rst_syn
set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_rst_syn.sv -section_id test_rst_syn
# end EDA_TEST_BENCH_SETTINGS(test_rst_syn)
# -----------------------------------------
# start EDA_TEST_BENCH_SETTINGS(test_edge2en)
# -------------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_edge2en
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_edge2en -section_id test_edge2en
set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_edge2en.sv -section_id test_edge2en
# end EDA_TEST_BENCH_SETTINGS(test_edge2en)
# -----------------------------------------
# start EDA_TEST_BENCH_SETTINGS(test_spi_slave)
# ---------------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_spi_slave
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_spi_slave -section_id test_spi_slave
set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_spi_slave.sv -section_id test_spi_slave
# end EDA_TEST_BENCH_SETTINGS(test_spi_slave)
# -------------------------------------------
# start EDA_TEST_BENCH_SETTINGS(test_channel_ctl)
# -----------------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_channel_ctl
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_channel_ctl -section_id test_channel_ctl
set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_channel_ctl.sv -section_id test_channel_ctl
# end EDA_TEST_BENCH_SETTINGS(test_channel_ctl)
# ---------------------------------------------
# start EDA_TEST_BENCH_SETTINGS(test_channel_out)
# -----------------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_channel_out
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_channel_out -section_id test_channel_out
set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_channel_out.sv -section_id test_channel_out
# end EDA_TEST_BENCH_SETTINGS(test_channel_out)
# ---------------------------------------------
# start EDA_TEST_BENCH_SETTINGS(test_waveform_ctl)
# ------------------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_waveform_ctl
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_waveform_ctl -section_id test_waveform_ctl
set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_waveform_ctl.sv -section_id test_waveform_ctl
# end EDA_TEST_BENCH_SETTINGS(test_waveform_ctl)
# ----------------------------------------------
# start EDA_TEST_BENCH_SETTINGS(test_waveform_gen)
# ------------------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_waveform_gen
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_waveform_gen -section_id test_waveform_gen
set_global_assignment -name EDA_TEST_BENCH_FILE sim/test_waveform_gen.sv -section_id test_waveform_gen
# end EDA_TEST_BENCH_SETTINGS(test_waveform_gen)
# ----------------------------------------------
# start EDA_TOOL_SETTINGS(eda_simulation)
# ---------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH test_top -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME test_top -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME test_regfile -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME test_rst_syn -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME test_edge2en -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME test_spi_slave -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME test_channel_ctl -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME test_channel_out -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME test_waveform_ctl -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME test_waveform_gen -section_id eda_simulation
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR sim/modelsim -section_id eda_simulation
# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------
# start EDA_TOOL_SETTINGS(eda_board_design_boundary_scan)
# -------------------------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
# end EDA_TOOL_SETTINGS(eda_board_design_boundary_scan)
# -----------------------------------------------------
# start EDA_TOOL_SETTINGS(eda_board_design_timing)
# ------------------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
# end EDA_TOOL_SETTINGS(eda_board_design_timing)
# ----------------------------------------------
# start EDA_TOOL_SETTINGS(eda_board_design_symbol)
# ------------------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
# end EDA_TOOL_SETTINGS(eda_board_design_symbol)
# ----------------------------------------------
# start EDA_TOOL_SETTINGS(eda_board_design_signal_integrity)
# ----------------------------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
# end EDA_TOOL_SETTINGS(eda_board_design_signal_integrity)
# --------------------------------------------------------
# -------------------------------------
# start ENTITY(neopixel_led_controller)
# Pin & Location Assignments
# ==========================
set_instance_assignment -name FAST_INPUT_REGISTER ON -to clk_i
set_instance_assignment -name FAST_INPUT_REGISTER ON -to rst_n_i
set_instance_assignment -name FAST_INPUT_REGISTER ON -to dc_i
set_instance_assignment -name FAST_INPUT_REGISTER ON -to spi_sclk_i
set_instance_assignment -name FAST_INPUT_REGISTER ON -to spi_mosi_i
set_instance_assignment -name FAST_INPUT_REGISTER ON -to spi_cs_n_i
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to spi_miso_o
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_1_o[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_1_o[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_1_o[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_1_o[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_1_o[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_1_o[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_1_o[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_1_o[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_1_o[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_2_o[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_2_o[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_2_o[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_2_o[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_2_o[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_2_o[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_2_o[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_2_o[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to segment_led_2_o[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[15]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[14]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[13]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to neopixel_code_o[0]
# Fitter Assignments
# ==================
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk_i
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rst_n_i
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to dc_i
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_sclk_i
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_mosi_i
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_cs_n_i
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_miso_o
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_1_o[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_1_o[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_1_o[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_1_o[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_1_o[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_1_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_1_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_1_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_1_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_2_o[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_2_o[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_2_o[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_2_o[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_2_o[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_2_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_2_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_2_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to segment_led_2_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to neopixel_code_o[0]
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(neopixel_led_controller)
# -----------------------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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