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Formats for Vector Arithmetic Instructions under OP-V major opcode
{reg: [
{bits: 7, name: 0x57, attr: 'OPIVV'},
{bits: 5, name: 'vd', type: 2},
{bits: 3, name: 0},
{bits: 5, name: 'vs1', type: 2},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'OPFVV'},
{bits: 5, name: 'vd / rd', type: 7},
{bits: 3, name: 1},
{bits: 5, name: 'vs1', type: 2},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'OPMVV'},
{bits: 5, name: 'vd / rd', type: 7},
{bits: 3, name: 2},
{bits: 5, name: 'vs1', type: 2},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: ['OPIVI']},
{bits: 5, name: 'vd', type: 2},
{bits: 3, name: 3},
{bits: 5, name: 'imm[4:0]', type: 5},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'OPIVX'},
{bits: 5, name: 'vd', type: 2},
{bits: 3, name: 4},
{bits: 5, name: 'rs1', type: 4},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'OPFVF'},
{bits: 5, name: 'vd', type: 2},
{bits: 3, name: 5},
{bits: 5, name: 'rs1', type: 4},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
{reg: [
{bits: 7, name: 0x57, attr: 'OPMVX'},
{bits: 5, name: 'vd / rd', type: 7},
{bits: 3, name: 6},
{bits: 5, name: 'rs1', type: 4},
{bits: 5, name: 'vs2', type: 2},
{bits: 1, name: 'vm'},
{bits: 6, name: 'funct6'},
]}
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