//A 4-bit adder with carry in and carry out
class mul32 extends Module {
  val io = IO(new Bundle {
    val in1  = Input(UInt(32.W))
    val in2  = Input(UInt(32.W))
    val out  = Output(UInt(65.W))
  })
  val io.out = Cat("b0".U(32.W),io.in2,0.U)
  for(i <- 0 until 31)
  {
    when(io.out(1,0)===1.U)
    {
      val io.out = Reg(init=0.U(65.W))
      io.out(64,33) := io.out(64,33) + io.in1
      io.out >> 1.U
    }
    .elsewhen(io.out(1,0)===2.U)
    {
      val io.out = Reg(init=0.U(65.W))
      io.out(64,33) := io.out(64,33) - io.in1
      io.out >> 1.U
    }
    .otherwise
    {
      val io.out = Reg(init=0.U(65.W))
      io.out >> 1.U
    }
  }
  val io.out = Reg(init=0.U(65.W))
  io.out >>1.U
}