// See LICENSE.txt for license details.
package examples

import chisel3._
import chisel3.util._

//A 4-bit adder with carry in and carry out
class div32 extends Module {
  val io = IO(new Bundle {
    val in1  = Input(UInt(32.W))
    val in2  = Input(UInt(32.W))
    val out  = Output(UInt(64.W))
  })
  val out =Cat("b0".U(32.W),io.in1)
  for(i <- 0 until 31)
  {
    val io.out = Reg(init=0.U(64.W))
    io.out(63,32) := io.out(63,32) - io.in2
    when(io.out(63)===1.U)
    {
      val io.out = Reg(init=0.U(64.W))
      io.out(63,32) := io.out(63,32) + io.in2
      io.out << 1.U
    }
    .elsewhen(io.out(63)===0.U)
    {
      io.out(0) := 1.U 
      io.out << 1.U
    }
  }
}