/dts-v1/;
// magic:		0xd00dfeed
// totalsize:		0x25c2e (154670)
// off_dt_struct:	0x38
// off_dt_strings:	0x2425c
// off_mem_rsvmap:	0x28
// version:		17
// last_comp_version:	16
// boot_cpuid_phys:	0x0
// size_dt_strings:	0x19d2
// size_dt_struct:	0x24224

/ {
    compatible = "rockchip,rk3588-lenovo", "rockchip,rk3588";
    interrupt-parent = <0x00000001>;
    #address-cells = <0x00000002>;
    #size-cells = <0x00000002>;
    model = "Rockchip RK3588 Lenovo Board";
    aliases {
        csi2dcphy0 = "/csi2-dcphy0";
        csi2dcphy1 = "/csi2-dcphy1";
        csi2dphy0 = "/csi2-dphy0";
        csi2dphy1 = "/csi2-dphy1";
        csi2dphy2 = "/csi2-dphy2";
        dsi0 = "/dsi@fde20000";
        dsi1 = "/dsi@fde30000";
        ethernet1 = "/ethernet@fe1c0000";
        gpio0 = "/pinctrl/gpio@fd8a0000";
        gpio1 = "/pinctrl/gpio@fec20000";
        gpio2 = "/pinctrl/gpio@fec30000";
        gpio3 = "/pinctrl/gpio@fec40000";
        gpio4 = "/pinctrl/gpio@fec50000";
        i2c0 = "/i2c@fd880000";
        i2c1 = "/i2c@fea90000";
        i2c2 = "/i2c@feaa0000";
        i2c3 = "/i2c@feab0000";
        i2c4 = "/i2c@feac0000";
        i2c5 = "/i2c@fead0000";
        i2c6 = "/i2c@fec80000";
        i2c7 = "/i2c@fec90000";
        i2c8 = "/i2c@feca0000";
        rkcif_mipi_lvds0 = "/rkcif-mipi-lvds";
        rkcif_mipi_lvds1 = "/rkcif-mipi-lvds1";
        rkcif_mipi_lvds2 = "/rkcif-mipi-lvds2";
        rkcif_mipi_lvds3 = "/rkcif-mipi-lvds3";
        rkvenc0 = "/rkvenc-core@fdbd0000";
        rkvenc1 = "/rkvenc-core@fdbe0000";
        jpege0 = "/jpege-core@fdba0000";
        jpege1 = "/jpege-core@fdba4000";
        jpege2 = "/jpege-core@fdba8000";
        jpege3 = "/jpege-core@fdbac000";
        serial0 = "/serial@fd890000";
        serial1 = "/serial@feb40000";
        serial2 = "/serial@feb50000";
        serial3 = "/serial@feb60000";
        serial4 = "/serial@feb70000";
        serial5 = "/serial@feb80000";
        serial6 = "/serial@feb90000";
        serial7 = "/serial@feba0000";
        serial8 = "/serial@febb0000";
        serial9 = "/serial@febc0000";
        spi0 = "/spi@feb00000";
        spi1 = "/spi@feb10000";
        spi2 = "/spi@feb20000";
        spi3 = "/spi@feb30000";
        spi4 = "/spi@fecb0000";
        spi5 = "/spi@fe2b0000";
        csi2dphy3 = "/csi2-dphy3";
        csi2dphy4 = "/csi2-dphy4";
        csi2dphy5 = "/csi2-dphy5";
        dp0 = "/dp@fde50000";
        dp1 = "/dp@fde60000";
        edp0 = "/edp@fdec0000";
        edp1 = "/edp@fded0000";
        ethernet0 = "/ethernet@fe1b0000";
        hdptx0 = "/phy@fed60000";
        hdptx1 = "/phy@fed70000";
        hdptxhdmi0 = "/hdmiphy@fed60000";
        hdptxhdmi1 = "/hdmiphy@fed70000";
        hdmi0 = "/hdmi@fde80000";
        hdmi1 = "/hdmi@fdea0000";
        rkcif_mipi_lvds4 = "/rkcif-mipi-lvds4";
        rkcif_mipi_lvds5 = "/rkcif-mipi-lvds5";
        usbdp0 = "/phy@fed80000";
        usbdp1 = "/phy@fed90000";
    };
    clocks {
        compatible = "simple-bus";
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        spll {
            compatible = "fixed-clock";
            #clock-cells = <0x00000000>;
            clock-frequency = <0x29d7ab80>;
            clock-output-names = "spll";
        };
        xin32k {
            compatible = "fixed-clock";
            #clock-cells = <0x00000000>;
            clock-frequency = <0x00008000>;
            clock-output-names = "xin32k";
        };
        xin24m {
            compatible = "fixed-clock";
            #clock-cells = <0x00000000>;
            clock-frequency = <0x016e3600>;
            clock-output-names = "xin24m";
        };
        hclk_vo1@fd7c08ec {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c08ec 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x00000264>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
            phandle = <0x00000005>;
        };
        aclk_vdpu_low_pre@fd7c08b0 {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c08b0 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x000001bc>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        hclk_vo0@fd7c08dc {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c08dc 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x0000026d>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
            phandle = <0x00000004>;
        };
        hclk_usb@fd7c08a8 {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c08a8 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x00000264>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        hclk_nvm@fd7c087c {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c087c 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x00000141>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
            phandle = <0x00000003>;
        };
        aclk_usb@fd7c08a8 {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c08a8 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x00000263>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        hclk_isp1_pre@fd7c0868 {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c0868 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x000001e1>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        aclk_isp1_pre@fd7c0868 {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c0868 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x000001e0>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        aclk_rkvdec0_pre@fd7c08a0 {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c08a0 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x000001bc>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        hclk_rkvdec0_pre@fd7c08a0 {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c08a0 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x000001be>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        aclk_rkvdec1_pre@fd7c08a4 {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c08a4 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x000001bc>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        hclk_rkvdec1_pre@fd7c08a4 {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c08a4 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x000001be>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        aclk_jpeg_decoder_pre@fd7c08b0 {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c08b0 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x000001bc>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        aclk_rkvenc1_pre@fd7c08c0 {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c08c0 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x000001c5>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        hclk_rkvenc1_pre@fd7c08c0 {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c08c0 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x000001c4>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        aclk_hdcp0_pre@fd7c08dc {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c08dc 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x0000026c>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        aclk_hdcp1_pre@fd7c08ec {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c08ec 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x00000263>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        pclk_av1_pre@fd7c0910 {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c0910 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x000001be>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        aclk_av1_pre@fd7c0910 {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c0910 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000002 0x000001bc>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        hclk_sdio_pre@fd7c092c {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c092c 0x00000000 0x00000010>;
            clock-names = "link";
            clocks = <0x00000003>;
            #power-domain-cells = <0x00000001>;
            #clock-cells = <0x00000000>;
        };
        pclk_vo0_grf@fd7c08dc {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c08dc 0x00000000 0x00000004>;
            clocks = <0x00000004>;
            clock-names = "link";
            #clock-cells = <0x00000000>;
            phandle = <0x00000055>;
        };
        pclk_vo1_grf@fd7c08ec {
            compatible = "rockchip,rk3588-clock-gate-link";
            reg = <0x00000000 0xfd7c08ec 0x00000000 0x00000004>;
            clocks = <0x00000005>;
            clock-names = "link";
            #clock-cells = <0x00000000>;
            phandle = <0x00000056>;
        };
    };
    cpus {
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        cpu-map {
            cluster0 {
                core0 {
                    cpu = <0x00000006>;
                };
                core1 {
                    cpu = <0x00000007>;
                };
                core2 {
                    cpu = <0x00000008>;
                };
                core3 {
                    cpu = <0x00000009>;
                };
            };
            cluster1 {
                core0 {
                    cpu = <0x0000000a>;
                };
                core1 {
                    cpu = <0x0000000b>;
                };
            };
            cluster2 {
                core0 {
                    cpu = <0x0000000c>;
                };
                core1 {
                    cpu = <0x0000000d>;
                };
            };
        };
        cpu@0 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000>;
            enable-method = "psci";
            capacity-dmips-mhz = <0x00000212>;
            clocks = <0x0000000e 0x00000000>;
            operating-points-v2 = <0x0000000f>;
            cpu-idle-states = <0x00000010>;
            i-cache-size = <0x00008000>;
            i-cache-line-size = <0x00000040>;
            i-cache-sets = <0x00000080>;
            d-cache-size = <0x00008000>;
            d-cache-line-size = <0x00000040>;
            d-cache-sets = <0x00000080>;
            next-level-cache = <0x00000011>;
            #cooling-cells = <0x00000002>;
            dynamic-power-coefficient = <0x00000064>;
            cpu-supply = <0x00000012>;
            mem-supply = <0x00000013>;
            phandle = <0x00000006>;
        };
        cpu@100 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000100>;
            enable-method = "psci";
            capacity-dmips-mhz = <0x00000212>;
            clocks = <0x0000000e 0x00000000>;
            operating-points-v2 = <0x0000000f>;
            cpu-idle-states = <0x00000010>;
            i-cache-size = <0x00008000>;
            i-cache-line-size = <0x00000040>;
            i-cache-sets = <0x00000080>;
            d-cache-size = <0x00008000>;
            d-cache-line-size = <0x00000040>;
            d-cache-sets = <0x00000080>;
            next-level-cache = <0x00000014>;
            phandle = <0x00000007>;
        };
        cpu@200 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000200>;
            enable-method = "psci";
            capacity-dmips-mhz = <0x00000212>;
            clocks = <0x0000000e 0x00000000>;
            operating-points-v2 = <0x0000000f>;
            cpu-idle-states = <0x00000010>;
            i-cache-size = <0x00008000>;
            i-cache-line-size = <0x00000040>;
            i-cache-sets = <0x00000080>;
            d-cache-size = <0x00008000>;
            d-cache-line-size = <0x00000040>;
            d-cache-sets = <0x00000080>;
            next-level-cache = <0x00000015>;
            phandle = <0x00000008>;
        };
        cpu@300 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000300>;
            enable-method = "psci";
            capacity-dmips-mhz = <0x00000212>;
            clocks = <0x0000000e 0x00000000>;
            operating-points-v2 = <0x0000000f>;
            cpu-idle-states = <0x00000010>;
            i-cache-size = <0x00008000>;
            i-cache-line-size = <0x00000040>;
            i-cache-sets = <0x00000080>;
            d-cache-size = <0x00008000>;
            d-cache-line-size = <0x00000040>;
            d-cache-sets = <0x00000080>;
            next-level-cache = <0x00000016>;
            phandle = <0x00000009>;
        };
        cpu@400 {
            device_type = "cpu";
            compatible = "arm,cortex-a76";
            reg = <0x00000400>;
            enable-method = "psci";
            capacity-dmips-mhz = <0x00000400>;
            clocks = <0x0000000e 0x00000002>;
            operating-points-v2 = <0x00000017>;
            cpu-idle-states = <0x00000010>;
            i-cache-size = <0x00010000>;
            i-cache-line-size = <0x00000040>;
            i-cache-sets = <0x00000100>;
            d-cache-size = <0x00010000>;
            d-cache-line-size = <0x00000040>;
            d-cache-sets = <0x00000100>;
            next-level-cache = <0x00000018>;
            #cooling-cells = <0x00000002>;
            dynamic-power-coefficient = <0x0000012c>;
            cpu-supply = <0x00000019>;
            mem-supply = <0x0000001a>;
            phandle = <0x0000000a>;
        };
        cpu@500 {
            device_type = "cpu";
            compatible = "arm,cortex-a76";
            reg = <0x00000500>;
            enable-method = "psci";
            capacity-dmips-mhz = <0x00000400>;
            clocks = <0x0000000e 0x00000002>;
            operating-points-v2 = <0x00000017>;
            cpu-idle-states = <0x00000010>;
            i-cache-size = <0x00010000>;
            i-cache-line-size = <0x00000040>;
            i-cache-sets = <0x00000100>;
            d-cache-size = <0x00010000>;
            d-cache-line-size = <0x00000040>;
            d-cache-sets = <0x00000100>;
            next-level-cache = <0x0000001b>;
            phandle = <0x0000000b>;
        };
        cpu@600 {
            device_type = "cpu";
            compatible = "arm,cortex-a76";
            reg = <0x00000600>;
            enable-method = "psci";
            capacity-dmips-mhz = <0x00000400>;
            clocks = <0x0000000e 0x00000003>;
            operating-points-v2 = <0x0000001c>;
            cpu-idle-states = <0x00000010>;
            i-cache-size = <0x00010000>;
            i-cache-line-size = <0x00000040>;
            i-cache-sets = <0x00000100>;
            d-cache-size = <0x00010000>;
            d-cache-line-size = <0x00000040>;
            d-cache-sets = <0x00000100>;
            next-level-cache = <0x0000001d>;
            #cooling-cells = <0x00000002>;
            dynamic-power-coefficient = <0x0000012c>;
            cpu-supply = <0x0000001e>;
            mem-supply = <0x0000001f>;
            phandle = <0x0000000c>;
        };
        cpu@700 {
            device_type = "cpu";
            compatible = "arm,cortex-a76";
            reg = <0x00000700>;
            enable-method = "psci";
            capacity-dmips-mhz = <0x00000400>;
            clocks = <0x0000000e 0x00000003>;
            operating-points-v2 = <0x0000001c>;
            cpu-idle-states = <0x00000010>;
            i-cache-size = <0x00010000>;
            i-cache-line-size = <0x00000040>;
            i-cache-sets = <0x00000100>;
            d-cache-size = <0x00010000>;
            d-cache-line-size = <0x00000040>;
            d-cache-sets = <0x00000100>;
            next-level-cache = <0x00000020>;
            phandle = <0x0000000d>;
        };
        idle-states {
            entry-method = "psci";
            cpu-sleep {
                compatible = "arm,idle-state";
                local-timer-stop;
                arm,psci-suspend-param = <0x00010000>;
                entry-latency-us = <0x00000064>;
                exit-latency-us = <0x00000078>;
                min-residency-us = <0x000003e8>;
                phandle = <0x00000010>;
            };
        };
        l2-cache-l0 {
            compatible = "cache";
            cache-size = <0x00020000>;
            cache-line-size = <0x00000040>;
            cache-sets = <0x00000200>;
            next-level-cache = <0x00000021>;
            phandle = <0x00000011>;
        };
        l2-cache-l1 {
            compatible = "cache";
            cache-size = <0x00020000>;
            cache-line-size = <0x00000040>;
            cache-sets = <0x00000200>;
            next-level-cache = <0x00000021>;
            phandle = <0x00000014>;
        };
        l2-cache-l2 {
            compatible = "cache";
            cache-size = <0x00020000>;
            cache-line-size = <0x00000040>;
            cache-sets = <0x00000200>;
            next-level-cache = <0x00000021>;
            phandle = <0x00000015>;
        };
        l2-cache-l3 {
            compatible = "cache";
            cache-size = <0x00020000>;
            cache-line-size = <0x00000040>;
            cache-sets = <0x00000200>;
            next-level-cache = <0x00000021>;
            phandle = <0x00000016>;
        };
        l2-cache-b0 {
            compatible = "cache";
            cache-size = <0x00080000>;
            cache-line-size = <0x00000040>;
            cache-sets = <0x00000400>;
            next-level-cache = <0x00000021>;
            phandle = <0x00000018>;
        };
        l2-cache-b1 {
            compatible = "cache";
            cache-size = <0x00080000>;
            cache-line-size = <0x00000040>;
            cache-sets = <0x00000400>;
            next-level-cache = <0x00000021>;
            phandle = <0x0000001b>;
        };
        l2-cache-b2 {
            compatible = "cache";
            cache-size = <0x00080000>;
            cache-line-size = <0x00000040>;
            cache-sets = <0x00000400>;
            next-level-cache = <0x00000021>;
            phandle = <0x0000001d>;
        };
        l2-cache-b3 {
            compatible = "cache";
            cache-size = <0x00080000>;
            cache-line-size = <0x00000040>;
            cache-sets = <0x00000400>;
            next-level-cache = <0x00000021>;
            phandle = <0x00000020>;
        };
        l3-cache {
            compatible = "cache";
            cache-size = <0x00300000>;
            cache-line-size = <0x00000040>;
            cache-sets = <0x00001000>;
            phandle = <0x00000021>;
        };
    };
    cluster0-opp-table {
        compatible = "operating-points-v2";
        opp-shared;
        rockchip,pvtm-voltage-sel = <0x00000000 0x00000582 0x00000000 0x00000583 0x0000059a 0x00000001 0x0000059b 0x000005b2 0x00000002 0x000005b3 0x000005ca 0x00000003 0x000005cb 0x000005e2 0x00000004 0x000005e3 0x000005fa 0x00000005 0x000005fb 0x0000270f 0x00000006>;
        rockchip,pvtm-pvtpll;
        rockchip,pvtm-offset = <0x00000064>;
        rockchip,pvtm-sample-time = <0x0000044c>;
        rockchip,pvtm-freq = <0x00159b40>;
        rockchip,pvtm-volt = <0x000b71b0>;
        rockchip,pvtm-ref-temp = <0x00000019>;
        rockchip,pvtm-temp-prop = <0x000000f4 0x000000f4>;
        rockchip,pvtm-thermal-zone = "soc-thermal";
        rockchip,grf = <0x00000022>;
        rockchip,reboot-freq = <0x00159b40>;
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-min-volt = <0x000b1008>;
        phandle = <0x0000000f>;
        opp-408000000 {
            opp-hz = <0x00000000 0x18519600>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000e7ef0 0x000a4cb8 0x000a4cb8 0x000e7ef0>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000e7ef0 0x000a4cb8 0x000a4cb8 0x000e7ef0>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-816000000 {
            opp-hz = <0x00000000 0x30a32c00>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000e7ef0 0x000a4cb8 0x000a4cb8 0x000e7ef0>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1008000000 {
            opp-hz = <0x00000000 0x3c14dc00>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000e7ef0 0x000a4cb8 0x000a4cb8 0x000e7ef0>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1200000000 {
            opp-hz = <0x00000000 0x47868c00>;
            opp-microvolt = <0x000aae60 0x000aae60 0x000e7ef0 0x000aae60 0x000aae60 0x000e7ef0>;
            opp-microvolt-L1 = <0x000a7d8c 0x000a7d8c 0x000e7ef0 0x000a7d8c 0x000a7d8c 0x000e7ef0>;
            opp-microvolt-L2 = <0x000a7d8c 0x000a7d8c 0x000e7ef0 0x000a7d8c 0x000a7d8c 0x000e7ef0>;
            opp-microvolt-L3 = <0x000a7d8c 0x000a7d8c 0x000e7ef0 0x000a7d8c 0x000a7d8c 0x000e7ef0>;
            opp-microvolt-L4 = <0x000a4cb8 0x000a4cb8 0x000e7ef0 0x000a4cb8 0x000a4cb8 0x000e7ef0>;
            opp-microvolt-L5 = <0x000a4cb8 0x000a4cb8 0x000e7ef0 0x000a4cb8 0x000a4cb8 0x000e7ef0>;
            opp-microvolt-L6 = <0x000a4cb8 0x000a4cb8 0x000e7ef0 0x000a4cb8 0x000a4cb8 0x000e7ef0>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1416000000 {
            opp-hz = <0x00000000 0x54667200>;
            opp-microvolt = <0x000ba284 0x000ba284 0x000e7ef0 0x000ba284 0x000ba284 0x000e7ef0>;
            opp-microvolt-L1 = <0x000b71b0 0x000b71b0 0x000e7ef0 0x000b71b0 0x000b71b0 0x000e7ef0>;
            opp-microvolt-L2 = <0x000b40dc 0x000b40dc 0x000e7ef0 0x000b40dc 0x000b40dc 0x000e7ef0>;
            opp-microvolt-L3 = <0x000b1008 0x000b1008 0x000e7ef0 0x000b1008 0x000b1008 0x000e7ef0>;
            opp-microvolt-L4 = <0x000b1008 0x000b1008 0x000e7ef0 0x000b1008 0x000b1008 0x000e7ef0>;
            opp-microvolt-L5 = <0x000adf34 0x000adf34 0x000e7ef0 0x000adf34 0x000adf34 0x000e7ef0>;
            opp-microvolt-L6 = <0x000adf34 0x000adf34 0x000e7ef0 0x000adf34 0x000adf34 0x000e7ef0>;
            clock-latency-ns = <0x00009c40>;
            opp-suspend;
        };
        opp-1608000000 {
            opp-hz = <0x00000000 0x5fd82200>;
            opp-microvolt = <0x000cf850 0x000cf850 0x000e7ef0 0x000cf850 0x000cf850 0x000e7ef0>;
            opp-microvolt-L1 = <0x000cc77c 0x000cc77c 0x000e7ef0 0x000cc77c 0x000cc77c 0x000e7ef0>;
            opp-microvolt-L2 = <0x000c96a8 0x000c96a8 0x000e7ef0 0x000c96a8 0x000c96a8 0x000e7ef0>;
            opp-microvolt-L3 = <0x000c65d4 0x000c65d4 0x000e7ef0 0x000c65d4 0x000c65d4 0x000e7ef0>;
            opp-microvolt-L4 = <0x000c3500 0x000c3500 0x000e7ef0 0x000c3500 0x000c3500 0x000e7ef0>;
            opp-microvolt-L5 = <0x000c3500 0x000c3500 0x000e7ef0 0x000c3500 0x000c3500 0x000e7ef0>;
            opp-microvolt-L6 = <0x000c042c 0x000c042c 0x000e7ef0 0x000c042c 0x000c042c 0x000e7ef0>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1800000000 {
            opp-hz = <0x00000000 0x6b49d200>;
            opp-microvolt = <0x000e7ef0 0x000e7ef0 0x000e7ef0 0x000e7ef0 0x000e7ef0 0x000e7ef0>;
            opp-microvolt-L1 = <0x000e4e1c 0x000e4e1c 0x000e7ef0 0x000e4e1c 0x000e4e1c 0x000e7ef0>;
            opp-microvolt-L2 = <0x000e1d48 0x000e1d48 0x000e7ef0 0x000e1d48 0x000e1d48 0x000e7ef0>;
            opp-microvolt-L3 = <0x000dec74 0x000dec74 0x000e7ef0 0x000dec74 0x000dec74 0x000e7ef0>;
            opp-microvolt-L4 = <0x000dbba0 0x000dbba0 0x000e7ef0 0x000dbba0 0x000dbba0 0x000e7ef0>;
            opp-microvolt-L5 = <0x000d8acc 0x000d8acc 0x000e7ef0 0x000d8acc 0x000d8acc 0x000e7ef0>;
            opp-microvolt-L6 = <0x000d59f8 0x000d59f8 0x000e7ef0 0x000d59f8 0x000d59f8 0x000e7ef0>;
            clock-latency-ns = <0x00009c40>;
        };
    };
    cluster1-opp-table {
        compatible = "operating-points-v2";
        opp-shared;
        rockchip,pvtm-voltage-sel = <0x00000000 0x00000668 0x00000000 0x00000669 0x0000068b 0x00000001 0x0000068c 0x000006ae 0x00000002 0x000006af 0x000006cf 0x00000003 0x000006d0 0x000006f0 0x00000004 0x000006f1 0x0000270f 0x00000005>;
        rockchip,pvtm-pvtpll;
        rockchip,pvtm-offset = <0x00000018>;
        rockchip,pvtm-sample-time = <0x0000044c>;
        rockchip,pvtm-freq = <0x00188940>;
        rockchip,pvtm-volt = <0x000b71b0>;
        rockchip,pvtm-ref-temp = <0x00000019>;
        rockchip,pvtm-temp-prop = <0x0000010e 0x0000010e>;
        rockchip,pvtm-thermal-zone = "soc-thermal";
        rockchip,grf = <0x00000023>;
        volt-mem-read-margin = <0x000d0bd8 0x00000001 0x000bac48 0x00000002 0x000a4cb8 0x00000003 0x00078d98 0x00000004>;
        low-volt-mem-read-margin = <0x00000004>;
        intermediate-threshold-freq = <0x000f6180>;
        rockchip,idle-threshold-freq = <0x00249f00>;
        rockchip,reboot-freq = <0x001b7740>;
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-min-volt = <0x000b1008>;
        phandle = <0x00000017>;
        opp-408000000 {
            opp-hz = <0x00000000 0x18519600>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
            opp-suspend;
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-816000000 {
            opp-hz = <0x00000000 0x30a32c00>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1008000000 {
            opp-hz = <0x00000000 0x3c14dc00>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1200000000 {
            opp-hz = <0x00000000 0x47868c00>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1416000000 {
            opp-hz = <0x00000000 0x54667200>;
            opp-microvolt = <0x000aae60 0x000aae60 0x000f4240 0x000aae60 0x000aae60 0x000f4240>;
            opp-microvolt-L1 = <0x000a7d8c 0x000a7d8c 0x000f4240 0x000a7d8c 0x000a7d8c 0x000f4240>;
            opp-microvolt-L2 = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            opp-microvolt-L3 = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            opp-microvolt-L4 = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            opp-microvolt-L5 = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1608000000 {
            opp-hz = <0x00000000 0x5fd82200>;
            opp-microvolt = <0x000b71b0 0x000b71b0 0x000f4240 0x000b71b0 0x000b71b0 0x000f4240>;
            opp-microvolt-L1 = <0x000b40dc 0x000b40dc 0x000f4240 0x000b40dc 0x000b40dc 0x000f4240>;
            opp-microvolt-L2 = <0x000b1008 0x000b1008 0x000f4240 0x000b1008 0x000b1008 0x000f4240>;
            opp-microvolt-L3 = <0x000adf34 0x000adf34 0x000f4240 0x000adf34 0x000adf34 0x000f4240>;
            opp-microvolt-L4 = <0x000aae60 0x000aae60 0x000f4240 0x000aae60 0x000aae60 0x000f4240>;
            opp-microvolt-L5 = <0x000aae60 0x000aae60 0x000f4240 0x000aae60 0x000aae60 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1800000000 {
            opp-hz = <0x00000000 0x6b49d200>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240 0x000c96a8 0x000c96a8 0x000f4240>;
            opp-microvolt-L1 = <0x000c65d4 0x000c65d4 0x000f4240 0x000c65d4 0x000c65d4 0x000f4240>;
            opp-microvolt-L2 = <0x000c3500 0x000c3500 0x000f4240 0x000c3500 0x000c3500 0x000f4240>;
            opp-microvolt-L3 = <0x000c042c 0x000c042c 0x000f4240 0x000c042c 0x000c042c 0x000f4240>;
            opp-microvolt-L4 = <0x000bd358 0x000bd358 0x000f4240 0x000bd358 0x000bd358 0x000f4240>;
            opp-microvolt-L5 = <0x000ba284 0x000ba284 0x000f4240 0x000ba284 0x000ba284 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-2016000000 {
            opp-hz = <0x00000000 0x7829b800>;
            opp-microvolt = <0x000dbba0 0x000dbba0 0x000f4240 0x000dbba0 0x000dbba0 0x000f4240>;
            opp-microvolt-L1 = <0x000d8acc 0x000d8acc 0x000f4240 0x000d8acc 0x000d8acc 0x000f4240>;
            opp-microvolt-L2 = <0x000d59f8 0x000d59f8 0x000f4240 0x000d59f8 0x000d59f8 0x000f4240>;
            opp-microvolt-L3 = <0x000d2924 0x000d2924 0x000f4240 0x000d2924 0x000d2924 0x000f4240>;
            opp-microvolt-L4 = <0x000cf850 0x000cf850 0x000f4240 0x000cf850 0x000cf850 0x000f4240>;
            opp-microvolt-L5 = <0x000cc77c 0x000cc77c 0x000f4240 0x000cc77c 0x000cc77c 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-2208000000 {
            opp-hz = <0x00000000 0x839b6800>;
            opp-microvolt = <0x000ee098 0x000ee098 0x000f4240 0x000ee098 0x000ee098 0x000f4240>;
            opp-microvolt-L2 = <0x000eafc4 0x000eafc4 0x000f4240 0x000eafc4 0x000eafc4 0x000f4240>;
            opp-microvolt-L3 = <0x000e7ef0 0x000e7ef0 0x000f4240 0x000e7ef0 0x000e7ef0 0x000f4240>;
            opp-microvolt-L4 = <0x000e1d48 0x000e1d48 0x000f4240 0x000e1d48 0x000e1d48 0x000f4240>;
            opp-microvolt-L5 = <0x000dec74 0x000dec74 0x000f4240 0x000dec74 0x000dec74 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-2400000000 {
            opp-hz = <0x00000000 0x8f0d1800>;
            opp-microvolt = <0x000f4240 0x000f4240 0x000f4240 0x000f4240 0x000f4240 0x000f4240>;
            opp-microvolt-L3 = <0x000f116c 0x000f116c 0x000f4240 0x000f116c 0x000f116c 0x000f4240>;
            opp-microvolt-L4 = <0x000ee098 0x000ee098 0x000f4240 0x000ee098 0x000ee098 0x000f4240>;
            opp-microvolt-L5 = <0x000eafc4 0x000eafc4 0x000f4240 0x000eafc4 0x000eafc4 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
    };
    cluster2-opp-table {
        compatible = "operating-points-v2";
        opp-shared;
        rockchip,pvtm-voltage-sel = <0x00000000 0x00000668 0x00000000 0x00000669 0x0000068b 0x00000001 0x0000068c 0x000006ae 0x00000002 0x000006af 0x000006cf 0x00000003 0x000006d0 0x000006f0 0x00000004 0x000006f1 0x0000270f 0x00000005>;
        rockchip,pvtm-pvtpll;
        rockchip,pvtm-offset = <0x00000018>;
        rockchip,pvtm-sample-time = <0x0000044c>;
        rockchip,pvtm-freq = <0x00188940>;
        rockchip,pvtm-volt = <0x000b71b0>;
        rockchip,pvtm-ref-temp = <0x00000019>;
        rockchip,pvtm-temp-prop = <0x0000010e 0x0000010e>;
        rockchip,pvtm-thermal-zone = "soc-thermal";
        rockchip,grf = <0x00000024>;
        volt-mem-read-margin = <0x000d0bd8 0x00000001 0x000bac48 0x00000002 0x000a4cb8 0x00000003 0x00078d98 0x00000004>;
        low-volt-mem-read-margin = <0x00000004>;
        intermediate-threshold-freq = <0x000f6180>;
        rockchip,idle-threshold-freq = <0x00249f00>;
        rockchip,reboot-freq = <0x001b7740>;
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-min-volt = <0x000b1008>;
        phandle = <0x0000001c>;
        opp-408000000 {
            opp-hz = <0x00000000 0x18519600>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
            opp-suspend;
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-816000000 {
            opp-hz = <0x00000000 0x30a32c00>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1008000000 {
            opp-hz = <0x00000000 0x3c14dc00>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1200000000 {
            opp-hz = <0x00000000 0x47868c00>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1416000000 {
            opp-hz = <0x00000000 0x54667200>;
            opp-microvolt = <0x000aae60 0x000aae60 0x000f4240 0x000aae60 0x000aae60 0x000f4240>;
            opp-microvolt-L1 = <0x000a7d8c 0x000a7d8c 0x000f4240 0x000a7d8c 0x000a7d8c 0x000f4240>;
            opp-microvolt-L2 = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            opp-microvolt-L3 = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            opp-microvolt-L4 = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            opp-microvolt-L5 = <0x000a4cb8 0x000a4cb8 0x000f4240 0x000a4cb8 0x000a4cb8 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1608000000 {
            opp-hz = <0x00000000 0x5fd82200>;
            opp-microvolt = <0x000b71b0 0x000b71b0 0x000f4240 0x000b71b0 0x000b71b0 0x000f4240>;
            opp-microvolt-L1 = <0x000b40dc 0x000b40dc 0x000f4240 0x000b40dc 0x000b40dc 0x000f4240>;
            opp-microvolt-L2 = <0x000b1008 0x000b1008 0x000f4240 0x000b1008 0x000b1008 0x000f4240>;
            opp-microvolt-L3 = <0x000adf34 0x000adf34 0x000f4240 0x000adf34 0x000adf34 0x000f4240>;
            opp-microvolt-L4 = <0x000aae60 0x000aae60 0x000f4240 0x000aae60 0x000aae60 0x000f4240>;
            opp-microvolt-L5 = <0x000aae60 0x000aae60 0x000f4240 0x000aae60 0x000aae60 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1800000000 {
            opp-hz = <0x00000000 0x6b49d200>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240 0x000c96a8 0x000c96a8 0x000f4240>;
            opp-microvolt-L1 = <0x000c65d4 0x000c65d4 0x000f4240 0x000c65d4 0x000c65d4 0x000f4240>;
            opp-microvolt-L2 = <0x000c3500 0x000c3500 0x000f4240 0x000c3500 0x000c3500 0x000f4240>;
            opp-microvolt-L3 = <0x000c042c 0x000c042c 0x000f4240 0x000c042c 0x000c042c 0x000f4240>;
            opp-microvolt-L4 = <0x000bd358 0x000bd358 0x000f4240 0x000bd358 0x000bd358 0x000f4240>;
            opp-microvolt-L5 = <0x000ba284 0x000ba284 0x000f4240 0x000ba284 0x000ba284 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-2016000000 {
            opp-hz = <0x00000000 0x7829b800>;
            opp-microvolt = <0x000dbba0 0x000dbba0 0x000f4240 0x000dbba0 0x000dbba0 0x000f4240>;
            opp-microvolt-L1 = <0x000d8acc 0x000d8acc 0x000f4240 0x000d8acc 0x000d8acc 0x000f4240>;
            opp-microvolt-L2 = <0x000d59f8 0x000d59f8 0x000f4240 0x000d59f8 0x000d59f8 0x000f4240>;
            opp-microvolt-L3 = <0x000d2924 0x000d2924 0x000f4240 0x000d2924 0x000d2924 0x000f4240>;
            opp-microvolt-L4 = <0x000cf850 0x000cf850 0x000f4240 0x000cf850 0x000cf850 0x000f4240>;
            opp-microvolt-L5 = <0x000cc77c 0x000cc77c 0x000f4240 0x000cc77c 0x000cc77c 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-2208000000 {
            opp-hz = <0x00000000 0x839b6800>;
            opp-microvolt = <0x000ee098 0x000ee098 0x000f4240 0x000ee098 0x000ee098 0x000f4240>;
            opp-microvolt-L2 = <0x000eafc4 0x000eafc4 0x000f4240 0x000eafc4 0x000eafc4 0x000f4240>;
            opp-microvolt-L3 = <0x000e7ef0 0x000e7ef0 0x000f4240 0x000e7ef0 0x000e7ef0 0x000f4240>;
            opp-microvolt-L4 = <0x000e1d48 0x000e1d48 0x000f4240 0x000e1d48 0x000e1d48 0x000f4240>;
            opp-microvolt-L5 = <0x000dec74 0x000dec74 0x000f4240 0x000dec74 0x000dec74 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-2400000000 {
            opp-hz = <0x00000000 0x8f0d1800>;
            opp-microvolt = <0x000f4240 0x000f4240 0x000f4240 0x000f4240 0x000f4240 0x000f4240>;
            opp-microvolt-L3 = <0x000f116c 0x000f116c 0x000f4240 0x000f116c 0x000f116c 0x000f4240>;
            opp-microvolt-L4 = <0x000ee098 0x000ee098 0x000f4240 0x000ee098 0x000ee098 0x000f4240>;
            opp-microvolt-L5 = <0x000eafc4 0x000eafc4 0x000f4240 0x000eafc4 0x000eafc4 0x000f4240>;
            clock-latency-ns = <0x00009c40>;
        };
    };
    arm-pmu {
        compatible = "arm,armv8-pmuv3";
        interrupts = <0x00000001 0x00000007 0x00000008>;
        interrupt-affinity = <0x00000006 0x00000007 0x00000008 0x00000009 0x0000000a 0x0000000b 0x0000000c 0x0000000d>;
    };
    cpuinfo {
        compatible = "rockchip,cpuinfo";
        nvmem-cells = <0x00000025 0x00000026 0x00000027>;
        nvmem-cell-names = "id", "cpu-version", "cpu-code";
    };
    csi2-dcphy0 {
        compatible = "rockchip,rk3588-csi2-dcphy";
        rockchip,hw = <0x00000028>;
        status = "disabled";
    };
    csi2-dcphy1 {
        compatible = "rockchip,rk3588-csi2-dcphy";
        rockchip,hw = <0x00000029>;
        status = "disabled";
    };
    csi2-dphy0 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x0000002a>;
        status = "disabled";
    };
    csi2-dphy1 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x0000002a>;
        status = "disabled";
    };
    csi2-dphy2 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x0000002a>;
        status = "disabled";
    };
    display-subsystem {
        compatible = "rockchip,display-subsystem";
        ports = <0x0000002b>;
        memory-region = <0x0000002c>;
        memory-region-names = "drm-logo";
        route {
            route-dp0 {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x0000002d>;
            };
            route-dsi0 {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x0000002e>;
            };
            route-dsi1 {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x0000002f>;
            };
            route-edp0 {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000030>;
            };
            route-edp1 {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
            };
            route-hdmi0 {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000031>;
            };
            route-rgb {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000032>;
            };
            route-dp1 {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000033>;
            };
            route-hdmi1 {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000034>;
            };
        };
    };
    dmc {
        compatible = "rockchip,rk3588-dmc";
        interrupts = <0x00000000 0x00000049 0x00000004>;
        interrupt-names = "complete";
        devfreq-events = <0x00000035>;
        clocks = <0x0000000e 0x00000004>;
        clock-names = "dmc_clk";
        operating-points-v2 = <0x00000036>;
        upthreshold = <0x00000028>;
        downdifferential = <0x00000014>;
        system-status-level = <0x00000001 0x00000004 0x00000008 0x00000008 0x00000002 0x00000001 0x00000010 0x00000004 0x00010000 0x00000004 0x00001000 0x00000008 0x00004000 0x00000008 0x00002000 0x00000008 0x00000c00 0x00000008>;
        auto-freq-en = <0x00000001>;
        status = "okay";
        center-supply = <0x00000037>;
    };
    dmc-opp-table {
        compatible = "operating-points-v2";
        phandle = <0x00000036>;
        opp-2750000000 {
            opp-hz = <0x00000000 0xa3e9ab80>;
            opp-microvolt = <0x000cf850>;
        };
    };
    firmware {
        scmi {
            compatible = "arm,scmi-smc";
            shmem = <0x00000038>;
            arm,smc-id = <0x82000010>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            protocol@14 {
                reg = <0x00000014>;
                #clock-cells = <0x00000001>;
                assigned-clocks = <0x0000000e 0x00000000 0x0000000e 0x00000002 0x0000000e 0x00000003>;
                assigned-clock-rates = <0x30a32c00 0x30a32c00 0x30a32c00>;
                phandle = <0x0000000e>;
            };
            protocol@16 {
                reg = <0x00000016>;
                #reset-cells = <0x00000001>;
                phandle = <0x000000f0>;
            };
        };
        sdei {
            compatible = "arm,sdei-1.0";
            method = "smc";
        };
        optee {
            compatible = "linaro,optee-tz";
            method = "smc";
        };
    };
    jpege-ccu {
        compatible = "rockchip,vpu-encoder-v2-ccu";
        status = "okay";
        phandle = <0x0000009b>;
    };
    mpp-srv {
        compatible = "rockchip,mpp-service";
        rockchip,taskqueue-count = <0x0000000c>;
        status = "okay";
        phandle = <0x00000096>;
    };
    psci {
        compatible = "arm,psci-1.0";
        method = "smc";
    };
    rkcif-dvp {
        compatible = "rockchip,rkcif-dvp";
        rockchip,hw = <0x00000039>;
        iommus = <0x0000003a>;
        status = "disabled";
        phandle = <0x0000003b>;
    };
    rkcif-dvp-sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x0000003b>;
        status = "disabled";
    };
    rkcif-mipi-lvds {
        compatible = "rockchip,rkcif-mipi-lvds";
        rockchip,hw = <0x00000039>;
        iommus = <0x0000003a>;
        status = "disabled";
        phandle = <0x0000003c>;
    };
    rkcif-mipi-lvds_sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x0000003c>;
        status = "disabled";
    };
    rkcif-mipi-lvds1 {
        compatible = "rockchip,rkcif-mipi-lvds";
        rockchip,hw = <0x00000039>;
        iommus = <0x0000003a>;
        status = "disabled";
        phandle = <0x0000003d>;
    };
    rkcif-mipi-lvds1-sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x0000003d>;
        status = "disabled";
    };
    rkcif-mipi-lvds2 {
        compatible = "rockchip,rkcif-mipi-lvds";
        rockchip,hw = <0x00000039>;
        iommus = <0x0000003a>;
        status = "disabled";
        phandle = <0x0000003e>;
    };
    rkcif-mipi-lvds2-sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x0000003e>;
        status = "disabled";
    };
    rkcif-mipi-lvds3 {
        compatible = "rockchip,rkcif-mipi-lvds";
        rockchip,hw = <0x00000039>;
        iommus = <0x0000003a>;
        status = "disabled";
        phandle = <0x0000003f>;
    };
    rkcif-mipi-lvds3-sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x0000003f>;
        status = "disabled";
    };
    rkisp0-vir0 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x00000040>;
        status = "disabled";
    };
    rkisp0-vir1 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x00000040>;
        status = "disabled";
    };
    rkisp0-vir2 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x00000040>;
        status = "disabled";
    };
    rkisp0-vir3 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x00000040>;
        status = "disabled";
    };
    rkisp1-vir0 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x00000041>;
        status = "disabled";
    };
    rkisp1-vir1 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x00000041>;
        status = "disabled";
    };
    rkisp1-vir2 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x00000041>;
        status = "disabled";
    };
    rkisp1-vir3 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x00000041>;
        status = "disabled";
    };
    rkispp0-vir0 {
        compatible = "rockchip,rk3588-rkispp-vir";
        rockchip,hw = <0x00000042>;
        status = "disabled";
    };
    rkispp1-vir0 {
        compatible = "rockchip,rk3588-rkispp-vir";
        rockchip,hw = <0x00000043>;
        status = "disabled";
    };
    rkvenc-ccu {
        compatible = "rockchip,rkv-encoder-v2-ccu";
        status = "okay";
        phandle = <0x000000a1>;
    };
    rockchip-suspend {
        compatible = "rockchip,pm-rk3588";
        status = "disabled";
        rockchip,sleep-debug-en = <0x00000000>;
        rockchip,sleep-mode-config = <0x01000608>;
        rockchip,wakeup-config = <0x00000100>;
    };
    rockchip-system-monitor {
        compatible = "rockchip,system-monitor";
        rockchip,thermal-zone = "soc-thermal";
    };
    thermal-zones {
        soc-thermal {
            polling-delay-passive = <0x00000014>;
            polling-delay = <0x000003e8>;
            sustainable-power = <0x00000834>;
            thermal-sensors = <0x00000044 0x00000000>;
            trips {
                trip-point-0 {
                    temperature = <0x000124f8>;
                    hysteresis = <0x000007d0>;
                    type = "passive";
                };
                trip-point-1 {
                    temperature = <0x00014c08>;
                    hysteresis = <0x000007d0>;
                    type = "passive";
                    phandle = <0x00000045>;
                };
                soc-crit {
                    temperature = <0x0001c138>;
                    hysteresis = <0x000007d0>;
                    type = "critical";
                };
            };
            cooling-maps {
                map0 {
                    trip = <0x00000045>;
                    cooling-device = <0x00000006 0xffffffff 0xffffffff>;
                    contribution = <0x00000400>;
                };
                map1 {
                    trip = <0x00000045>;
                    cooling-device = <0x0000000a 0xffffffff 0xffffffff>;
                    contribution = <0x00000400>;
                };
                map2 {
                    trip = <0x00000045>;
                    cooling-device = <0x0000000c 0xffffffff 0xffffffff>;
                    contribution = <0x00000400>;
                };
                map3 {
                    trip = <0x00000045>;
                    cooling-device = <0x00000046 0xffffffff 0xffffffff>;
                    contribution = <0x00000400>;
                };
            };
        };
        bigcore0-thermal {
            polling-delay-passive = <0x00000014>;
            polling-delay = <0x000003e8>;
            thermal-sensors = <0x00000044 0x00000001>;
        };
        bigcore1-thermal {
            polling-delay-passive = <0x00000014>;
            polling-delay = <0x000003e8>;
            thermal-sensors = <0x00000044 0x00000002>;
        };
        littlecore-thermal {
            polling-delay-passive = <0x00000014>;
            polling-delay = <0x000003e8>;
            thermal-sensors = <0x00000044 0x00000003>;
        };
        center-thermal {
            polling-delay-passive = <0x00000014>;
            polling-delay = <0x000003e8>;
            thermal-sensors = <0x00000044 0x00000004>;
        };
        gpu-thermal {
            polling-delay-passive = <0x00000014>;
            polling-delay = <0x000003e8>;
            thermal-sensors = <0x00000044 0x00000005>;
        };
        npu-thermal {
            polling-delay-passive = <0x00000014>;
            polling-delay = <0x000003e8>;
            thermal-sensors = <0x00000044 0x00000006>;
        };
    };
    timer {
        compatible = "arm,armv8-timer";
        interrupts = <0x00000001 0x0000000d 0x00000f04 0x00000001 0x0000000e 0x00000f04 0x00000001 0x0000000b 0x00000f04 0x00000001 0x0000000a 0x00000f04>;
    };
    sram@10f000 {
        compatible = "mmio-sram";
        reg = <0x00000000 0x0010f000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        ranges = <0x00000000 0x00000000 0x0010f000 0x00000100>;
        sram@0 {
            compatible = "arm,scmi-shmem";
            reg = <0x00000000 0x00000100>;
            phandle = <0x00000038>;
        };
    };
    gpu@fb000000 {
        compatible = "arm,mali-bifrost";
        reg = <0x00000000 0xfb000000 0x00000000 0x00200000>;
        interrupts = <0x00000000 0x0000005e 0x00000004 0x00000000 0x0000005d 0x00000004 0x00000000 0x0000005c 0x00000004>;
        interrupt-names = "GPU", "MMU", "JOB";
        clocks = <0x0000000e 0x00000005 0x00000002 0x00000115 0x00000002 0x00000116 0x00000002 0x00000114>;
        clock-names = "clk_mali", "clk_gpu_coregroup", "clk_gpu_stacks", "clk_gpu";
        assigned-clocks = <0x0000000e 0x00000005>;
        assigned-clock-rates = <0x0bebc200>;
        power-domains = <0x00000047 0x0000000c>;
        operating-points-v2 = <0x00000048>;
        #cooling-cells = <0x00000002>;
        dynamic-power-coefficient = <0x00000ba6>;
        upthreshold = <0x0000001e>;
        downdifferential = <0x0000000a>;
        status = "okay";
        mali-supply = <0x00000049>;
        mem-supply = <0x0000004a>;
        phandle = <0x00000046>;
    };
    gpu-opp-table {
        compatible = "operating-points-v2";
        rockchip,pvtm-voltage-sel = <0x00000000 0x0000033e 0x00000000 0x0000033f 0x00000357 0x00000001 0x00000358 0x00000370 0x00000002 0x00000371 0x00000389 0x00000003 0x0000038a 0x000003a2 0x00000004 0x000003a3 0x0000270f 0x00000005>;
        rockchip,pvtm-pvtpll;
        rockchip,pvtm-offset = <0x0000001c>;
        rockchip,pvtm-sample-time = <0x0000044c>;
        rockchip,pvtm-freq = <0x000c3500>;
        rockchip,pvtm-volt = <0x000b71b0>;
        rockchip,pvtm-ref-temp = <0x00000019>;
        rockchip,pvtm-temp-prop = <0xffffff79 0xffffff79>;
        rockchip,pvtm-thermal-zone = "gpu-thermal";
        clocks = <0x00000002 0x00000114>;
        clock-names = "clk";
        rockchip,grf = <0x0000004b>;
        volt-mem-read-margin = <0x000d0bd8 0x00000001 0x000bac48 0x00000002 0x000a4cb8 0x00000003 0x00078d98 0x00000004>;
        low-volt-mem-read-margin = <0x00000004>;
        intermediate-threshold-freq = <0x00061a80>;
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-min-volt = <0x000b1008>;
        phandle = <0x00000048>;
        opp-300000000 {
            opp-hz = <0x00000000 0x11e1a300>;
            opp-microvolt = <0x00098968 0x00098968 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
        };
        opp-400000000 {
            opp-hz = <0x00000000 0x17d78400>;
            opp-microvolt = <0x00098968 0x00098968 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
        };
        opp-500000000 {
            opp-hz = <0x00000000 0x1dcd6500>;
            opp-microvolt = <0x00098968 0x00098968 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000a1be4 0x000a1be4 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
            opp-microvolt-L2 = <0x0009eb10 0x0009eb10 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
            opp-microvolt-L3 = <0x0009ba3c 0x0009ba3c 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
            opp-microvolt-L4 = <0x00098968 0x00098968 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
            opp-microvolt-L5 = <0x00098968 0x00098968 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
        };
        opp-700000000 {
            opp-hz = <0x00000000 0x29b92700>;
            opp-microvolt = <0x000aae60 0x000aae60 0x000cf850 0x000aae60 0x000aae60 0x000cf850>;
            opp-microvolt-L2 = <0x000a7d8c 0x000a7d8c 0x000cf850 0x000a7d8c 0x000a7d8c 0x000cf850>;
            opp-microvolt-L3 = <0x000a4cb8 0x000a4cb8 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
            opp-microvolt-L4 = <0x000a1be4 0x000a1be4 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
            opp-microvolt-L5 = <0x000a1be4 0x000a1be4 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
        };
        opp-800000000 {
            opp-hz = <0x00000000 0x2faf0800>;
            opp-microvolt = <0x000b71b0 0x000b71b0 0x000cf850 0x000b71b0 0x000b71b0 0x000cf850>;
            opp-microvolt-L1 = <0x000b40dc 0x000b40dc 0x000cf850 0x000b40dc 0x000b40dc 0x000cf850>;
            opp-microvolt-L2 = <0x000b1008 0x000b1008 0x000cf850 0x000b1008 0x000b1008 0x000cf850>;
            opp-microvolt-L3 = <0x000adf34 0x000adf34 0x000cf850 0x000adf34 0x000adf34 0x000cf850>;
            opp-microvolt-L4 = <0x000aae60 0x000aae60 0x000cf850 0x000aae60 0x000aae60 0x000cf850>;
            opp-microvolt-L5 = <0x000aae60 0x000aae60 0x000cf850 0x000aae60 0x000aae60 0x000cf850>;
        };
        opp-900000000 {
            opp-hz = <0x00000000 0x35a4e900>;
            opp-microvolt = <0x000c3500 0x000c3500 0x000cf850 0x000c3500 0x000c3500 0x000cf850>;
            opp-microvolt-L1 = <0x000c042c 0x000c042c 0x000cf850 0x000c042c 0x000c042c 0x000cf850>;
            opp-microvolt-L2 = <0x000bd358 0x000bd358 0x000cf850 0x000bd358 0x000bd358 0x000cf850>;
            opp-microvolt-L3 = <0x000ba284 0x000ba284 0x000cf850 0x000ba284 0x000ba284 0x000cf850>;
            opp-microvolt-L4 = <0x000b71b0 0x000b71b0 0x000cf850 0x000b71b0 0x000b71b0 0x000cf850>;
            opp-microvolt-L5 = <0x000b40dc 0x000b40dc 0x000cf850 0x000b40dc 0x000b40dc 0x000cf850>;
        };
        opp-1000000000 {
            opp-hz = <0x00000000 0x3b9aca00>;
            opp-microvolt = <0x000cf850 0x000cf850 0x000cf850 0x000cf850 0x000cf850 0x000cf850>;
            opp-microvolt-L1 = <0x000cc77c 0x000cc77c 0x000cf850 0x000cc77c 0x000cc77c 0x000cf850>;
            opp-microvolt-L2 = <0x000c96a8 0x000c96a8 0x000cf850 0x000c96a8 0x000c96a8 0x000cf850>;
            opp-microvolt-L3 = <0x000c65d4 0x000c65d4 0x000cf850 0x000c65d4 0x000c65d4 0x000cf850>;
            opp-microvolt-L4 = <0x000c3500 0x000c3500 0x000cf850 0x000c3500 0x000c3500 0x000cf850>;
            opp-microvolt-L5 = <0x000c042c 0x000c042c 0x000cf850 0x000c042c 0x000c042c 0x000cf850>;
        };
    };
    usbdrd3_0 {
        compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
        clocks = <0x00000002 0x000001a3 0x00000002 0x000001a2 0x00000002 0x000001a1>;
        clock-names = "ref", "suspend", "bus";
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        status = "okay";
        usb@fc000000 {
            compatible = "snps,dwc3";
            reg = <0x00000000 0xfc000000 0x00000000 0x00400000>;
            interrupts = <0x00000000 0x000000dc 0x00000004>;
            power-domains = <0x00000047 0x0000001f>;
            resets = <0x00000002 0x000002a4>;
            reset-names = "usb3-otg";
            dr_mode = "otg";
            phys = <0x0000004c 0x0000004d>;
            phy-names = "usb2-phy", "usb3-phy";
            phy_type = "utmi_wide";
            snps,dis_enblslpm_quirk;
            snps,dis-u1-entry-quirk;
            snps,dis-u2-entry-quirk;
            snps,dis-u2-freeclk-exists-quirk;
            snps,dis-del-phy-power-chg-quirk;
            snps,dis-tx-ipgap-linecheck-quirk;
            quirk-skip-phy-init;
            status = "okay";
            usb-role-switch;
            port {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000004e>;
                    phandle = <0x0000011d>;
                };
            };
        };
    };
    usb@fc800000 {
        compatible = "generic-ehci";
        reg = <0x00000000 0xfc800000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x000000d7 0x00000004>;
        clocks = <0x00000002 0x0000019d 0x00000002 0x0000019e 0x0000004f>;
        clock-names = "usbhost", "arbiter", "utmi";
        phys = <0x00000050>;
        phy-names = "usb2-phy";
        power-domains = <0x00000047 0x0000001f>;
        status = "okay";
    };
    usb@fc840000 {
        compatible = "generic-ohci";
        reg = <0x00000000 0xfc840000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x000000d8 0x00000004>;
        clocks = <0x00000002 0x0000019d 0x00000002 0x0000019e 0x0000004f>;
        clock-names = "usbhost", "arbiter", "utmi";
        phys = <0x00000050>;
        phy-names = "usb2-phy";
        power-domains = <0x00000047 0x0000001f>;
        status = "okay";
    };
    usb@fc880000 {
        compatible = "generic-ehci";
        reg = <0x00000000 0xfc880000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x000000da 0x00000004>;
        clocks = <0x00000002 0x0000019f 0x00000002 0x000001a0 0x00000051>;
        clock-names = "usbhost", "arbiter", "utmi";
        phys = <0x00000052>;
        phy-names = "usb2-phy";
        power-domains = <0x00000047 0x0000001f>;
        status = "okay";
    };
    usb@fc8c0000 {
        compatible = "generic-ohci";
        reg = <0x00000000 0xfc8c0000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x000000db 0x00000004>;
        clocks = <0x00000002 0x0000019f 0x00000002 0x000001a0 0x00000051>;
        clock-names = "usbhost", "arbiter", "utmi";
        phys = <0x00000052>;
        phy-names = "usb2-phy";
        power-domains = <0x00000047 0x0000001f>;
        status = "okay";
    };
    iommu@fc900000 {
        compatible = "arm,smmu-v3";
        reg = <0x00000000 0xfc900000 0x00000000 0x00200000>;
        interrupts = <0x00000000 0x00000171 0x00000004 0x00000000 0x00000173 0x00000004 0x00000000 0x00000176 0x00000004 0x00000000 0x0000016f 0x00000004>;
        interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
        #iommu-cells = <0x00000001>;
        status = "disabled";
    };
    iommu@fcb00000 {
        compatible = "arm,smmu-v3";
        reg = <0x00000000 0xfcb00000 0x00000000 0x00200000>;
        interrupts = <0x00000000 0x0000017d 0x00000004 0x00000000 0x0000017f 0x00000004 0x00000000 0x00000182 0x00000004 0x00000000 0x0000017b 0x00000004>;
        interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
        #iommu-cells = <0x00000001>;
        status = "disabled";
    };
    usbhost3_0 {
        compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
        clocks = <0x00000002 0x00000179 0x00000002 0x00000178 0x00000002 0x00000177 0x00000002 0x0000017a 0x00000002 0x00000166 0x00000002 0x00000181>;
        clock-names = "ref", "suspend", "bus", "utmi", "php", "pipe";
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        status = "okay";
        usb@fcd00000 {
            compatible = "snps,dwc3";
            reg = <0x00000000 0xfcd00000 0x00000000 0x00400000>;
            interrupts = <0x00000000 0x000000de 0x00000004>;
            resets = <0x00000002 0x00000237>;
            reset-names = "usb3-host";
            dr_mode = "host";
            phys = <0x00000053 0x00000004>;
            phy-names = "usb3-phy";
            phy_type = "utmi_wide";
            snps,dis_enblslpm_quirk;
            snps,dis-u2-freeclk-exists-quirk;
            snps,dis-del-phy-power-chg-quirk;
            snps,dis-tx-ipgap-linecheck-quirk;
            snps,dis_rxdet_inp3_quirk;
            status = "okay";
        };
    };
    syscon@fd588000 {
        compatible = "rockchip,rk3588-pmu0-grf", "syscon", "simple-mfd";
        reg = <0x00000000 0xfd588000 0x00000000 0x00002000>;
        reboot-mode {
            compatible = "syscon-reboot-mode";
            offset = <0x00000080>;
            mode-bootloader = <0x5242c301>;
            mode-charge = <0x5242c30b>;
            mode-fastboot = <0x5242c309>;
            mode-loader = <0x5242c301>;
            mode-normal = <0x5242c300>;
            mode-recovery = <0x5242c303>;
            mode-ums = <0x5242c30c>;
            mode-panic = <0x5242c307>;
            mode-watchdog = <0x5242c308>;
        };
    };
    syscon@fd58a000 {
        compatible = "rockchip,rk3588-pmu1-grf", "syscon";
        reg = <0x00000000 0xfd58a000 0x00000000 0x00002000>;
        phandle = <0x000000e1>;
    };
    syscon@fd58c000 {
        compatible = "rockchip,rk3588-sys-grf", "syscon", "simple-mfd";
        reg = <0x00000000 0xfd58c000 0x00000000 0x00001000>;
        phandle = <0x000000ae>;
        rgb {
            compatible = "rockchip,rk3588-rgb";
            pinctrl-names = "default";
            pinctrl-0 = <0x00000054>;
            status = "disabled";
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    endpoint@2 {
                        reg = <0x00000002>;
                        remote-endpoint = <0x00000032>;
                        status = "disabled";
                        phandle = <0x000000cb>;
                    };
                };
            };
        };
    };
    syscon@fd590000 {
        compatible = "rockchip,rk3588-bigcore0-grf", "syscon";
        reg = <0x00000000 0xfd590000 0x00000000 0x00000100>;
        phandle = <0x00000023>;
    };
    syscon@fd592000 {
        compatible = "rockchip,rk3588-bigcore1-grf", "syscon";
        reg = <0x00000000 0xfd592000 0x00000000 0x00000100>;
        phandle = <0x00000024>;
    };
    syscon@fd594000 {
        compatible = "rockchip,rk3588-litcore-grf", "syscon";
        reg = <0x00000000 0xfd594000 0x00000000 0x00000100>;
        phandle = <0x00000022>;
    };
    syscon@fd598000 {
        compatible = "rockchip,rk3588-dsu-grf", "syscon";
        reg = <0x00000000 0xfd598000 0x00000000 0x00000100>;
    };
    syscon@fd5a0000 {
        compatible = "rockchip,rk3588-gpu-grf", "syscon";
        reg = <0x00000000 0xfd5a0000 0x00000000 0x00000100>;
        phandle = <0x0000004b>;
    };
    syscon@fd5a2000 {
        compatible = "rockchip,rk3588-npu-grf", "syscon";
        reg = <0x00000000 0xfd5a2000 0x00000000 0x00000100>;
        phandle = <0x00000094>;
    };
    syscon@fd5a4000 {
        compatible = "rockchip,rk3588-vop-grf", "syscon";
        reg = <0x00000000 0xfd5a4000 0x00000000 0x00002000>;
        phandle = <0x000000b2>;
    };
    syscon@fd5a6000 {
        compatible = "rockchip,rk3588-vo-grf", "syscon";
        reg = <0x00000000 0xfd5a6000 0x00000000 0x00002000>;
        clocks = <0x00000055>;
        phandle = <0x0000016b>;
    };
    syscon@fd5a8000 {
        compatible = "rockchip,rk3588-vo-grf", "syscon";
        reg = <0x00000000 0xfd5a8000 0x00000000 0x00000100>;
        clocks = <0x00000056>;
        phandle = <0x000000b3>;
    };
    syscon@fd5ac000 {
        compatible = "rockchip,rk3588-usb-grf", "syscon";
        reg = <0x00000000 0xfd5ac000 0x00000000 0x00004000>;
        phandle = <0x00000057>;
    };
    syscon@fd5b0000 {
        compatible = "rockchip,rk3588-php-grf", "syscon";
        reg = <0x00000000 0xfd5b0000 0x00000000 0x00001000>;
        phandle = <0x00000059>;
    };
    syscon@fd5b4000 {
        compatible = "rockchip,mipi-dphy-grf", "syscon";
        reg = <0x00000000 0xfd5b4000 0x00000000 0x00001000>;
        phandle = <0x00000170>;
    };
    syscon@fd5b5000 {
        compatible = "rockchip,mipi-dphy-grf", "syscon";
        reg = <0x00000000 0xfd5b5000 0x00000000 0x00001000>;
        phandle = <0x000001a3>;
    };
    syscon@fd5bc000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x00000000 0xfd5bc000 0x00000000 0x00000100>;
        phandle = <0x00000171>;
    };
    syscon@fd5c4000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x00000000 0xfd5c4000 0x00000000 0x00000100>;
        phandle = <0x00000172>;
    };
    syscon@fd5c8000 {
        compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
        reg = <0x00000000 0xfd5c8000 0x00000000 0x00004000>;
        phandle = <0x0000016a>;
    };
    syscon@fd5d0000 {
        compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
        reg = <0x00000000 0xfd5d0000 0x00000000 0x00004000>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        phandle = <0x00000169>;
        usb2-phy@0 {
            compatible = "rockchip,rk3588-usb2phy";
            reg = <0x00000000 0x00000010>;
            interrupts = <0x00000000 0x00000189 0x00000004>;
            resets = <0x00000002 0x000c0047 0x00000002 0x00000488>;
            reset-names = "phy", "apb";
            clocks = <0x00000002 0x000002b5>;
            clock-names = "phyclk";
            clock-output-names = "usb480m_phy0";
            #clock-cells = <0x00000000>;
            rockchip,usbctrl-grf = <0x00000057>;
            status = "okay";
            phandle = <0x0000011b>;
            otg-port {
                #phy-cells = <0x00000000>;
                status = "okay";
                dr_mode = "otg";
                phandle = <0x0000004c>;
            };
        };
    };
    syscon@fd5d8000 {
        compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
        reg = <0x00000000 0xfd5d8000 0x00000000 0x00004000>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        usb2-phy@8000 {
            compatible = "rockchip,rk3588-usb2phy";
            reg = <0x00008000 0x00000010>;
            interrupts = <0x00000000 0x00000187 0x00000004>;
            resets = <0x00000002 0x000c0049 0x00000002 0x0000048a>;
            reset-names = "phy", "apb";
            clocks = <0x00000002 0x000002b5>;
            clock-names = "phyclk";
            clock-output-names = "usb480m_phy2";
            #clock-cells = <0x00000000>;
            status = "okay";
            phandle = <0x0000004f>;
            host-port {
                #phy-cells = <0x00000000>;
                status = "okay";
                phy-supply = <0x00000058>;
                phandle = <0x00000050>;
            };
        };
    };
    syscon@fd5dc000 {
        compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
        reg = <0x00000000 0xfd5dc000 0x00000000 0x00004000>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        usb2-phy@c000 {
            compatible = "rockchip,rk3588-usb2phy";
            reg = <0x0000c000 0x00000010>;
            interrupts = <0x00000000 0x00000188 0x00000004>;
            resets = <0x00000002 0x000c004a 0x00000002 0x0000048b>;
            reset-names = "phy", "apb";
            clocks = <0x00000002 0x000002b5>;
            clock-names = "phyclk";
            clock-output-names = "usb480m_phy3";
            #clock-cells = <0x00000000>;
            status = "okay";
            phandle = <0x00000051>;
            host-port {
                #phy-cells = <0x00000000>;
                status = "okay";
                phy-supply = <0x00000058>;
                phandle = <0x00000052>;
            };
        };
    };
    syscon@fd5e0000 {
        compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
        reg = <0x00000000 0xfd5e0000 0x00000000 0x00000100>;
        phandle = <0x00000168>;
    };
    syscon@fd5e8000 {
        compatible = "rockchip,mipi-dcphy-grf", "syscon";
        reg = <0x00000000 0xfd5e8000 0x00000000 0x00004000>;
        phandle = <0x0000016e>;
    };
    syscon@fd5ec000 {
        compatible = "rockchip,mipi-dcphy-grf", "syscon";
        reg = <0x00000000 0xfd5ec000 0x00000000 0x00004000>;
        phandle = <0x0000016f>;
    };
    syscon@fd5f0000 {
        compatible = "rockchip,rk3588-ioc", "syscon";
        reg = <0x00000000 0xfd5f0000 0x00000000 0x00010000>;
        phandle = <0x00000173>;
    };
    sram@fd600000 {
        compatible = "mmio-sram";
        reg = <0x00000000 0xfd600000 0x00000000 0x00100000>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        ranges = <0x00000000 0x00000000 0xfd600000 0x00100000>;
        rkvdec-sram@0 {
            reg = <0x00000000 0x00080000>;
            phandle = <0x000000a5>;
        };
        rkvdec-sram@80000 {
            reg = <0x00080000 0x00080000>;
            phandle = <0x000000a7>;
        };
    };
    clock-controller@fd7c0000 {
        compatible = "rockchip,rk3588-cru";
        rockchip,grf = <0x00000059>;
        reg = <0x00000000 0xfd7c0000 0x00000000 0x0005c000>;
        #clock-cells = <0x00000001>;
        #reset-cells = <0x00000001>;
        assigned-clocks = <0x00000002 0x00000009 0x00000002 0x00000005 0x00000002 0x00000008 0x00000002 0x00000007 0x00000002 0x000000d8 0x00000002 0x000000da 0x00000002 0x000000d9 0x00000002 0x0000010e 0x00000002 0x0000010f 0x00000002 0x00000110 0x00000002 0x00000299 0x00000002 0x0000029a 0x00000002 0x00000270 0x00000002 0x0000007b 0x00000002 0x000000ec 0x00000002 0x00000114>;
        assigned-clock-rates = <0x05f5e100 0x2ed96880 0x32a9f880 0x46cf7100 0x29d7ab80 0x17d78400 0x1dcd6500 0x2faf0800 0x05f5e100 0x17d78400 0x05f5e100 0x0bebc200 0x2faf0800 0x165a0bc0 0x08f0d180 0x0bebc200>;
        phandle = <0x00000002>;
    };
    i2c@fd880000 {
        compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfd880000 0x00000000 0x00001000>;
        clocks = <0x00000002 0x00000287 0x00000002 0x00000286>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x0000013d 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000005a>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
    };
    serial@fd890000 {
        compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfd890000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000014b 0x00000004>;
        clocks = <0x00000002 0x000002ae 0x00000002 0x000002af>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000005b 0x00000006 0x0000005b 0x00000007>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000005c>;
        status = "disabled";
    };
    pwm@fd8b0000 {
        compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfd8b0000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x0000005d>;
        clocks = <0x00000002 0x000002a5 0x00000002 0x000002a4>;
        clock-names = "pwm", "pclk";
        status = "disabled";
    };
    pwm@fd8b0010 {
        compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfd8b0010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x0000005e>;
        clocks = <0x00000002 0x000002a5 0x00000002 0x000002a4>;
        clock-names = "pwm", "pclk";
        status = "disabled";
    };
    pwm@fd8b0020 {
        compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfd8b0020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x0000005f>;
        clocks = <0x00000002 0x000002a5 0x00000002 0x000002a4>;
        clock-names = "pwm", "pclk";
        status = "disabled";
    };
    pwm@fd8b0030 {
        compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfd8b0030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000158 0x00000004 0x00000000 0x00000159 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000060>;
        clocks = <0x00000002 0x000002a5 0x00000002 0x000002a4>;
        clock-names = "pwm", "pclk";
        status = "disabled";
    };
    power-management@fd8d8000 {
        compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
        reg = <0x00000000 0xfd8d8000 0x00000000 0x00000400>;
        phandle = <0x000000b4>;
        power-controller {
            compatible = "rockchip,rk3588-power-controller";
            #power-domain-cells = <0x00000001>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            status = "okay";
            phandle = <0x00000047>;
            power-domain@8 {
                reg = <0x00000008>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                power-domain@9 {
                    reg = <0x00000009>;
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    clocks = <0x00000002 0x0000012f 0x00000002 0x00000131 0x00000002 0x00000130 0x00000002 0x00000126>;
                    pm_qos = <0x00000061 0x00000062 0x00000063>;
                    power-domain@10 {
                        reg = <0x0000000a>;
                        clocks = <0x00000002 0x0000012f 0x00000002 0x00000131 0x00000002 0x00000130>;
                        pm_qos = <0x00000064>;
                    };
                    power-domain@11 {
                        reg = <0x0000000b>;
                        clocks = <0x00000002 0x0000012f 0x00000002 0x00000131 0x00000002 0x00000130>;
                        pm_qos = <0x00000065>;
                    };
                };
            };
            power-domain@12 {
                reg = <0x0000000c>;
                clocks = <0x00000002 0x00000114 0x00000002 0x00000115 0x00000002 0x00000116>;
                pm_qos = <0x00000066 0x00000067 0x00000068 0x00000069>;
            };
            power-domain@13 {
                reg = <0x0000000d>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                power-domain@14 {
                    reg = <0x0000000e>;
                    clocks = <0x00000002 0x0000018f 0x00000002 0x000001be 0x00000002 0x000001bc 0x00000002 0x00000190 0x00000002 0x0000018e>;
                    pm_qos = <0x0000006a>;
                };
                power-domain@15 {
                    reg = <0x0000000f>;
                    clocks = <0x00000002 0x00000194 0x00000002 0x000001be 0x00000002 0x000001bc 0x00000002 0x00000195>;
                    pm_qos = <0x0000006b>;
                };
                power-domain@16 {
                    reg = <0x00000010>;
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    clocks = <0x00000002 0x000001c4 0x00000002 0x000001c5>;
                    pm_qos = <0x0000006c 0x0000006d 0x0000006e>;
                    power-domain@17 {
                        reg = <0x00000011>;
                        clocks = <0x00000002 0x000001c9 0x00000002 0x000001c4 0x00000002 0x000001c5 0x00000002 0x000001ca>;
                        pm_qos = <0x0000006f 0x00000070 0x00000071>;
                    };
                };
            };
            power-domain@21 {
                reg = <0x00000015>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                clocks = <0x00000002 0x000001be 0x00000002 0x000001bd 0x00000002 0x000001bc 0x00000002 0x000001bf 0x00000002 0x000001aa 0x00000002 0x000001a9 0x00000002 0x000001ac 0x00000002 0x000001ad 0x00000002 0x000001ae 0x00000002 0x000001af 0x00000002 0x000001b0 0x00000002 0x000001b1 0x00000002 0x000001b2 0x00000002 0x000001b3 0x00000002 0x000001b4 0x00000002 0x000001b5 0x00000002 0x000001b7 0x00000002 0x000001b6>;
                pm_qos = <0x00000072 0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079>;
                power-domain@23 {
                    reg = <0x00000017>;
                    clocks = <0x00000002 0x0000004b 0x00000002 0x00000049 0x00000002 0x000001be>;
                    pm_qos = <0x0000007a>;
                };
                power-domain@14 {
                    reg = <0x0000000e>;
                    clocks = <0x00000002 0x0000018f 0x00000002 0x000001be 0x00000002 0x000001bc 0x00000002 0x00000190>;
                    pm_qos = <0x0000006a>;
                };
                power-domain@15 {
                    reg = <0x0000000f>;
                    clocks = <0x00000002 0x00000194 0x00000002 0x000001be 0x00000002 0x000001bc>;
                    pm_qos = <0x0000006b>;
                };
                power-domain@22 {
                    reg = <0x00000016>;
                    clocks = <0x00000002 0x000001ba 0x00000002 0x000001b9>;
                    pm_qos = <0x0000007b>;
                };
            };
            power-domain@24 {
                reg = <0x00000018>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                clocks = <0x00000002 0x0000026e 0x00000002 0x0000026d 0x00000002 0x00000270>;
                pm_qos = <0x0000007c 0x0000007d>;
                power-domain@25 {
                    reg = <0x00000019>;
                    clocks = <0x00000002 0x000001f6 0x00000002 0x000001f7 0x00000002 0x000001f5 0x00000002 0x000001f3 0x00000002 0x000001ee 0x00000002 0x000001ed 0x00000002 0x0000026d>;
                    pm_qos = <0x0000007e>;
                };
            };
            power-domain@26 {
                reg = <0x0000001a>;
                clocks = <0x00000002 0x0000022e 0x00000002 0x0000022f 0x00000002 0x0000022d 0x00000002 0x00000218 0x00000002 0x00000217 0x00000002 0x0000022b 0x00000002 0x00000264>;
                pm_qos = <0x0000007f 0x00000080>;
            };
            power-domain@27 {
                reg = <0x0000001b>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                clocks = <0x00000002 0x000001e1 0x00000002 0x000001e2 0x00000002 0x000001df 0x00000002 0x000001de 0x00000002 0x000001e5 0x00000002 0x000001e4>;
                pm_qos = <0x00000081 0x00000082 0x00000083 0x00000084>;
                power-domain@28 {
                    reg = <0x0000001c>;
                    clocks = <0x00000002 0x00000121 0x00000002 0x00000120 0x00000002 0x000001e1 0x00000002 0x000001e2>;
                    pm_qos = <0x00000085 0x00000086>;
                };
                power-domain@29 {
                    reg = <0x0000001d>;
                    clocks = <0x00000002 0x000001d6 0x00000002 0x000001d5 0x00000002 0x000001d9 0x00000002 0x000001d8 0x00000002 0x000001e2>;
                    pm_qos = <0x00000087 0x00000088>;
                };
            };
            power-domain@30 {
                reg = <0x0000001e>;
                clocks = <0x00000002 0x00000189 0x00000002 0x0000018a>;
                pm_qos = <0x00000089>;
            };
            power-domain@31 {
                reg = <0x0000001f>;
                clocks = <0x00000002 0x00000166 0x00000002 0x0000019b 0x00000002 0x0000019c 0x00000002 0x0000019d 0x00000002 0x0000019e 0x00000002 0x0000019f 0x00000002 0x000001a0>;
                pm_qos = <0x0000008a 0x0000008b 0x0000008c 0x0000008d>;
            };
            power-domain@33 {
                reg = <0x00000021>;
                clocks = <0x00000002 0x00000166 0x00000002 0x00000169 0x00000002 0x0000016a>;
            };
            power-domain@34 {
                reg = <0x00000022>;
                clocks = <0x00000002 0x00000166 0x00000002 0x00000169 0x00000002 0x0000016a>;
            };
            power-domain@37 {
                reg = <0x00000025>;
                clocks = <0x00000002 0x00000199 0x00000002 0x00000140>;
                pm_qos = <0x0000008e>;
            };
            power-domain@38 {
                reg = <0x00000026>;
                clocks = <0x00000002 0x0000003c 0x00000002 0x0000003d>;
            };
            power-domain@40 {
                reg = <0x00000028>;
                pm_qos = <0x0000008f>;
            };
        };
    };
    pvtm@fda40000 {
        compatible = "rockchip,rk3588-bigcore0-pvtm";
        reg = <0x00000000 0xfda40000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@0 {
            reg = <0x00000000>;
            clocks = <0x00000002 0x000002c6 0x00000002 0x00000015>;
            clock-names = "clk", "pclk";
        };
    };
    pvtm@fda50000 {
        compatible = "rockchip,rk3588-bigcore1-pvtm";
        reg = <0x00000000 0xfda50000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@1 {
            reg = <0x00000001>;
            clocks = <0x00000002 0x000002c8 0x00000002 0x00000017>;
            clock-names = "clk", "pclk";
        };
    };
    pvtm@fda60000 {
        compatible = "rockchip,rk3588-litcore-pvtm";
        reg = <0x00000000 0xfda60000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@2 {
            reg = <0x00000002>;
            clocks = <0x00000002 0x000002ca 0x00000002 0x0000001b>;
            clock-names = "clk", "pclk";
        };
    };
    pvtm@fdaf0000 {
        compatible = "rockchip,rk3588-npu-pvtm";
        reg = <0x00000000 0xfdaf0000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@3 {
            reg = <0x00000003>;
            clocks = <0x00000002 0x0000012b 0x00000002 0x00000129>;
            clock-names = "clk", "pclk";
            resets = <0x00000002 0x000001de 0x00000002 0x000001dc>;
            reset-names = "rts", "rst-p";
        };
    };
    pvtm@fdb30000 {
        compatible = "rockchip,rk3588-gpu-pvtm";
        reg = <0x00000000 0xfdb30000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@4 {
            reg = <0x00000004>;
            clocks = <0x00000002 0x00000118>;
            clock-names = "clk";
            resets = <0x00000002 0x00000430 0x00000002 0x0000042f>;
            reset-names = "rts", "rst-p";
        };
    };
    npu@fdab0000 {
        compatible = "rockchip,rk3588-rknpu";
        reg = <0x00000000 0xfdab0000 0x00000000 0x00010000 0x00000000 0xfdac0000 0x00000000 0x00010000 0x00000000 0xfdad0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x0000006e 0x00000004 0x00000000 0x0000006f 0x00000004 0x00000000 0x00000070 0x00000004>;
        interrupt-names = "npu0_irq", "npu1_irq", "npu2_irq";
        clocks = <0x0000000e 0x00000006 0x00000002 0x0000012d 0x00000002 0x00000122 0x00000002 0x00000124 0x00000002 0x0000012e 0x00000002 0x00000123 0x00000002 0x00000125 0x00000002 0x00000131>;
        clock-names = "clk_npu", "aclk0", "aclk1", "aclk2", "hclk0", "hclk1", "hclk2", "pclk";
        assigned-clocks = <0x0000000e 0x00000006>;
        assigned-clock-rates = <0x0bebc200>;
        resets = <0x00000002 0x000001e6 0x00000002 0x000001b0 0x00000002 0x000001c0 0x00000002 0x000001e8 0x00000002 0x000001b2 0x00000002 0x000001c2>;
        reset-names = "srst_a0", "srst_a1", "srst_a2", "srst_h0", "srst_h1", "srst_h2";
        power-domains = <0x00000047 0x00000009 0x00000047 0x0000000a 0x00000047 0x0000000b>;
        power-domain-names = "npu0", "npu1", "npu2";
        operating-points-v2 = <0x00000090>;
        iommus = <0x00000091>;
        status = "okay";
        rknpu-supply = <0x00000092>;
        mem-supply = <0x00000093>;
    };
    npu-opp-table {
        compatible = "operating-points-v2";
        rockchip,pvtm-voltage-sel = <0x00000000 0x00000348 0x00000000 0x00000349 0x00000361 0x00000001 0x00000362 0x0000037a 0x00000002 0x0000037b 0x00000393 0x00000003 0x00000394 0x0000270f 0x00000004>;
        rockchip,pvtm-pvtpll;
        rockchip,pvtm-offset = <0x00000050>;
        rockchip,pvtm-sample-time = <0x0000044c>;
        rockchip,pvtm-freq = <0x000c3500>;
        rockchip,pvtm-volt = <0x000b71b0>;
        rockchip,pvtm-ref-temp = <0x00000019>;
        rockchip,pvtm-temp-prop = <0xffffff8f 0xffffff8f>;
        rockchip,pvtm-thermal-zone = "npu-thermal";
        clocks = <0x00000002 0x0000012a>;
        clock-names = "pclk";
        rockchip,grf = <0x00000094>;
        volt-mem-read-margin = <0x000d0bd8 0x00000001 0x000bac48 0x00000002 0x000a4cb8 0x00000003 0x00078d98 0x00000004>;
        low-volt-read-margin = <0x00000004>;
        intermediate-threshold-freq = <0x0007a120>;
        rockchip,init-freq = <0x000f4240>;
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-min-volt = <0x000b1008>;
        phandle = <0x00000090>;
        opp-200000000 {
            opp-hz = <0x00000000 0x0bebc200>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
        };
        opp-300000000 {
            opp-hz = <0x00000000 0x11e1a300>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
        };
        opp-400000000 {
            opp-hz = <0x00000000 0x17d78400>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
        };
        opp-500000000 {
            opp-hz = <0x00000000 0x1dcd6500>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000a4cb8 0x000a4cb8 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
        };
        opp-700000000 {
            opp-hz = <0x00000000 0x29b92700>;
            opp-microvolt = <0x000aae60 0x000aae60 0x000cf850 0x000aae60 0x000aae60 0x000cf850>;
            opp-microvolt-L2 = <0x000a7d8c 0x000a7d8c 0x000cf850 0x000a7d8c 0x000a7d8c 0x000cf850>;
            opp-microvolt-L3 = <0x000a4cb8 0x000a4cb8 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
            opp-microvolt-L4 = <0x000a4cb8 0x000a4cb8 0x000cf850 0x000a4cb8 0x000a4cb8 0x000cf850>;
        };
        opp-800000000 {
            opp-hz = <0x00000000 0x2faf0800>;
            opp-microvolt = <0x000b71b0 0x000b71b0 0x000cf850 0x000b71b0 0x000b71b0 0x000cf850>;
            opp-microvolt-L1 = <0x000b40dc 0x000b40dc 0x000cf850 0x000b40dc 0x000b40dc 0x000cf850>;
            opp-microvolt-L2 = <0x000b1008 0x000b1008 0x000cf850 0x000b1008 0x000b1008 0x000cf850>;
            opp-microvolt-L3 = <0x000adf34 0x000adf34 0x000cf850 0x000adf34 0x000adf34 0x000cf850>;
            opp-microvolt-L4 = <0x000adf34 0x000adf34 0x000cf850 0x000adf34 0x000adf34 0x000cf850>;
        };
        opp-900000000 {
            opp-hz = <0x00000000 0x35a4e900>;
            opp-microvolt = <0x000c3500 0x000c3500 0x000cf850 0x000c3500 0x000c3500 0x000cf850>;
            opp-microvolt-L1 = <0x000c042c 0x000c042c 0x000cf850 0x000c042c 0x000c042c 0x000cf850>;
            opp-microvolt-L2 = <0x000bd358 0x000bd358 0x000cf850 0x000bd358 0x000bd358 0x000cf850>;
            opp-microvolt-L3 = <0x000ba284 0x000ba284 0x000cf850 0x000ba284 0x000ba284 0x000cf850>;
            opp-microvolt-L4 = <0x000b71b0 0x000b71b0 0x000cf850 0x000b71b0 0x000b71b0 0x000cf850>;
        };
        opp-1000000000 {
            opp-hz = <0x00000000 0x3b9aca00>;
            opp-microvolt = <0x000cf850 0x000cf850 0x000cf850 0x000cf850 0x000cf850 0x000cf850>;
            opp-microvolt-L1 = <0x000cc77c 0x000cc77c 0x000cf850 0x000cc77c 0x000cc77c 0x000cf850>;
            opp-microvolt-L2 = <0x000c96a8 0x000c96a8 0x000cf850 0x000c96a8 0x000c96a8 0x000cf850>;
            opp-microvolt-L3 = <0x000c65d4 0x000c65d4 0x000cf850 0x000c65d4 0x000c65d4 0x000cf850>;
            opp-microvolt-L4 = <0x000c3500 0x000c3500 0x000cf850 0x000c3500 0x000c3500 0x000cf850>;
        };
    };
    iommu@fdab9000 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdab9000 0x00000000 0x00000100 0x00000000 0xfdaba000 0x00000000 0x00000100 0x00000000 0xfdaca000 0x00000000 0x00000100 0x00000000 0xfdada000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000006e 0x00000004 0x00000000 0x0000006f 0x00000004 0x00000000 0x00000070 0x00000004>;
        interrupt-names = "npu0_mmu", "npu1_mmu", "npu2_mmu";
        clocks = <0x00000002 0x0000012d 0x00000002 0x00000122 0x00000002 0x00000124 0x00000002 0x0000012e 0x00000002 0x00000123 0x00000002 0x00000125>;
        clock-names = "aclk0", "aclk1", "aclk2", "iface0", "iface1", "iface2";
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000091>;
    };
    vdpu@fdb50400 {
        compatible = "rockchip,vpu-decoder-v2";
        reg = <0x00000000 0xfdb50400 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x00000077 0x00000004>;
        interrupt-names = "irq_vdpu";
        clocks = <0x00000002 0x000001c0 0x00000002 0x000001c1>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,normal-rates = <0x2367b880 0x00000000>;
        assigned-clocks = <0x00000002 0x000001c0>;
        assigned-clock-rates = <0x2367b880>;
        resets = <0x00000002 0x000002c8 0x00000002 0x000002c9>;
        reset-names = "shared_video_a", "shared_video_h";
        rockchip,skip-pmu-idle-request;
        iommus = <0x00000095>;
        rockchip,srv = <0x00000096>;
        rockchip,taskqueue-node = <0x00000000>;
        power-domains = <0x00000047 0x00000015>;
        status = "okay";
    };
    iommu@fdb50800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdb50800 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x00000076 0x00000004>;
        interrupt-names = "irq_vdpu_mmu";
        clocks = <0x00000002 0x000001c0 0x00000002 0x000001c1>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000047 0x00000015>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000095>;
    };
    avsd-plus@fdb51000 {
        compatible = "rockchip,avs-plus-decoder";
        reg = <0x00000000 0xfdb51000 0x00000000 0x00000200>;
        interrupts = <0x00000000 0x00000077 0x00000004>;
        interrupt-names = "irq_avsd";
        clocks = <0x00000002 0x000001c0 0x00000002 0x000001c1>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        resets = <0x00000002 0x000002c8 0x00000002 0x000002c9>;
        reset-names = "shared_video_a", "shared_video_h";
        iommus = <0x00000095>;
        power-domains = <0x00000047 0x00000015>;
        rockchip,srv = <0x00000096>;
        rockchip,taskqueue-node = <0x00000000>;
        status = "disabled";
    };
    rga@fdb60000 {
        compatible = "rockchip,rga3_core0";
        reg = <0x00000000 0xfdb60000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000072 0x00000004>;
        interrupt-names = "rga3_core0_irq";
        clocks = <0x00000002 0x000001ba 0x00000002 0x000001b9 0x00000002 0x000001bb>;
        clock-names = "aclk_rga3_0", "hclk_rga3_0", "clk_rga3_0";
        power-domains = <0x00000047 0x00000016>;
        iommus = <0x00000097>;
        status = "okay";
    };
    iommu@fdb60f00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdb60f00 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000072 0x00000004>;
        interrupt-names = "rga3_0_mmu";
        clocks = <0x00000002 0x000001ba 0x00000002 0x000001b9>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000047 0x00000016>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000097>;
    };
    rga@fdb70000 {
        compatible = "rockchip,rga3_core1";
        reg = <0x00000000 0xfdb70000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000073 0x00000004>;
        interrupt-names = "rga3_core1_irq";
        clocks = <0x00000002 0x0000018a 0x00000002 0x00000189 0x00000002 0x0000018b>;
        clock-names = "aclk_rga3_1", "hclk_rga3_1", "clk_rga3_1";
        power-domains = <0x00000047 0x0000001e>;
        iommus = <0x00000098>;
        status = "okay";
    };
    iommu@fdb70f00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdb70f00 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000073 0x00000004>;
        interrupt-names = "rga3_1_mmu";
        clocks = <0x00000002 0x0000018a 0x00000002 0x00000189>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000047 0x0000001e>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000098>;
    };
    rga@fdb80000 {
        compatible = "rockchip,rga2_core0";
        reg = <0x00000000 0xfdb80000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000074 0x00000004>;
        interrupt-names = "rga2_irq";
        clocks = <0x00000002 0x000001b7 0x00000002 0x000001b6 0x00000002 0x000001b8>;
        clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2";
        power-domains = <0x00000047 0x00000015>;
        status = "okay";
    };
    jpegd@fdb90000 {
        compatible = "rockchip,rkv-jpeg-decoder-v1";
        reg = <0x00000000 0xfdb90000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x00000081 0x00000004>;
        interrupt-names = "irq_jpegd";
        clocks = <0x00000002 0x000001b4 0x00000002 0x000001b5>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,normal-rates = <0x23c34600 0x00000000>;
        assigned-clocks = <0x00000002 0x000001b4>;
        assigned-clock-rates = <0x23c34600>;
        resets = <0x00000002 0x000002d2 0x00000002 0x000002d3>;
        reset-names = "video_a", "video_h";
        rockchip,skip-pmu-idle-request;
        iommus = <0x00000099>;
        rockchip,srv = <0x00000096>;
        rockchip,taskqueue-node = <0x00000001>;
        power-domains = <0x00000047 0x00000015>;
        status = "okay";
    };
    iommu@fdb90480 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdb90480 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x00000082 0x00000004>;
        interrupt-names = "irq_jpegd_mmu";
        clocks = <0x00000002 0x000001b4 0x00000002 0x000001b5>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000047 0x00000015>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000099>;
    };
    jpege-core@fdba0000 {
        compatible = "rockchip,vpu-encoder-v2-core";
        reg = <0x00000000 0xfdba0000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000007a 0x00000004>;
        interrupt-names = "irq_jpege0";
        clocks = <0x00000002 0x000001ac 0x00000002 0x000001ad>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,normal-rates = <0x2367b880 0x00000000>;
        assigned-clocks = <0x00000002 0x000001ac>;
        assigned-clock-rates = <0x2367b880>;
        resets = <0x00000002 0x000002ca 0x00000002 0x000002cb>;
        reset-names = "video_a", "video_h";
        rockchip,skip-pmu-idle-request;
        iommus = <0x0000009a>;
        rockchip,srv = <0x00000096>;
        rockchip,taskqueue-node = <0x00000002>;
        rockchip,ccu = <0x0000009b>;
        power-domains = <0x00000047 0x00000015>;
        status = "okay";
    };
    iommu@fdba0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdba0800 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x00000079 0x00000004>;
        interrupt-names = "irq_jpege0_mmu";
        clocks = <0x00000002 0x000001ac 0x00000002 0x000001ad>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000047 0x00000015>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x0000009a>;
    };
    jpege-core@fdba4000 {
        compatible = "rockchip,vpu-encoder-v2-core";
        reg = <0x00000000 0xfdba4000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000007c 0x00000004>;
        interrupt-names = "irq_jpege1";
        clocks = <0x00000002 0x000001ae 0x00000002 0x000001af>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,normal-rates = <0x2367b880 0x00000000>;
        assigned-clocks = <0x00000002 0x000001ae>;
        assigned-clock-rates = <0x2367b880>;
        resets = <0x00000002 0x000002cc 0x00000002 0x000002cd>;
        reset-names = "video_a", "video_h";
        rockchip,skip-pmu-idle-request;
        iommus = <0x0000009c>;
        rockchip,srv = <0x00000096>;
        rockchip,taskqueue-node = <0x00000003>;
        rockchip,ccu = <0x0000009b>;
        power-domains = <0x00000047 0x00000015>;
        status = "okay";
    };
    iommu@fdba4800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdba4800 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000007b 0x00000004>;
        interrupt-names = "irq_jpege1_mmu";
        clocks = <0x00000002 0x000001ae 0x00000002 0x000001af>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000047 0x00000015>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x0000009c>;
    };
    jpege-core@fdba8000 {
        compatible = "rockchip,vpu-encoder-v2-core";
        reg = <0x00000000 0xfdba8000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000007e 0x00000004>;
        interrupt-names = "irq_jpege2";
        clocks = <0x00000002 0x000001b0 0x00000002 0x000001b1>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,normal-rates = <0x2367b880 0x00000000>;
        assigned-clocks = <0x00000002 0x000001b0>;
        assigned-clock-rates = <0x2367b880>;
        resets = <0x00000002 0x000002ce 0x00000002 0x000002cf>;
        reset-names = "video_a", "video_h";
        rockchip,skip-pmu-idle-request;
        iommus = <0x0000009d>;
        rockchip,srv = <0x00000096>;
        rockchip,taskqueue-node = <0x00000004>;
        rockchip,ccu = <0x0000009b>;
        power-domains = <0x00000047 0x00000015>;
        status = "okay";
    };
    iommu@fdba8800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdba8800 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000007d 0x00000004>;
        interrupt-names = "irq_jpege2_mmu";
        clocks = <0x00000002 0x000001b0 0x00000002 0x000001b1>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000047 0x00000015>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x0000009d>;
    };
    jpege-core@fdbac000 {
        compatible = "rockchip,vpu-encoder-v2-core";
        reg = <0x00000000 0xfdbac000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x00000080 0x00000004>;
        interrupt-names = "irq_jpege3";
        clocks = <0x00000002 0x000001b2 0x00000002 0x000001b3>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,normal-rates = <0x2367b880 0x00000000>;
        assigned-clocks = <0x00000002 0x000001b2>;
        assigned-clock-rates = <0x2367b880>;
        resets = <0x00000002 0x000002d0 0x00000002 0x000002d1>;
        reset-names = "video_a", "video_h";
        rockchip,skip-pmu-idle-request;
        iommus = <0x0000009e>;
        rockchip,srv = <0x00000096>;
        rockchip,taskqueue-node = <0x00000005>;
        rockchip,ccu = <0x0000009b>;
        power-domains = <0x00000047 0x00000015>;
        status = "okay";
    };
    iommu@fdbac800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdbac800 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000007f 0x00000004>;
        interrupt-names = "irq_jpege3_mmu";
        clocks = <0x00000002 0x000001b2 0x00000002 0x000001b3>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000047 0x00000015>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x0000009e>;
    };
    iep@fdbb0000 {
        compatible = "rockchip,iep-v2";
        reg = <0x00000000 0xfdbb0000 0x00000000 0x00000500>;
        interrupts = <0x00000000 0x00000075 0x00000004>;
        interrupt-names = "irq_iep";
        clocks = <0x00000002 0x000001aa 0x00000002 0x000001a9 0x00000002 0x000001ab>;
        clock-names = "aclk", "hclk", "sclk";
        resets = <0x00000002 0x000002d5 0x00000002 0x000002d4 0x00000002 0x000002d6>;
        reset-names = "rst_a", "rst_h", "rst_s";
        rockchip,skip-pmu-idle-request;
        power-domains = <0x00000047 0x00000015>;
        rockchip,srv = <0x00000096>;
        rockchip,taskqueue-node = <0x00000006>;
        iommus = <0x0000009f>;
        status = "okay";
    };
    iommu@fdbb0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdbb0800 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000075 0x00000004>;
        interrupt-names = "irq_iep_mmu";
        clocks = <0x00000002 0x000001aa 0x00000002 0x000001a9>;
        clock-names = "aclk", "iface";
        #iommu-cells = <0x00000000>;
        power-domains = <0x00000047 0x00000015>;
        status = "okay";
        phandle = <0x0000009f>;
    };
    rkvenc-core@fdbd0000 {
        compatible = "rockchip,rkv-encoder-v2-core";
        reg = <0x00000000 0xfdbd0000 0x00000000 0x00006000>;
        interrupts = <0x00000000 0x00000065 0x00000004>;
        interrupt-names = "irq_rkvenc0";
        clocks = <0x00000002 0x000001c5 0x00000002 0x000001c4 0x00000002 0x000001c6>;
        clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
        rockchip,normal-rates = <0x23c34600 0x00000000 0x2faf0800>;
        assigned-clocks = <0x00000002 0x000001c5 0x00000002 0x000001c6>;
        assigned-clock-rates = <0x23c34600 0x2faf0800>;
        resets = <0x00000002 0x000002f5 0x00000002 0x000002f4 0x00000002 0x000002f6>;
        reset-names = "video_a", "video_h", "video_core";
        rockchip,skip-pmu-idle-request;
        iommus = <0x000000a0>;
        rockchip,srv = <0x00000096>;
        rockchip,ccu = <0x000000a1>;
        rockchip,taskqueue-node = <0x00000007>;
        rockchip,task-capacity = <0x00000008>;
        power-domains = <0x00000047 0x00000010>;
        status = "okay";
    };
    iommu@fdbdf000 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdbdf000 0x00000000 0x00000040 0x00000000 0xfdbdf040 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x00000063 0x00000004 0x00000000 0x00000064 0x00000004>;
        interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1";
        clocks = <0x00000002 0x000001c5 0x00000002 0x000001c4>;
        clock-names = "aclk", "iface";
        rockchip,disable-mmu-reset;
        rockchip,enable-cmd-retry;
        rockchip,shootdown-entire;
        #iommu-cells = <0x00000000>;
        power-domains = <0x00000047 0x00000010>;
        status = "okay";
        phandle = <0x000000a0>;
    };
    rkvenc-core@fdbe0000 {
        compatible = "rockchip,rkv-encoder-v2-core";
        reg = <0x00000000 0xfdbe0000 0x00000000 0x00006000>;
        interrupts = <0x00000000 0x00000068 0x00000004>;
        interrupt-names = "irq_rkvenc1";
        clocks = <0x00000002 0x000001ca 0x00000002 0x000001c9 0x00000002 0x000001cb>;
        clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
        rockchip,normal-rates = <0x23c34600 0x00000000 0x2faf0800>;
        assigned-clocks = <0x00000002 0x000001ca 0x00000002 0x000001cb>;
        assigned-clock-rates = <0x23c34600 0x2faf0800>;
        resets = <0x00000002 0x00000305 0x00000002 0x00000304 0x00000002 0x00000306>;
        reset-names = "video_a", "video_h", "video_core";
        rockchip,skip-pmu-idle-request;
        iommus = <0x000000a2>;
        rockchip,srv = <0x00000096>;
        rockchip,ccu = <0x000000a1>;
        rockchip,taskqueue-node = <0x00000007>;
        rockchip,task-capacity = <0x00000008>;
        power-domains = <0x00000047 0x00000011>;
        status = "okay";
    };
    iommu@fdbef000 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdbef000 0x00000000 0x00000040 0x00000000 0xfdbef040 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x00000066 0x00000004 0x00000000 0x00000067 0x00000004>;
        interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1";
        clocks = <0x00000002 0x000001ca 0x00000002 0x000001c9>;
        lock-names = "aclk", "iface";
        rockchip,disable-mmu-reset;
        rockchip,enable-cmd-retry;
        rockchip,shootdown-entire;
        #iommu-cells = <0x00000000>;
        power-domains = <0x00000047 0x00000011>;
        status = "okay";
        phandle = <0x000000a2>;
    };
    rkvdec-ccu@fdc30000 {
        compatible = "rockchip,rkv-decoder-v2-ccu";
        reg = <0x00000000 0xfdc30000 0x00000000 0x00000100>;
        reg-names = "ccu";
        clocks = <0x00000002 0x0000018e>;
        clock-names = "aclk_ccu";
        assigned-clocks = <0x00000002 0x0000018e>;
        assigned-clock-rates = <0x23c34600>;
        resets = <0x00000002 0x00000282>;
        reset-names = "video_ccu";
        rockchip,skip-pmu-idle-request;
        power-domains = <0x00000047 0x0000000e>;
        status = "okay";
        phandle = <0x000000a4>;
    };
    rkvdec-core@fdc38000 {
        compatible = "rockchip,rkv-decoder-v2";
        reg = <0x00000000 0xfdc38100 0x00000000 0x00000400 0x00000000 0xfdc38000 0x00000000 0x00000100>;
        reg-names = "regs", "link";
        interrupts = <0x00000000 0x0000005f 0x00000004>;
        interrupt-names = "irq_rkvdec0";
        clocks = <0x00000002 0x00000190 0x00000002 0x0000018f 0x00000002 0x00000193 0x00000002 0x00000191 0x00000002 0x00000192>;
        clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac", "clk_hevc_cabac";
        rockchip,normal-rates = <0x2faf0800 0x00000000 0x23c34600 0x23c34600 0x3b9aca00>;
        assigned-clocks = <0x00000002 0x00000190 0x00000002 0x00000193 0x00000002 0x00000191 0x00000002 0x00000192>;
        assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>;
        resets = <0x00000002 0x00000284 0x00000002 0x00000283 0x00000002 0x00000289 0x00000002 0x00000287 0x00000002 0x00000288>;
        reset-names = "video_a", "video_h", "video_core", "video_cabac", "video_hevc_cabac";
        rockchip,skip-pmu-idle-request;
        iommus = <0x000000a3>;
        rockchip,srv = <0x00000096>;
        rockchip,ccu = <0x000000a4>;
        rockchip,core-mask = <0x00010001>;
        rockchip,taskqueue-node = <0x00000009>;
        rockchip,sram = <0x000000a5>;
        rockchip,rcb-iova = <0x10000000 0x00100000>;
        rockchip,rcb-min-width = <0x00000200>;
        power-domains = <0x00000047 0x0000000e>;
        status = "okay";
    };
    iommu@fdc38700 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdc38700 0x00000000 0x00000040 0x00000000 0xfdc38740 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x00000060 0x00000004>;
        interrupt-names = "irq_rkvdec0_mmu";
        clocks = <0x00000002 0x00000190 0x00000002 0x0000018f>;
        clock-names = "aclk", "iface";
        rockchip,disable-mmu-reset;
        rockchip,enable-cmd-retry;
        rockchip,shootdown-entire;
        rockchip,master-handle-irq;
        #iommu-cells = <0x00000000>;
        power-domains = <0x00000047 0x0000000e>;
        status = "okay";
        phandle = <0x000000a3>;
    };
    rkvdec-core@fdc48000 {
        compatible = "rockchip,rkv-decoder-v2";
        reg = <0x00000000 0xfdc48100 0x00000000 0x00000400 0x00000000 0xfdc48000 0x00000000 0x00000100>;
        reg-names = "regs", "link";
        interrupts = <0x00000000 0x00000061 0x00000004>;
        interrupt-names = "irq_rkvdec1";
        clocks = <0x00000002 0x00000195 0x00000002 0x00000194 0x00000002 0x00000198 0x00000002 0x00000196 0x00000002 0x00000197>;
        clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac", "clk_hevc_cabac";
        rockchip,normal-rates = <0x2faf0800 0x00000000 0x23c34600 0x23c34600 0x3b9aca00>;
        assigned-clocks = <0x00000002 0x00000195 0x00000002 0x00000198 0x00000002 0x00000196 0x00000002 0x00000197>;
        assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>;
        resets = <0x00000002 0x00000293 0x00000002 0x00000292 0x00000002 0x00000298 0x00000002 0x00000296 0x00000002 0x00000297>;
        reset-names = "video_a", "video_h", "video_core", "video_cabac", "video_hevc_cabac";
        rockchip,skip-pmu-idle-request;
        iommus = <0x000000a6>;
        rockchip,srv = <0x00000096>;
        rockchip,ccu = <0x000000a4>;
        rockchip,core-mask = <0x00020002>;
        rockchip,taskqueue-node = <0x00000009>;
        rockchip,sram = <0x000000a7>;
        rockchip,rcb-iova = <0x10100000 0x00100000>;
        rockchip,rcb-min-width = <0x00000200>;
        power-domains = <0x00000047 0x0000000f>;
        status = "okay";
    };
    iommu@fdc48700 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdc48700 0x00000000 0x00000040 0x00000000 0xfdc48740 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x00000062 0x00000004>;
        interrupt-names = "irq_rkvdec1_mmu";
        clocks = <0x00000002 0x00000195 0x00000002 0x00000194>;
        clock-names = "aclk", "iface";
        rockchip,disable-mmu-reset;
        rockchip,enable-cmd-retry;
        rockchip,shootdown-entire;
        rockchip,master-handle-irq;
        #iommu-cells = <0x00000000>;
        power-domains = <0x00000047 0x0000000f>;
        status = "okay";
        phandle = <0x000000a6>;
    };
    av1d@fdc70000 {
        compatible = "rockchip,av1-decoder";
        reg = <0x00000000 0xfdc70000 0x00000000 0x00000800 0x00000000 0xfdc80000 0x00000000 0x00000400 0x00000000 0xfdc90000 0x00000000 0x00000400>;
        reg-names = "vcd", "cache", "afbc";
        interrupts = <0x00000000 0x0000006c 0x00000004 0x00000000 0x0000006b 0x00000004 0x00000000 0x0000006a 0x00000004>;
        interrupt-names = "irq_av1d", "irq_cache", "irq_afbc";
        clocks = <0x00000002 0x00000049 0x00000002 0x0000004b>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,normal-rates = <0x17d78400 0x17d78400>;
        assigned-clocks = <0x00000002 0x00000049 0x00000002 0x0000004b>;
        assigned-clock-rates = <0x17d78400 0x17d78400>;
        resets = <0x00000002 0x00000442 0x00000002 0x00000445>;
        reset-names = "video_a", "video_h";
        iommus = <0x000000a8>;
        rockchip,srv = <0x00000096>;
        rockchip,taskqueue-node = <0x0000000b>;
        power-domains = <0x00000047 0x00000017>;
        status = "disabled";
    };
    iommu@fdca0000 {
        compatible = "rockchip,iommu-av1";
        reg = <0x00000000 0xfdca0000 0x00000000 0x00000600>;
        interrupts = <0x00000000 0x0000006d 0x00000004>;
        interrupt-names = "irq_av1d_mmu";
        clocks = <0x00000002 0x00000049 0x00000002 0x0000004b>;
        clock-names = "aclk", "iface";
        #iommu-cells = <0x00000000>;
        power-domains = <0x00000047 0x00000017>;
        status = "disabled";
        phandle = <0x000000a8>;
    };
    rkisp-unite@fdcb0000 {
        compatible = "rockchip,rk3588-rkisp-unite";
        reg = <0x00000000 0xfdcb0000 0x00000000 0x00010000 0x00000000 0xfdcc0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000087 0x00000004 0x00000000 0x00000089 0x00000004 0x00000000 0x0000008a 0x00000004>;
        interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
        clocks = <0x00000002 0x000001de 0x00000002 0x000001df 0x00000002 0x000001db 0x00000002 0x000001dc 0x00000002 0x000001dd 0x00000002 0x00000120 0x00000002 0x00000121 0x00000002 0x0000011d 0x00000002 0x0000011e 0x00000002 0x0000011f>;
        clock-names = "aclk_isp0", "hclk_isp0", "clk_isp_core0", "clk_isp_core_marvin0", "clk_isp_core_vicap0", "aclk_isp1", "hclk_isp1", "clk_isp_core1", "clk_isp_core_marvin1", "clk_isp_core_vicap1";
        power-domains = <0x00000047 0x0000001c>;
        iommus = <0x000000a9>;
        status = "disabled";
    };
    rkisp@fdcb0000 {
        compatible = "rockchip,rk3588-rkisp";
        reg = <0x00000000 0xfdcb0000 0x00000000 0x00007f00>;
        interrupts = <0x00000000 0x00000083 0x00000004 0x00000000 0x00000085 0x00000004 0x00000000 0x00000086 0x00000004>;
        interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
        clocks = <0x00000002 0x000001de 0x00000002 0x000001df 0x00000002 0x000001db 0x00000002 0x000001dc 0x00000002 0x000001dd>;
        clock-names = "aclk_isp", "hclk_isp", "clk_isp_core", "clk_isp_core_marvin", "clk_isp_core_vicap";
        power-domains = <0x00000047 0x0000001b>;
        iommus = <0x000000aa>;
        status = "disabled";
        phandle = <0x00000040>;
    };
    rkisp-unite-mmu@fdcb7f00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdcb7f00 0x00000000 0x00000100 0x00000000 0xfdcc7f00 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000084 0x00000004 0x00000000 0x00000088 0x00000004>;
        interrupt-names = "isp0_mmu", "isp1_mmu";
        clocks = <0x00000002 0x000001de 0x00000002 0x000001df 0x00000002 0x00000120 0x00000002 0x00000121>;
        clock-names = "aclk0", "iface0", "aclk1", "iface1";
        power-domains = <0x00000047 0x0000001c>;
        #iommu-cells = <0x00000000>;
        rockchip,disable-mmu-reset;
        status = "disabled";
        phandle = <0x000000a9>;
    };
    iommu@fdcb7f00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdcb7f00 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000084 0x00000004>;
        interrupt-names = "isp0_mmu";
        clocks = <0x00000002 0x000001de 0x00000002 0x000001df>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000047 0x0000001b>;
        #iommu-cells = <0x00000000>;
        rockchip,disable-mmu-reset;
        status = "disabled";
        phandle = <0x000000aa>;
    };
    rkisp@fdcc0000 {
        compatible = "rockchip,rk3588-rkisp";
        reg = <0x00000000 0xfdcc0000 0x00000000 0x00007f00>;
        interrupts = <0x00000000 0x00000087 0x00000004 0x00000000 0x00000089 0x00000004 0x00000000 0x0000008a 0x00000004>;
        interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
        clocks = <0x00000002 0x00000120 0x00000002 0x00000121 0x00000002 0x0000011d 0x00000002 0x0000011e 0x00000002 0x0000011f>;
        clock-names = "aclk_isp", "hclk_isp", "clk_isp_core", "clk_isp_core_marvin", "clk_isp_core_vicap";
        power-domains = <0x00000047 0x0000001c>;
        iommus = <0x000000ab>;
        status = "disabled";
        phandle = <0x00000041>;
    };
    iommu@fdcc7f00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdcc7f00 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000088 0x00000004>;
        interrupt-names = "isp1_mmu";
        clocks = <0x00000002 0x00000120 0x00000002 0x00000121>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000047 0x0000001c>;
        #iommu-cells = <0x00000000>;
        rockchip,disable-mmu-reset;
        status = "disabled";
        phandle = <0x000000ab>;
    };
    rkispp@fdcd0000 {
        compatible = "rockchip,rk3588-rkispp";
        reg = <0x00000000 0xfdcd0000 0x00000000 0x00000f00>;
        interrupts = <0x00000000 0x0000008b 0x00000004>;
        interrupt-names = "fec_irq";
        clocks = <0x00000002 0x000001d5 0x00000002 0x000001d6 0x00000002 0x000001d7>;
        clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
        power-domains = <0x00000047 0x0000001d>;
        iommus = <0x000000ac>;
        status = "disabled";
        phandle = <0x00000042>;
    };
    iommu@fdcd0f00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdcd0f00 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000008c 0x00000004>;
        interrupt-names = "fec0_mmu";
        clocks = <0x00000002 0x000001d5 0x00000002 0x000001d6 0x00000002 0x000001d7>;
        clock-names = "aclk", "iface", "pclk";
        power-domains = <0x00000047 0x0000001d>;
        #iommu-cells = <0x00000000>;
        rockchip,disable-mmu-reset;
        status = "disabled";
        phandle = <0x000000ac>;
    };
    rkispp@fdcd8000 {
        compatible = "rockchip,rk3588-rkispp";
        reg = <0x00000000 0xfdcd8000 0x00000000 0x00000f00>;
        interrupts = <0x00000000 0x0000008d 0x00000004>;
        interrupt-names = "fec_irq";
        clocks = <0x00000002 0x000001d8 0x00000002 0x000001d9 0x00000002 0x000001da>;
        clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
        power-domains = <0x00000047 0x0000001d>;
        iommus = <0x000000ad>;
        status = "disabled";
        phandle = <0x00000043>;
    };
    iommu@fdcd8f00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdcd8f00 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000008e 0x00000004>;
        interrupt-names = "fec1_mmu";
        clocks = <0x00000002 0x000001d8 0x00000002 0x000001d9 0x00000002 0x000001da>;
        clock-names = "aclk", "iface", "pclk";
        power-domains = <0x00000047 0x0000001d>;
        #iommu-cells = <0x00000000>;
        rockchip,disable-mmu-reset;
        status = "disabled";
        phandle = <0x000000ad>;
    };
    rkcif@fdce0000 {
        compatible = "rockchip,rk3588-cif";
        reg = <0x00000000 0xfdce0000 0x00000000 0x00000800>;
        reg-names = "cif_regs";
        interrupts = <0x00000000 0x0000009b 0x00000004>;
        interrupt-names = "cif-intr";
        clocks = <0x00000002 0x000001e4 0x00000002 0x000001e5 0x00000002 0x000001e3>;
        clock-names = "aclk_cif", "hclk_cif", "dclk_cif";
        resets = <0x00000002 0x00000317 0x00000002 0x00000318 0x00000002 0x00000316>;
        reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d";
        assigned-clocks = <0x00000002 0x000001e3>;
        assigned-clock-rates = <0x23c34600>;
        power-domains = <0x00000047 0x0000001b>;
        rockchip,grf = <0x000000ae>;
        iommus = <0x0000003a>;
        status = "disabled";
        phandle = <0x00000039>;
    };
    iommu@fdce0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdce0800 0x00000000 0x00000100 0x00000000 0xfdce0900 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000071 0x00000004>;
        interrupt-names = "cif_mmu";
        clocks = <0x00000002 0x000001e4 0x00000002 0x000001e5>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000047 0x0000001b>;
        rockchip,disable-mmu-reset;
        #iommu-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x0000003a>;
    };
    mipi0-csi2@fdd10000 {
        compatible = "rockchip,rk3588-mipi-csi2";
        reg = <0x00000000 0xfdd10000 0x00000000 0x00010000>;
        reg-names = "csihost_regs";
        interrupts = <0x00000000 0x0000008f 0x00000004 0x00000000 0x00000090 0x00000004>;
        interrupt-names = "csi-intr1", "csi-intr2";
        clocks = <0x00000002 0x000001cf 0x00000002 0x000001cd>;
        clock-names = "pclk_csi2host", "iclk_csi2host";
        resets = <0x00000002 0x00000324 0x00000002 0x00000334>;
        reset-names = "srst_csihost_p", "srst_csihost_vicap";
        status = "disabled";
    };
    mipi1-csi2@fdd20000 {
        compatible = "rockchip,rk3588-mipi-csi2";
        reg = <0x00000000 0xfdd20000 0x00000000 0x00010000>;
        reg-names = "csihost_regs";
        interrupts = <0x00000000 0x00000091 0x00000004 0x00000000 0x00000092 0x00000004>;
        interrupt-names = "csi-intr1", "csi-intr2";
        clocks = <0x00000002 0x000001d0 0x00000002 0x000001ce>;
        clock-names = "pclk_csi2host", "iclk_csi2host";
        resets = <0x00000002 0x00000325 0x00000002 0x00000335>;
        reset-names = "srst_csihost_p", "srst_csihost_vicap";
        status = "disabled";
    };
    mipi2-csi2@fdd30000 {
        compatible = "rockchip,rk3588-mipi-csi2";
        reg = <0x00000000 0xfdd30000 0x00000000 0x00010000>;
        reg-names = "csihost_regs";
        interrupts = <0x00000000 0x00000093 0x00000004 0x00000000 0x00000094 0x00000004>;
        interrupt-names = "csi-intr1", "csi-intr2";
        clocks = <0x00000002 0x000001d1>;
        clock-names = "pclk_csi2host";
        resets = <0x00000002 0x00000326 0x00000002 0x00000336>;
        reset-names = "srst_csihost_p", "srst_csihost_vicap";
        status = "disabled";
    };
    mipi3-csi2@fdd40000 {
        compatible = "rockchip,rk3588-mipi-csi2";
        reg = <0x00000000 0xfdd40000 0x00000000 0x00010000>;
        reg-names = "csihost_regs";
        interrupts = <0x00000000 0x00000095 0x00000004 0x00000000 0x00000096 0x00000004>;
        interrupt-names = "csi-intr1", "csi-intr2";
        clocks = <0x00000002 0x000001d2>;
        clock-names = "pclk_csi2host";
        resets = <0x00000002 0x00000327 0x00000002 0x00000337>;
        reset-names = "srst_csihost_p", "srst_csihost_vicap";
        status = "disabled";
    };
    vop@fdd90000 {
        compatible = "rockchip,rk3588-vop";
        reg = <0x00000000 0xfdd90000 0x00000000 0x00004200 0x00000000 0xfdd95000 0x00000000 0x00001000>;
        reg-names = "regs", "gamma_lut";
        interrupts = <0x00000000 0x0000009c 0x00000004>;
        clocks = <0x00000002 0x00000270 0x00000002 0x0000026f 0x00000002 0x00000274 0x00000002 0x00000275 0x00000002 0x00000276 0x00000002 0x00000277 0x00000002 0x0000026e 0x00000002 0x00000271 0x00000002 0x00000272 0x00000002 0x00000273 0x000000af 0x000000b0>;
        clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3", "pclk_vop", "dclk_src_vp0", "dclk_src_vp1", "dclk_src_vp2", "hdmi0_phy_pll", "hdmi1_phy_pll";
        resets = <0x00000002 0x00000349 0x00000002 0x00000348 0x00000002 0x0000034d 0x00000002 0x00000350 0x00000002 0x00000351 0x00000002 0x00000352>;
        reset-names = "axi", "ahb", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3";
        iommus = <0x000000b1>;
        power-domains = <0x00000047 0x00000018>;
        rockchip,grf = <0x000000ae>;
        rockchip,vop-grf = <0x000000b2>;
        rockchip,vo1-grf = <0x000000b3>;
        rockchip,pmu = <0x000000b4>;
        status = "okay";
        disable-win-move;
        assigned-clocks = <0x00000002 0x00000271 0x00000002 0x00000272 0x00000002 0x00000273 0x00000002 0x00000277>;
        assigned-clock-parents = <0x00000000 0x00000000 0x00000002 0x00000004 0x00000000>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            phandle = <0x0000002b>;
            port@0 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000000>;
                cursor-win-id = <0x00000003>;
                rockchip,plane-mask = <0x0000000d>;
                rockchip,primary-plane = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x000000b5>;
                    phandle = <0x000000d5>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x000000b6>;
                    phandle = <0x000000de>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x000000b7>;
                    phandle = <0x00000031>;
                };
                endpoint@3 {
                    reg = <0x00000003>;
                    remote-endpoint = <0x000000b8>;
                    phandle = <0x00000184>;
                };
                endpoint@4 {
                    reg = <0x00000004>;
                    remote-endpoint = <0x000000b9>;
                    phandle = <0x0000018d>;
                };
                endpoint@5 {
                    reg = <0x00000005>;
                    remote-endpoint = <0x000000ba>;
                    phandle = <0x0000018a>;
                };
            };
            port@1 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000001>;
                cursor-win-id = <0x00000008>;
                rockchip,plane-mask = <0x00000142>;
                rockchip,primary-plane = <0x00000001>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x000000bb>;
                    phandle = <0x0000002d>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x000000bc>;
                    phandle = <0x000000df>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x000000bd>;
                    phandle = <0x000000db>;
                };
                endpoint@3 {
                    reg = <0x00000003>;
                    remote-endpoint = <0x000000be>;
                    phandle = <0x00000033>;
                };
                endpoint@4 {
                    reg = <0x00000004>;
                    remote-endpoint = <0x000000bf>;
                    phandle = <0x0000018e>;
                };
                endpoint@5 {
                    reg = <0x00000005>;
                    remote-endpoint = <0x000000c0>;
                    phandle = <0x00000034>;
                };
            };
            port@2 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000002>;
                assigned-clocks = <0x00000002 0x00000273>;
                assigned-clock-parents = <0x00000002 0x00000004>;
                cursor-win-id = <0x00000009>;
                rockchip,plane-mask = <0x00000280>;
                rockchip,primary-plane = <0x00000007>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x000000c1>;
                    phandle = <0x000000d6>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x000000c2>;
                    phandle = <0x00000030>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x000000c3>;
                    phandle = <0x000000dc>;
                };
                endpoint@3 {
                    reg = <0x00000003>;
                    remote-endpoint = <0x000000c4>;
                    phandle = <0x000000cf>;
                };
                endpoint@4 {
                    reg = <0x00000004>;
                    remote-endpoint = <0x000000c5>;
                    phandle = <0x000000d1>;
                };
                endpoint@5 {
                    reg = <0x00000005>;
                    remote-endpoint = <0x000000c6>;
                    phandle = <0x00000185>;
                };
                endpoint@6 {
                    reg = <0x00000006>;
                    remote-endpoint = <0x000000c7>;
                    phandle = <0x0000018f>;
                };
                endpoint@7 {
                    reg = <0x00000007>;
                    remote-endpoint = <0x000000c8>;
                    phandle = <0x0000018b>;
                };
            };
            port@3 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000003>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x000000c9>;
                    phandle = <0x0000002e>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x000000ca>;
                    phandle = <0x0000002f>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x000000cb>;
                    phandle = <0x00000032>;
                };
            };
        };
    };
    iommu@fdd97e00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdd97e00 0x00000000 0x00000100 0x00000000 0xfdd97f00 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000009c 0x00000004>;
        interrupt-names = "vop_mmu";
        clocks = <0x00000002 0x00000270 0x00000002 0x0000026f>;
        clock-names = "aclk", "iface";
        #iommu-cells = <0x00000000>;
        rockchip,disable-device-link-resume;
        rockchip,shootdown-entire;
        status = "okay";
        phandle = <0x000000b1>;
    };
    spdif-tx@fddb0000 {
        compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
        reg = <0x00000000 0xfddb0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000c3 0x00000004>;
        dmas = <0x000000cc 0x00000006>;
        dma-names = "tx";
        clock-names = "mclk", "hclk";
        clocks = <0x00000002 0x00000209 0x00000002 0x00000204>;
        assigned-clocks = <0x00000002 0x00000205>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        power-domains = <0x00000047 0x00000019>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    i2s@fddc0000 {
        compatible = "rockchip,rk3588-i2s-tdm";
        reg = <0x00000000 0xfddc0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000b8 0x00000004>;
        clocks = <0x00000002 0x000001fb 0x00000002 0x000001fb 0x00000002 0x000001f0>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        assigned-clocks = <0x00000002 0x000001f9>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        dmas = <0x000000cd 0x00000000>;
        dma-names = "tx";
        power-domains = <0x00000047 0x00000019>;
        resets = <0x00000002 0x0000038d>;
        reset-names = "tx-m";
        rockchip,playback-only;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    spdif-tx@fdde0000 {
        compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
        reg = <0x00000000 0xfdde0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000c4 0x00000004>;
        dmas = <0x000000cc 0x00000007>;
        dma-names = "tx";
        clock-names = "mclk", "hclk";
        clocks = <0x00000002 0x00000257 0x00000002 0x00000253>;
        assigned-clocks = <0x00000002 0x00000254>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        power-domains = <0x00000047 0x0000001a>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    i2s@fddf0000 {
        compatible = "rockchip,rk3588-i2s-tdm";
        reg = <0x00000000 0xfddf0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000b9 0x00000004>;
        clocks = <0x00000002 0x00000246 0x00000002 0x00000246 0x00000002 0x00000248>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        assigned-clocks = <0x00000002 0x00000243>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        dmas = <0x000000cd 0x00000002>;
        dma-names = "tx";
        power-domains = <0x00000047 0x0000001a>;
        resets = <0x00000002 0x000003e8>;
        reset-names = "tx-m";
        rockchip,playback-only;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    i2s@fddfc000 {
        compatible = "rockchip,rk3588-i2s-tdm";
        reg = <0x00000000 0xfddfc000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000bd 0x00000004>;
        clocks = <0x00000002 0x00000242 0x00000002 0x00000242 0x00000002 0x0000023e>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        assigned-clocks = <0x00000002 0x0000023f>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        dmas = <0x000000cd 0x00000017>;
        dma-names = "rx";
        power-domains = <0x00000047 0x0000001a>;
        resets = <0x00000002 0x00000413>;
        reset-names = "rx-m";
        rockchip,capture-only;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    spdif-rx@fde08000 {
        compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
        reg = <0x00000000 0xfde08000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000c7 0x00000004>;
        clocks = <0x00000002 0x0000025e 0x00000002 0x0000025d>;
        clock-names = "mclk", "hclk";
        assigned-clocks = <0x00000002 0x0000025e>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        dmas = <0x0000005b 0x00000015>;
        dma-names = "rx";
        power-domains = <0x00000047 0x0000001a>;
        resets = <0x00000002 0x000003fd>;
        reset-names = "spdifrx-m";
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    dsi@fde20000 {
        compatible = "rockchip,rk3588-mipi-dsi2";
        reg = <0x00000000 0xfde20000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x000000a7 0x00000004>;
        clocks = <0x00000002 0x00000278 0x00000002 0x0000027a>;
        clock-names = "pclk", "sys_clk";
        resets = <0x00000002 0x00000354>;
        reset-names = "apb";
        power-domains = <0x00000047 0x00000018>;
        phys = <0x000000ce>;
        phy-names = "dcphy";
        rockchip,grf = <0x000000b2>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x000000cf>;
                    status = "disabled";
                    phandle = <0x000000c4>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x0000002e>;
                    status = "disabled";
                    phandle = <0x000000c9>;
                };
            };
        };
    };
    dsi@fde30000 {
        compatible = "rockchip,rk3588-mipi-dsi2";
        reg = <0x00000000 0xfde30000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x000000a8 0x00000004>;
        clocks = <0x00000002 0x00000279 0x00000002 0x0000027b>;
        clock-names = "pclk", "sys_clk";
        resets = <0x00000002 0x00000355>;
        reset-names = "apb";
        power-domains = <0x00000047 0x00000018>;
        phys = <0x000000d0>;
        phy-names = "dcphy";
        rockchip,grf = <0x000000b2>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x000000d1>;
                    status = "disabled";
                    phandle = <0x000000c5>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x0000002f>;
                    status = "disabled";
                    phandle = <0x000000ca>;
                };
            };
        };
    };
    dp@fde50000 {
        compatible = "rockchip,rk3588-dp";
        reg = <0x00000000 0xfde50000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x000000a1 0x00000004>;
        clocks = <0x00000002 0x000001e6 0x00000002 0x000002cc 0x00000002 0x000001fb 0x00000002 0x00000207 0x00000004 0x00000002 0x000001ea>;
        clock-names = "apb", "aux", "i2s", "spdif", "hclk", "hdcp";
        assigned-clocks = <0x00000002 0x000002cc>;
        assigned-clock-rates = <0x00f42400>;
        resets = <0x00000002 0x00000388>;
        phys = <0x000000d2>;
        power-domains = <0x00000047 0x00000019>;
        #sound-dai-cells = <0x00000001>;
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <0x000000d3>;
        hpd-gpios = <0x000000d4 0x00000000 0x00000000>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x000000d5>;
                    status = "okay";
                    phandle = <0x000000b5>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x0000002d>;
                    status = "disabled";
                    phandle = <0x000000bb>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x000000d6>;
                    status = "disabled";
                    phandle = <0x000000c1>;
                };
            };
        };
    };
    hdmi@fde80000 {
        compatible = "rockchip,rk3588-dw-hdmi";
        reg = <0x00000000 0xfde80000 0x00000000 0x00020000>;
        interrupts = <0x00000000 0x000000a9 0x00000004 0x00000000 0x000000aa 0x00000004 0x00000000 0x000000ab 0x00000004 0x00000000 0x000000ac 0x00000004 0x00000000 0x00000168 0x00000004>;
        clocks = <0x00000002 0x00000221 0x00000002 0x00000265 0x00000002 0x00000222 0x00000002 0x00000223 0x00000002 0x00000246 0x00000002 0x00000274 0x00000002 0x00000275 0x00000002 0x00000276 0x00000002 0x00000277 0x00000005>;
        clock-names = "pclk", "hpd", "earc", "hdmitx_ref", "aud", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3", "hclk_vo1";
        resets = <0x00000002 0x000003d0 0x00000002 0x0000049c>;
        reset-names = "ref", "hdp";
        power-domains = <0x00000047 0x0000001a>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000d7 0x000000d8 0x000000d9 0x000000da>;
        reg-io-width = <0x00000004>;
        rockchip,grf = <0x000000ae>;
        rockchip,vo1_grf = <0x000000b3>;
        phys = <0x000000af>;
        phy-names = "hdmi";
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000031>;
                    status = "disabled";
                    phandle = <0x000000b7>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x000000db>;
                    status = "disabled";
                    phandle = <0x000000bd>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x000000dc>;
                    status = "disabled";
                    phandle = <0x000000c3>;
                };
            };
        };
    };
    edp@fdec0000 {
        compatible = "rockchip,rk3588-edp";
        reg = <0x00000000 0xfdec0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000a3 0x00000004>;
        clocks = <0x00000002 0x00000211 0x00000002 0x00000210 0x00000002 0x00000212 0x00000005>;
        clock-names = "dp", "pclk", "spdif", "hclk";
        resets = <0x00000002 0x000003e1 0x00000002 0x000003e0>;
        reset-names = "dp", "apb";
        phys = <0x000000dd>;
        phy-names = "dp";
        power-domains = <0x00000047 0x0000001a>;
        rockchip,grf = <0x000000b3>;
        status = "okay";
        force-hpd;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x000000de>;
                    status = "disabled";
                    phandle = <0x000000b6>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x000000df>;
                    status = "okay";
                    phandle = <0x000000bc>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x00000030>;
                    status = "disabled";
                    phandle = <0x000000c2>;
                };
            };
            port@1 {
                reg = <0x00000001>;
                endpoint {
                    remote-endpoint = <0x000000e0>;
                    phandle = <0x000001ae>;
                };
            };
        };
    };
    qos@fdf35000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf35000 0x00000000 0x00000020>;
        phandle = <0x00000066>;
    };
    qos@fdf35200 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf35200 0x00000000 0x00000020>;
        phandle = <0x00000067>;
    };
    qos@fdf35400 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf35400 0x00000000 0x00000020>;
        phandle = <0x00000068>;
    };
    qos@fdf35600 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf35600 0x00000000 0x00000020>;
        phandle = <0x00000069>;
    };
    qos@fdf36000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf36000 0x00000000 0x00000020>;
        phandle = <0x00000089>;
    };
    qos@fdf39000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf39000 0x00000000 0x00000020>;
        phandle = <0x0000008e>;
    };
    qos@fdf3d800 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf3d800 0x00000000 0x00000020>;
        phandle = <0x0000008f>;
    };
    qos@fdf3e000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf3e000 0x00000000 0x00000020>;
        phandle = <0x0000008b>;
    };
    qos@fdf3e200 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf3e200 0x00000000 0x00000020>;
        phandle = <0x0000008a>;
    };
    qos@fdf3e400 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf3e400 0x00000000 0x00000020>;
        phandle = <0x0000008c>;
    };
    qos@fdf3e600 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf3e600 0x00000000 0x00000020>;
        phandle = <0x0000008d>;
    };
    qos@fdf40000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf40000 0x00000000 0x00000020>;
        phandle = <0x00000087>;
    };
    qos@fdf40200 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf40200 0x00000000 0x00000020>;
        phandle = <0x00000088>;
    };
    qos@fdf40400 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf40400 0x00000000 0x00000020>;
        phandle = <0x00000081>;
    };
    qos@fdf40500 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf40500 0x00000000 0x00000020>;
        phandle = <0x00000082>;
    };
    qos@fdf40600 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf40600 0x00000000 0x00000020>;
        phandle = <0x00000083>;
    };
    qos@fdf40800 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf40800 0x00000000 0x00000020>;
        phandle = <0x00000084>;
    };
    qos@fdf41000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf41000 0x00000000 0x00000020>;
        phandle = <0x00000085>;
    };
    qos@fdf41100 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf41100 0x00000000 0x00000020>;
        phandle = <0x00000086>;
    };
    qos@fdf60000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf60000 0x00000000 0x00000020>;
        phandle = <0x0000006c>;
    };
    qos@fdf60200 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf60200 0x00000000 0x00000020>;
        phandle = <0x0000006d>;
    };
    qos@fdf60400 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf60400 0x00000000 0x00000020>;
        phandle = <0x0000006e>;
    };
    qos@fdf61000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf61000 0x00000000 0x00000020>;
        phandle = <0x0000006f>;
    };
    qos@fdf61200 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf61200 0x00000000 0x00000020>;
        phandle = <0x00000070>;
    };
    qos@fdf61400 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf61400 0x00000000 0x00000020>;
        phandle = <0x00000071>;
    };
    qos@fdf62000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf62000 0x00000000 0x00000020>;
        phandle = <0x0000006a>;
    };
    qos@fdf63000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf63000 0x00000000 0x00000020>;
        phandle = <0x0000006b>;
    };
    qos@fdf64000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf64000 0x00000000 0x00000020>;
        phandle = <0x0000007a>;
    };
    qos@fdf66000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf66000 0x00000000 0x00000020>;
        phandle = <0x00000072>;
    };
    qos@fdf66200 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf66200 0x00000000 0x00000020>;
        phandle = <0x00000073>;
    };
    qos@fdf66400 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf66400 0x00000000 0x00000020>;
        phandle = <0x00000074>;
    };
    qos@fdf66600 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf66600 0x00000000 0x00000020>;
        phandle = <0x00000075>;
    };
    qos@fdf66800 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf66800 0x00000000 0x00000020>;
        phandle = <0x00000076>;
    };
    qos@fdf66a00 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf66a00 0x00000000 0x00000020>;
        phandle = <0x00000077>;
    };
    qos@fdf66c00 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf66c00 0x00000000 0x00000020>;
        phandle = <0x00000078>;
    };
    qos@fdf66e00 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf66e00 0x00000000 0x00000020>;
        phandle = <0x00000079>;
    };
    qos@fdf67000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf67000 0x00000000 0x00000020>;
        phandle = <0x0000007b>;
    };
    qos@fdf67200 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf67200 0x00000000 0x00000020>;
    };
    qos@fdf70000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf70000 0x00000000 0x00000020>;
        phandle = <0x00000064>;
    };
    qos@fdf71000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf71000 0x00000000 0x00000020>;
        phandle = <0x00000065>;
    };
    qos@fdf72000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf72000 0x00000000 0x00000020>;
        phandle = <0x00000061>;
    };
    qos@fdf72200 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf72200 0x00000000 0x00000020>;
        phandle = <0x00000062>;
    };
    qos@fdf72400 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf72400 0x00000000 0x00000020>;
        phandle = <0x00000063>;
    };
    qos@fdf80000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf80000 0x00000000 0x00000020>;
        phandle = <0x0000007e>;
    };
    qos@fdf81000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf81000 0x00000000 0x00000020>;
        phandle = <0x0000007f>;
    };
    qos@fdf81200 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf81200 0x00000000 0x00000020>;
        phandle = <0x00000080>;
    };
    qos@fdf82000 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf82000 0x00000000 0x00000020>;
        phandle = <0x0000007c>;
    };
    qos@fdf82200 {
        compatible = "syscon";
        reg = <0x00000000 0xfdf82200 0x00000000 0x00000020>;
        phandle = <0x0000007d>;
    };
    dfi@fe060000 {
        reg = <0x00000000 0xfe060000 0x00000000 0x00010000>;
        compatible = "rockchip,rk3588-dfi";
        rockchip,pmu_grf = <0x000000e1>;
        status = "okay";
        phandle = <0x00000035>;
    };
    pcie@fe180000 {
        compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
        #address-cells = <0x00000003>;
        #size-cells = <0x00000002>;
        bus-range = <0x00000030 0x0000003f>;
        clocks = <0x00000002 0x00000151 0x00000002 0x00000156 0x00000002 0x0000014c 0x00000002 0x0000015c 0x00000002 0x00000161 0x00000002 0x000002c5>;
        clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux", "pipe";
        device_type = "pci";
        interrupts = <0x00000000 0x000000f8 0x00000004 0x00000000 0x000000f7 0x00000004 0x00000000 0x000000f6 0x00000004 0x00000000 0x000000f5 0x00000004 0x00000000 0x000000f4 0x00000004>;
        interrupt-names = "sys", "pmc", "msg", "legacy", "err";
        #interrupt-cells = <0x00000001>;
        interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
        interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x000000e2 0x00000000 0x00000000 0x00000000 0x00000000 0x00000002 0x000000e2 0x00000001 0x00000000 0x00000000 0x00000000 0x00000003 0x000000e2 0x00000002 0x00000000 0x00000000 0x00000000 0x00000004 0x000000e2 0x00000003>;
        linux,pci-domain = <0x00000003>;
        num-ib-windows = <0x00000008>;
        num-ob-windows = <0x00000008>;
        num-viewport = <0x00000004>;
        max-link-speed = <0x00000002>;
        msi-map = <0x00003000 0x000000e3 0x00003000 0x00001000>;
        num-lanes = <0x00000001>;
        phys = <0x00000053 0x00000002>;
        phy-names = "pcie-phy";
        ranges = <0x00000800 0x00000000 0xf3000000 0x00000000 0xf3000000 0x00000000 0x00100000 0x81000000 0x00000000 0xf3100000 0x00000000 0xf3100000 0x00000000 0x00100000 0x82000000 0x00000000 0xf3200000 0x00000000 0xf3200000 0x00000000 0x00e00000 0xc3000000 0x00000009 0xc0000000 0x00000009 0xc0000000 0x00000000 0x40000000>;
        reg = <0x00000000 0xfe180000 0x00000000 0x00010000 0x0000000a 0x40c00000 0x00000000 0x00400000>;
        reg-names = "pcie-apb", "pcie-dbi";
        resets = <0x00000002 0x00000210 0x00000002 0x0000021f>;
        reset-names = "pcie", "periph";
        rockchip,pipe-grf = <0x00000059>;
        status = "disabled";
        legacy-interrupt-controller {
            interrupt-controller;
            #address-cells = <0x00000000>;
            #interrupt-cells = <0x00000001>;
            interrupt-parent = <0x00000001>;
            interrupts = <0x00000000 0x000000f5 0x00000001>;
            phandle = <0x000000e2>;
        };
    };
    pcie@fe190000 {
        compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
        #address-cells = <0x00000003>;
        #size-cells = <0x00000002>;
        bus-range = <0x00000040 0x0000004f>;
        clocks = <0x00000002 0x00000152 0x00000002 0x00000157 0x00000002 0x0000014d 0x00000002 0x0000015d 0x00000002 0x00000162 0x00000002 0x00000182>;
        clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux", "pipe";
        device_type = "pci";
        interrupts = <0x00000000 0x000000fd 0x00000004 0x00000000 0x000000fc 0x00000004 0x00000000 0x000000fb 0x00000004 0x00000000 0x000000fa 0x00000004 0x00000000 0x000000f9 0x00000004>;
        interrupt-names = "sys", "pmc", "msg", "legacy", "err";
        #interrupt-cells = <0x00000001>;
        interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
        interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x000000e4 0x00000000 0x00000000 0x00000000 0x00000000 0x00000002 0x000000e4 0x00000001 0x00000000 0x00000000 0x00000000 0x00000003 0x000000e4 0x00000002 0x00000000 0x00000000 0x00000000 0x00000004 0x000000e4 0x00000003>;
        linux,pci-domain = <0x00000004>;
        num-ib-windows = <0x00000008>;
        num-ob-windows = <0x00000008>;
        num-viewport = <0x00000004>;
        max-link-speed = <0x00000002>;
        msi-map = <0x00004000 0x000000e3 0x00004000 0x00001000>;
        num-lanes = <0x00000001>;
        phys = <0x000000e5 0x00000002>;
        phy-names = "pcie-phy";
        ranges = <0x00000800 0x00000000 0xf4000000 0x00000000 0xf4000000 0x00000000 0x00100000 0x81000000 0x00000000 0xf4100000 0x00000000 0xf4100000 0x00000000 0x00100000 0x82000000 0x00000000 0xf4200000 0x00000000 0xf4200000 0x00000000 0x00e00000 0xc3000000 0x0000000a 0x00000000 0x0000000a 0x00000000 0x00000000 0x40000000>;
        reg = <0x00000000 0xfe190000 0x00000000 0x00010000 0x0000000a 0x41000000 0x00000000 0x00400000>;
        reg-names = "pcie-apb", "pcie-dbi";
        resets = <0x00000002 0x00000211 0x00000002 0x00000220>;
        reset-names = "pcie", "periph";
        rockchip,pipe-grf = <0x00000059>;
        status = "disabled";
        legacy-interrupt-controller {
            interrupt-controller;
            #address-cells = <0x00000000>;
            #interrupt-cells = <0x00000001>;
            interrupt-parent = <0x00000001>;
            interrupts = <0x00000000 0x000000fa 0x00000001>;
            phandle = <0x000000e4>;
        };
    };
    ethernet@fe1c0000 {
        compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
        reg = <0x00000000 0xfe1c0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x000000ea 0x00000004 0x00000000 0x000000e9 0x00000004>;
        interrupt-names = "macirq", "eth_wake_irq";
        rockchip,grf = <0x000000ae>;
        rockchip,php_grf = <0x00000059>;
        clocks = <0x00000002 0x00000144 0x00000002 0x00000145 0x00000002 0x00000168 0x00000002 0x0000016d 0x00000002 0x00000143>;
        clock-names = "stmmaceth", "clk_mac_ref", "pclk_mac", "aclk_mac", "ptp_ref";
        resets = <0x00000002 0x0000020b>;
        reset-names = "stmmaceth";
        power-domains = <0x00000047 0x00000021>;
        snps,mixed-burst;
        snps,tso;
        snps,axi-config = <0x000000e6>;
        snps,mtl-rx-config = <0x000000e7>;
        snps,mtl-tx-config = <0x000000e8>;
        status = "disabled";
        mdio {
            compatible = "snps,dwmac-mdio";
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
        };
        stmmac-axi-config {
            snps,wr_osr_lmt = <0x00000004>;
            snps,rd_osr_lmt = <0x00000008>;
            snps,blen = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000010 0x00000008 0x00000004>;
            phandle = <0x000000e6>;
        };
        rx-queues-config {
            snps,rx-queues-to-use = <0x00000002>;
            phandle = <0x000000e7>;
            queue0 {
            };
            queue1 {
            };
        };
        tx-queues-config {
            snps,tx-queues-to-use = <0x00000002>;
            phandle = <0x000000e8>;
            queue0 {
            };
            queue1 {
            };
        };
    };
    sata@fe210000 {
        compatible = "rockchip,rk-ahci", "snps,dwc-ahci";
        reg = <0x00000000 0xfe210000 0x00000000 0x00001000>;
        clocks = <0x00000002 0x00000171 0x00000002 0x0000016e 0x00000002 0x00000174 0x00000002 0x00000163 0x00000002 0x0000017e>;
        clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
        interrupts = <0x00000000 0x00000111 0x00000004>;
        interrupt-names = "hostc";
        phys = <0x000000e5 0x00000001>;
        phy-names = "sata-phy";
        ports-implemented = <0x00000001>;
        status = "disabled";
    };
    sata@fe230000 {
        compatible = "rockchip,rk-ahci", "snps,dwc-ahci";
        reg = <0x00000000 0xfe230000 0x00000000 0x00001000>;
        clocks = <0x00000002 0x00000173 0x00000002 0x00000170 0x00000002 0x00000176 0x00000002 0x00000165 0x00000002 0x00000180>;
        clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
        interrupts = <0x00000000 0x00000113 0x00000004>;
        interrupt-names = "hostc";
        phys = <0x00000053 0x00000001>;
        phy-names = "sata-phy";
        ports-implemented = <0x00000001>;
        status = "disabled";
    };
    spi@fe2b0000 {
        compatible = "rockchip,sfc";
        reg = <0x00000000 0xfe2b0000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x000000ce 0x00000004>;
        clocks = <0x00000002 0x0000013d 0x00000002 0x0000013e>;
        clock-names = "clk_sfc", "hclk_sfc";
        assigned-clocks = <0x00000002 0x0000013d>;
        assigned-clock-rates = <0x05f5e100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
    };
    mmc@fe2c0000 {
        compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x00000000 0xfe2c0000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x000000cb 0x00000004>;
        clocks = <0x0000000e 0x00000017 0x0000000e 0x00000009 0x00000002 0x000002c2 0x00000002 0x000002c3>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x00000100>;
        max-frequency = <0x08f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000e9 0x000000ea 0x000000eb 0x000000ec>;
        power-domains = <0x00000047 0x00000028>;
        status = "okay";
        no-sdio;
        no-mmc;
        bus-width = <0x00000004>;
        cap-mmc-highspeed;
        cap-sd-highspeed;
        disable-wp;
        sd-uhs-sdr104;
        vmmc-supply = <0x000000ed>;
        vqmmc-supply = <0x000000ee>;
    };
    mmc@fe2d0000 {
        compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x00000000 0xfe2d0000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x000000cc 0x00000004>;
        clocks = <0x00000002 0x00000199 0x00000002 0x0000019a 0x00000002 0x000002c0 0x00000002 0x000002c1>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x00000100>;
        max-frequency = <0x0bebc200>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ef>;
        power-domains = <0x00000047 0x00000025>;
        status = "disabled";
    };
    mmc@fe2e0000 {
        compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci";
        reg = <0x00000000 0xfe2e0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x000000cd 0x00000004>;
        assigned-clocks = <0x00000002 0x0000013b 0x00000002 0x0000013c 0x00000002 0x0000013a>;
        assigned-clock-rates = <0x0bebc200 0x016e3600 0x0bebc200>;
        clocks = <0x00000002 0x0000013a 0x00000002 0x00000138 0x00000002 0x00000139 0x00000002 0x0000013b 0x00000002 0x0000013c>;
        clock-names = "core", "bus", "axi", "block", "timer";
        resets = <0x00000002 0x000001f6 0x00000002 0x000001f4 0x00000002 0x000001f5 0x00000002 0x000001f7 0x00000002 0x000001f8>;
        reset-names = "core", "bus", "axi", "block", "timer";
        max-frequency = <0x0bebc200>;
        status = "okay";
        bus-width = <0x00000008>;
        no-sdio;
        no-sd;
        non-removable;
    };
    crypto@fe370000 {
        compatible = "rockchip,rk3588-crypto";
        reg = <0x00000000 0xfe370000 0x00000000 0x00002000>;
        interrupts = <0x00000000 0x000000d1 0x00000004>;
        clocks = <0x0000000e 0x0000000b 0x0000000e 0x0000000c 0x0000000e 0x00000014 0x0000000e 0x00000015>;
        clock-names = "aclk", "hclk", "sclk", "pka";
        resets = <0x000000f0 0x0000000f>;
        reset-names = "crypto-rst";
        status = "disabled";
    };
    rng@fe378000 {
        compatible = "rockchip,trngv1";
        reg = <0x00000000 0xfe378000 0x00000000 0x00000200>;
        interrupts = <0x00000000 0x00000190 0x00000004>;
        clocks = <0x0000000e 0x0000000c>;
        clock-names = "hclk_trng";
        resets = <0x000000f0 0x00000030>;
        reset-names = "reset";
        status = "okay";
    };
    i2s@fe470000 {
        compatible = "rockchip,rk3588-i2s-tdm";
        reg = <0x00000000 0xfe470000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000b4 0x00000004>;
        clocks = <0x00000002 0x00000033 0x00000002 0x00000037 0x00000002 0x00000030>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        assigned-clocks = <0x00000002 0x00000031 0x00000002 0x00000035>;
        assigned-clock-parents = <0x00000002 0x00000005 0x00000002 0x00000005>;
        dmas = <0x0000005b 0x00000000 0x0000005b 0x00000001>;
        dma-names = "tx", "rx";
        power-domains = <0x00000047 0x00000026>;
        resets = <0x00000002 0x00000077 0x00000002 0x0000007a>;
        reset-names = "tx-m", "rx-m";
        rockchip,clk-trcm = <0x00000001>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f1 0x000000f2 0x000000f3 0x000000f4>;
        #sound-dai-cells = <0x00000000>;
        status = "okay";
        phandle = <0x000001aa>;
    };
    i2s@fe480000 {
        compatible = "rockchip,rk3588-i2s-tdm";
        reg = <0x00000000 0xfe480000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000b5 0x00000004>;
        clocks = <0x00000002 0x0000028c 0x00000002 0x00000290 0x00000002 0x00000288>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x0000005b 0x00000002 0x0000005b 0x00000003>;
        dma-names = "tx", "rx";
        resets = <0x00000002 0x000c002a 0x00000002 0x000c002d>;
        reset-names = "tx-m", "rx-m";
        rockchip,clk-trcm = <0x00000001>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f5 0x000000f6 0x000000f7 0x000000f8 0x000000f9 0x000000fa 0x000000fb 0x000000fc 0x000000fd 0x000000fe>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    i2s@fe490000 {
        compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
        reg = <0x00000000 0xfe490000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000b6 0x00000004>;
        clocks = <0x00000002 0x00000027 0x00000002 0x00000022>;
        clock-names = "i2s_clk", "i2s_hclk";
        assigned-clocks = <0x00000002 0x00000024>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        dmas = <0x000000cc 0x00000000 0x000000cc 0x00000001>;
        dma-names = "tx", "rx";
        power-domains = <0x00000047 0x00000026>;
        rockchip,clk-trcm = <0x00000001>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ff 0x00000100 0x00000101 0x00000102>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    i2s@fe4a0000 {
        compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
        reg = <0x00000000 0xfe4a0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000b7 0x00000004>;
        clocks = <0x00000002 0x0000002d 0x00000002 0x00000023>;
        clock-names = "i2s_clk", "i2s_hclk";
        assigned-clocks = <0x00000002 0x0000002a>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        dmas = <0x000000cc 0x00000002 0x000000cc 0x00000003>;
        dma-names = "tx", "rx";
        power-domains = <0x00000047 0x00000026>;
        rockchip,clk-trcm = <0x00000001>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000103 0x00000104 0x00000105 0x00000106>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    pdm@fe4b0000 {
        compatible = "rockchip,rk3588-pdm";
        reg = <0x00000000 0xfe4b0000 0x00000000 0x00001000>;
        clocks = <0x00000002 0x0000029f 0x00000002 0x0000029e>;
        clock-names = "pdm_clk", "pdm_hclk";
        dmas = <0x0000005b 0x00000004>;
        dma-names = "rx";
        pinctrl-names = "default";
        pinctrl-0 = <0x00000107 0x00000108 0x00000109 0x0000010a 0x0000010b 0x0000010c>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    pdm@fe4c0000 {
        compatible = "rockchip,rk3588-pdm";
        reg = <0x00000000 0xfe4c0000 0x00000000 0x00001000>;
        clocks = <0x00000002 0x0000003b 0x00000002 0x0000003a>;
        clock-names = "pdm_clk", "pdm_hclk";
        assigned-clocks = <0x00000002 0x0000003b>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        dmas = <0x000000cc 0x00000004>;
        dma-names = "rx";
        power-domains = <0x00000047 0x00000026>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000010d 0x0000010e 0x0000010f 0x00000110 0x00000111 0x00000112>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    vad@fe4d0000 {
        compatible = "rockchip,rk3588-vad";
        reg = <0x00000000 0xfe4d0000 0x00000000 0x00001000>;
        reg-names = "vad";
        clocks = <0x00000002 0x000002a0>;
        clock-names = "hclk";
        interrupts = <0x00000000 0x000000ca 0x00000004>;
        rockchip,audio-src = <0x00000000>;
        rockchip,det-channel = <0x00000000>;
        rockchip,mode = <0x00000000>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    spdif-tx@fe4e0000 {
        compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
        reg = <0x00000000 0xfe4e0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000c1 0x00000004>;
        dmas = <0x0000005b 0x00000005>;
        dma-names = "tx";
        clock-names = "mclk", "hclk";
        clocks = <0x00000002 0x00000041 0x00000002 0x0000003e>;
        assigned-clocks = <0x00000002 0x0000003f>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        power-domains = <0x00000047 0x00000026>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000113>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    spdif-tx@fe4f0000 {
        compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
        reg = <0x00000000 0xfe4f0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000c2 0x00000004>;
        dmas = <0x000000cc 0x00000005>;
        dma-names = "tx";
        clock-names = "mclk", "hclk";
        clocks = <0x00000002 0x00000047 0x00000002 0x00000044>;
        assigned-clocks = <0x00000002 0x00000045>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        power-domains = <0x00000047 0x00000026>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000114>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    codec-digital@fe500000 {
        compatible = "rockchip,rk3588-codec-digital", "rockchip,codec-digital-v1";
        reg = <0x00000000 0xfe500000 0x00000000 0x00001000>;
        clocks = <0x00000002 0x00000029 0x00000002 0x0000002f>;
        clock-names = "dac", "pclk";
        power-domains = <0x00000047 0x00000026>;
        resets = <0x00000002 0x00000084>;
        reset-names = "reset";
        rockchip,grf = <0x000000ae>;
        rockchip,pwm-output-mode;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000115>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    hwspinlock@fe5a0000 {
        compatible = "rockchip,hwspinlock";
        reg = <0x00000000 0xfe5a0000 0x00000000 0x00000100>;
        #hwlock-cells = <0x00000001>;
    };
    interrupt-controller@fe600000 {
        compatible = "arm,gic-v3";
        #interrupt-cells = <0x00000003>;
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        interrupt-controller;
        reg = <0x00000000 0xfe600000 0x00000000 0x00010000 0x00000000 0xfe680000 0x00000000 0x00100000>;
        interrupts = <0x00000001 0x00000009 0x00000004>;
        phandle = <0x00000001>;
        msi-controller@fe640000 {
            compatible = "arm,gic-v3-its";
            msi-controller;
            #msi-cells = <0x00000001>;
            reg = <0x00000000 0xfe640000 0x00000000 0x00020000>;
            phandle = <0x000000e3>;
        };
        msi-controller@fe660000 {
            compatible = "arm,gic-v3-its";
            msi-controller;
            #msi-cells = <0x00000001>;
            reg = <0x00000000 0xfe660000 0x00000000 0x00020000>;
            phandle = <0x00000195>;
        };
    };
    dma-controller@fea10000 {
        compatible = "arm,pl330", "arm,primecell";
        reg = <0x00000000 0xfea10000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000056 0x00000004 0x00000000 0x00000057 0x00000004>;
        clocks = <0x00000002 0x00000078>;
        clock-names = "apb_pclk";
        #dma-cells = <0x00000001>;
        arm,pl330-periph-burst;
        phandle = <0x0000005b>;
    };
    dma-controller@fea30000 {
        compatible = "arm,pl330", "arm,primecell";
        reg = <0x00000000 0xfea30000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000058 0x00000004 0x00000000 0x00000059 0x00000004>;
        clocks = <0x00000002 0x00000079>;
        clock-names = "apb_pclk";
        #dma-cells = <0x00000001>;
        arm,pl330-periph-burst;
        phandle = <0x000000cc>;
    };
    can@fea50000 {
        compatible = "rockchip,can-2.0";
        reg = <0x00000000 0xfea50000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000155 0x00000004>;
        clocks = <0x00000002 0x00000070 0x00000002 0x0000006f>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x00000002 0x000000b9 0x00000002 0x000000b8>;
        reset-names = "can", "can-apb";
        pinctrl-names = "default";
        pinctrl-0 = <0x00000116>;
        tx-fifo-depth = <0x00000001>;
        rx-fifo-depth = <0x00000006>;
        status = "disabled";
    };
    can@fea60000 {
        compatible = "rockchip,can-2.0";
        reg = <0x00000000 0xfea60000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000156 0x00000004>;
        clocks = <0x00000002 0x00000072 0x00000002 0x00000071>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x00000002 0x000000bb 0x00000002 0x000000ba>;
        reset-names = "can", "can-apb";
        pinctrl-names = "default";
        pinctrl-0 = <0x00000117>;
        tx-fifo-depth = <0x00000001>;
        rx-fifo-depth = <0x00000006>;
        status = "disabled";
    };
    can@fea70000 {
        compatible = "rockchip,can-2.0";
        reg = <0x00000000 0xfea70000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000157 0x00000004>;
        clocks = <0x00000002 0x00000074 0x00000002 0x00000073>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x00000002 0x000000bd 0x00000002 0x000000bc>;
        reset-names = "can", "can-apb";
        pinctrl-names = "default";
        pinctrl-0 = <0x00000118>;
        tx-fifo-depth = <0x00000001>;
        rx-fifo-depth = <0x00000006>;
        status = "disabled";
    };
    decompress@fea80000 {
        compatible = "rockchip,hw-decompress";
        reg = <0x00000000 0xfea80000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000055 0x00000004>;
        clocks = <0x00000002 0x00000075 0x00000002 0x00000077 0x00000002 0x00000076>;
        clock-names = "aclk", "dclk", "pclk";
        resets = <0x00000002 0x00000118>;
        reset-names = "dresetn";
        status = "disabled";
    };
    i2c@fea90000 {
        compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfea90000 0x00000000 0x00001000>;
        clocks = <0x00000002 0x0000008d 0x00000002 0x00000085>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x0000013e 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000119>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        anx7411@2c {
            status = "okay";
            compatible = "analogix,anx7411";
            reg = <0x0000002c>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            interrupt-parent = <0x0000011a>;
            interrupts = <0x00000009 0x00000008>;
            extcon = <0x0000011b>;
            pinctrl-names = "default";
            pinctrl-0 = <0x0000011c>;
            phandle = <0x00000123>;
            port {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000011d>;
                    phandle = <0x0000004e>;
                };
            };
            connector@0 {
                compatible = "usb-c-connector";
                reg = <0x00000000>;
                power-role = "dual";
                data-role = "dual";
                try-power-role = "sink";
                altmodes {
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    altmode@0 {
                        reg = <0x00000000>;
                        svid = <0x0000ff01>;
                        vdo = <0xffffffff>;
                    };
                };
                ports {
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    port@0 {
                        reg = <0x00000000>;
                        endpoint {
                            remote-endpoint = <0x0000011e>;
                            phandle = <0x0000016c>;
                        };
                    };
                    port@1 {
                        reg = <0x00000001>;
                        endpoint {
                            remote-endpoint = <0x0000011f>;
                            phandle = <0x0000016d>;
                        };
                    };
                };
            };
        };
    };
    i2c@feaa0000 {
        compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfeaa0000 0x00000000 0x00001000>;
        clocks = <0x00000002 0x0000008e 0x00000002 0x00000086>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x0000013f 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000120>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        hym8563@51 {
            compatible = "haoyu,hym8563";
            reg = <0x00000051>;
            #clock-cells = <0x00000000>;
            clock-frequency = <0x00008000>;
            clock-output-names = "hym8563";
            pinctrl-names = "default";
            pinctrl-0 = <0x00000121>;
            interrupt-parent = <0x00000122>;
            interrupts = <0x0000001c 0x00000008>;
        };
        sc8886@6b {
            compatible = "southchip,sc8886";
            reg = <0x0000006b>;
            ti,usb-charger-detection = <0x00000123 0x00000124>;
            interrupt-parent = <0x00000122>;
            interrupts = <0x00000014 0x00000008>;
            pinctrl-names = "default";
            pinctrl-0 = <0x00000125>;
            extcon = <0x0000011b 0x00000126>;
            ti,charge-current = <0x002625a0>;
            ti,max-input-voltage = <0x01312d00>;
            ti,max-input-current = <0x005b8d80>;
            ti,max-charge-voltage = <0x01005900>;
            ti,input-current = <0x0007a120>;
            ti,input-current-sdp = <0x0007a120>;
            ti,input-current-dcp = <0x001e8480>;
            ti,input-current-cdp = <0x001e8480>;
            ti,minimum-sys-voltage = <0x0070ea40>;
            ti,otg-voltage = <0x004c4b40>;
            ti,otg-current = <0x0007a120>;
            pd-charge-only = <0x00000000>;
            status = "okay";
        };
        sbs@b {
            status = "okay";
            compatible = "sbs,sbs-battery";
            reg = <0x0000000b>;
            sbs,poll-retry-count = <0x00000064>;
            sbs,i2c-retry-count = <0x00000064>;
        };
    };
    i2c@feab0000 {
        compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfeab0000 0x00000000 0x00001000>;
        clocks = <0x00000002 0x0000008f 0x00000002 0x00000087>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000140 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000127>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        es8326@18 {
            status = "okay";
            compatible = "everest,es8326";
            reg = <0x00000018>;
            #sound-dai-cells = <0x00000000>;
            clocks = <0x00000002 0x00000039>;
            clock-names = "mclk";
            assigned-clocks = <0x00000002 0x00000039>;
            assigned-clock-rates = <0x00bb8000>;
            pinctrl-names = "default";
            pinctrl-0 = <0x00000128 0x00000129 0x0000012a>;
            interrupt-parent = <0x000000d4>;
            interrupts = <0x0000001d 0x00000001>;
            mclk-rate = <0x00bb8000>;
            mic1-src = [22];
            mic2-src = [44];
            jack-pol = [0e];
            spk-con-gpio = <0x000000d4 0x0000001b 0x00000001>;
            phandle = <0x000001ab>;
        };
    };
    i2c@feac0000 {
        compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfeac0000 0x00000000 0x00001000>;
        clocks = <0x00000002 0x00000090 0x00000002 0x00000088>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000141 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012b>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        clock-frequency = <0x00061a80>;
        touchpad@2c {
            compatible = "hid-over-i2c";
            reg = <0x0000002c>;
            hid-descr-addr = <0x00000020>;
            interrupt-parent = <0x000000d4>;
            interrupts = <0x0000000a 0x00000008>;
            pinctrl-names = "default";
            pinctrl-0 = <0x0000012c>;
            status = "okay";
        };
    };
    i2c@fead0000 {
        compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfead0000 0x00000000 0x00001000>;
        clocks = <0x00000002 0x00000091 0x00000002 0x00000089>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000142 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012d>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
    };
    timer@feae0000 {
        compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
        reg = <0x00000000 0xfeae0000 0x00000000 0x00000020>;
        interrupts = <0x00000000 0x00000121 0x00000004>;
        clocks = <0x00000002 0x0000005c 0x00000002 0x0000005f>;
        clock-names = "pclk", "timer";
    };
    watchdog@feaf0000 {
        compatible = "snps,dw-wdt";
        reg = <0x00000000 0xfeaf0000 0x00000000 0x00000100>;
        clocks = <0x00000002 0x0000006c 0x00000002 0x0000006b>;
        clock-names = "tclk", "pclk";
        interrupts = <0x00000000 0x0000013b 0x00000004>;
        status = "disabled";
    };
    spi@feb00000 {
        compatible = "rockchip,rk3066-spi";
        reg = <0x00000000 0xfeb00000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000146 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x00000002 0x000000a3 0x00000002 0x0000009e>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000005b 0x0000000e 0x0000005b 0x0000000f>;
        dma-names = "tx", "rx";
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012e 0x0000012f 0x00000130>;
        num-cs = <0x00000002>;
        status = "disabled";
    };
    spi@feb10000 {
        compatible = "rockchip,rk3066-spi";
        reg = <0x00000000 0xfeb10000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000147 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x00000002 0x000000a4 0x00000002 0x0000009f>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000005b 0x00000010 0x0000005b 0x00000011>;
        dma-names = "tx", "rx";
        pinctrl-names = "default";
        pinctrl-0 = <0x00000131 0x00000132 0x00000133>;
        num-cs = <0x00000002>;
        status = "disabled";
    };
    spi@feb20000 {
        compatible = "rockchip,rk3066-spi";
        reg = <0x00000000 0xfeb20000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000148 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x00000002 0x000000a5 0x00000002 0x000000a0>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x000000cc 0x0000000f 0x000000cc 0x00000010>;
        dma-names = "tx", "rx";
        pinctrl-names = "default";
        pinctrl-0 = <0x00000134 0x00000135 0x00000136>;
        num-cs = <0x00000002>;
        status = "okay";
        assigned-clocks = <0x00000002 0x000000a5>;
        assigned-clock-rates = <0x0bebc200>;
        rk806master@0 {
            compatible = "rockchip,rk806";
            spi-max-frequency = <0x000f4240>;
            reg = <0x00000000>;
            interrupt-parent = <0x00000122>;
            interrupts = <0x00000007 0x00000008>;
            pinctrl-names = "default", "pmic-power-off";
            pinctrl-0 = <0x00000137 0x00000138 0x00000139 0x0000013a>;
            pinctrl-1 = <0x0000013b>;
            low_voltage_threshold = <0x00000bb8>;
            shutdown_voltage_threshold = <0x00000a8c>;
            shutdown_temperture_threshold = <0x000000a0>;
            hotdie_temperture_threshold = <0x00000073>;
            pmic-reset-func = <0x00000001>;
            vcc1-supply = <0x0000013c>;
            vcc2-supply = <0x0000013c>;
            vcc3-supply = <0x0000013c>;
            vcc4-supply = <0x0000013c>;
            vcc5-supply = <0x0000013c>;
            vcc6-supply = <0x0000013c>;
            vcc7-supply = <0x0000013c>;
            vcc8-supply = <0x0000013c>;
            vcc9-supply = <0x0000013c>;
            vcc10-supply = <0x0000013c>;
            vcc11-supply = <0x0000013d>;
            vcc12-supply = <0x0000013c>;
            vcc13-supply = <0x0000013c>;
            vcc14-supply = <0x0000013e>;
            vcca-supply = <0x0000013c>;
            pwrkey {
                status = "okay";
            };
            pinctrl_rk806 {
                gpio-controller;
                #gpio-cells = <0x00000002>;
                rk806_dvs1_null {
                    pins = "gpio_pwrctrl2";
                    function = "pin_fun0";
                    phandle = <0x00000138>;
                };
                rk806_dvs1_slp {
                    pins = "gpio_pwrctrl1";
                    function = "pin_fun1";
                };
                rk806_dvs1_pwrdn {
                    pins = "gpio_pwrctrl1";
                    function = "pin_fun2";
                    phandle = <0x0000013b>;
                };
                rk806_dvs1_rst {
                    pins = "gpio_pwrctrl1";
                    function = "pin_fun3";
                };
                rk806_dvs2_null {
                    pins = "gpio_pwrctrl2";
                    function = "pin_fun0";
                    phandle = <0x00000139>;
                };
                rk806_dvs2_slp {
                    pins = "gpio_pwrctrl2";
                    function = "pin_fun1";
                };
                rk806_dvs2_pwrdn {
                    pins = "gpio_pwrctrl2";
                    function = "pin_fun2";
                };
                rk806_dvs2_rst {
                    pins = "gpio_pwrctrl2";
                    function = "pin_fun3";
                };
                rk806_dvs2_dvs {
                    pins = "gpio_pwrctrl2";
                    function = "pin_fun4";
                };
                rk806_dvs2_gpio {
                    pins = "gpio_pwrctrl2";
                    function = "pin_fun5";
                };
                rk806_dvs3_null {
                    pins = "gpio_pwrctrl3";
                    function = "pin_fun0";
                    phandle = <0x0000013a>;
                };
                rk806_dvs3_slp {
                    pins = "gpio_pwrctrl3";
                    function = "pin_fun1";
                };
                rk806_dvs3_pwrdn {
                    pins = "gpio_pwrctrl3";
                    function = "pin_fun2";
                };
                rk806_dvs3_rst {
                    pins = "gpio_pwrctrl3";
                    function = "pin_fun3";
                };
                rk806_dvs3_dvs {
                    pins = "gpio_pwrctrl3";
                    function = "pin_fun4";
                };
                rk806_dvs3_gpio {
                    pins = "gpio_pwrctrl3";
                    function = "pin_fun5";
                };
            };
            regulators {
                DCDC_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00086470>;
                    regulator-max-microvolt = <0x000e7ef0>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_gpu_s0";
                    phandle = <0x00000049>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00086470>;
                    regulator-max-microvolt = <0x000e7ef0>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_npu_s0";
                    phandle = <0x00000092>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000b71b0>;
                    regulator-max-microvolt = <0x000b71b0>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_log_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                        regulator-suspend-microvolt = <0x000b71b0>;
                    };
                };
                DCDC_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00086470>;
                    regulator-max-microvolt = <0x000e7ef0>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_vdenc_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000a4cb8>;
                    regulator-max-microvolt = <0x000e7ef0>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_gpu_mem_s0";
                    phandle = <0x0000004a>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG6 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000a4cb8>;
                    regulator-max-microvolt = <0x000e7ef0>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_npu_mem_s0";
                    phandle = <0x00000093>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG7 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001e8480>;
                    regulator-max-microvolt = <0x001e8480>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_2v0_pldo_s3";
                    phandle = <0x0000013d>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x001e8480>;
                    };
                };
                DCDC_REG8 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000a4cb8>;
                    regulator-max-microvolt = <0x000e7ef0>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_vdenc_mem_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG9 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-name = "vdd2_ddr_s3";
                    regulator-state-mem {
                        regulator-on-in-suspend;
                    };
                };
                DCDC_REG10 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x0010c8e0>;
                    regulator-max-microvolt = <0x0010c8e0>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vcc_1v1_nldo_s3";
                    phandle = <0x0000013e>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x0010c8e0>;
                    };
                };
                PLDO_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "avcc_1v8_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                PLDO_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd1_1v8_ddr_s3";
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x001b7740>;
                    };
                };
                PLDO_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "avcc_1v8_codec_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                PLDO_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00325aa0>;
                    regulator-max-microvolt = <0x00325aa0>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vcc_3v3_s3";
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x00325aa0>;
                    };
                };
                PLDO_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x00325aa0>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vccio_sd_s0";
                    phandle = <0x000000ee>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                PLDO_REG6 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vccio_1v8_s3";
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x001b7740>;
                    };
                };
                NLDO_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000b71b0>;
                    regulator-max-microvolt = <0x000b71b0>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_0v75_s3";
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x000b71b0>;
                    };
                };
                NLDO_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000dbba0>;
                    regulator-max-microvolt = <0x000dbba0>;
                    regulator-name = "vdd2l_0v9_ddr_s3";
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x000dbba0>;
                    };
                };
                NLDO_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000b71b0>;
                    regulator-max-microvolt = <0x000b71b0>;
                    regulator-name = "vdd_0v75_hdmi_edp_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                NLDO_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000b71b0>;
                    regulator-max-microvolt = <0x000b71b0>;
                    regulator-name = "avdd_0v75_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                NLDO_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000cf850>;
                    regulator-max-microvolt = <0x000cf850>;
                    regulator-name = "vdd_0v85_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
            };
        };
        rk806slave@1 {
            compatible = "rockchip,rk806";
            spi-max-frequency = <0x000f4240>;
            reg = <0x00000001>;
            interrupt-parent = <0x00000122>;
            interrupts = <0x00000007 0x00000008>;
            pinctrl-names = "default";
            pinctrl-0 = <0x0000013f 0x00000140 0x00000141>;
            pmic-reset-func = <0x00000001>;
            vcc1-supply = <0x0000013c>;
            vcc2-supply = <0x0000013c>;
            vcc3-supply = <0x0000013c>;
            vcc4-supply = <0x0000013c>;
            vcc5-supply = <0x0000013c>;
            vcc6-supply = <0x0000013c>;
            vcc7-supply = <0x0000013c>;
            vcc8-supply = <0x0000013c>;
            vcc9-supply = <0x0000013c>;
            vcc10-supply = <0x0000013c>;
            vcc11-supply = <0x0000013d>;
            vcc12-supply = <0x0000013c>;
            vcc13-supply = <0x0000013e>;
            vcc14-supply = <0x0000013d>;
            vcca-supply = <0x0000013c>;
            pwrkey {
                status = "disabled";
            };
            pinctrl_slave_rk806 {
                gpio-controller;
                #gpio-cells = <0x00000002>;
                rk806_slave_dvs1_null {
                    pins = "gpio_pwrctrl2";
                    function = "pin_fun0";
                    phandle = <0x0000013f>;
                };
                rk806_slave_dvs1_slp {
                    pins = "gpio_pwrctrl1";
                    function = "pin_fun1";
                };
                rk806_slave_dvs1_pwrdn {
                    pins = "gpio_pwrctrl1";
                    function = "pin_fun2";
                };
                rk806_slave_dvs1_rst {
                    pins = "gpio_pwrctrl1";
                    function = "pin_fun3";
                };
                rk806_slave_dvs2_null {
                    pins = "gpio_pwrctrl2";
                    function = "pin_fun0";
                    phandle = <0x00000140>;
                };
                rk806_slave_dvs2_slp {
                    pins = "gpio_pwrctrl2";
                    function = "pin_fun1";
                };
                rk806_slave_dvs2_pwrdn {
                    pins = "gpio_pwrctrl2";
                    function = "pin_fun2";
                };
                rk806_slave_dvs2_rst {
                    pins = "gpio_pwrctrl2";
                    function = "pin_fun3";
                };
                rk806_slave_dvs2_dvs {
                    pins = "gpio_pwrctrl2";
                    function = "pin_fun4";
                };
                rk806_slave_dvs2_gpio {
                    pins = "gpio_pwrctrl2";
                    function = "pin_fun5";
                };
                rk806_slave_dvs3_null {
                    pins = "gpio_pwrctrl3";
                    function = "pin_fun0";
                    phandle = <0x00000141>;
                };
                rk806_slave_dvs3_slp {
                    pins = "gpio_pwrctrl3";
                    function = "pin_fun1";
                };
                rk806_slave_dvs3_pwrdn {
                    pins = "gpio_pwrctrl3";
                    function = "pin_fun2";
                };
                rk806_slave_dvs3_rst {
                    pins = "gpio_pwrctrl3";
                    function = "pin_fun3";
                };
                rk806_slave_dvs3_dvs {
                    pins = "gpio_pwrctrl3";
                    function = "pin_fun4";
                };
                rk806_slave_dvs3_gpio {
                    pins = "gpio_pwrctrl3";
                    function = "pin_fun5";
                };
            };
            regulators {
                DCDC_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00086470>;
                    regulator-max-microvolt = <0x00100590>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_cpu_big1_s0";
                    phandle = <0x0000001e>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00086470>;
                    regulator-max-microvolt = <0x00100590>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_cpu_big0_s0";
                    phandle = <0x00000019>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00086470>;
                    regulator-max-microvolt = <0x000e7ef0>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_cpu_lit_s0";
                    phandle = <0x00000012>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00325aa0>;
                    regulator-max-microvolt = <0x00325aa0>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vcc_3v3_s0";
                    phandle = <0x000001b3>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000a4cb8>;
                    regulator-max-microvolt = <0x00100590>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_cpu_big1_mem_s0";
                    phandle = <0x0000001f>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG6 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000a4cb8>;
                    regulator-max-microvolt = <0x00100590>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_cpu_big0_mem_s0";
                    phandle = <0x0000001a>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG7 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vcc_1v8_s0";
                    phandle = <0x0000015c>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG8 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000a4cb8>;
                    regulator-max-microvolt = <0x000e7ef0>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_cpu_lit_mem_s0";
                    phandle = <0x00000013>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG9 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-name = "vddq_ddr_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG10 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000cf850>;
                    regulator-max-microvolt = <0x000cf850>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_ddr_s0";
                    phandle = <0x00000037>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                PLDO_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vcc_1v8_cam_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                PLDO_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "avdd1v8_ddr_pll_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                PLDO_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_1v8_pll_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                PLDO_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00325aa0>;
                    regulator-max-microvolt = <0x00325aa0>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vcc_3v3_sd_s0";
                    phandle = <0x000000ed>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                PLDO_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x002ab980>;
                    regulator-max-microvolt = <0x002ab980>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vcc_2v8_cam_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                PLDO_REG6 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "pldo6_s3";
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x001b7740>;
                    };
                };
                NLDO_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000b71b0>;
                    regulator-max-microvolt = <0x000b71b0>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "vdd_0v75_pll_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                NLDO_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000cf850>;
                    regulator-max-microvolt = <0x000cf850>;
                    regulator-name = "vdd_ddr_pll_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                NLDO_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000cf850>;
                    regulator-max-microvolt = <0x000cf850>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "avdd_0v85_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                NLDO_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00124f80>;
                    regulator-max-microvolt = <0x00124f80>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "avdd_1v2_cam_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                NLDO_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00124f80>;
                    regulator-max-microvolt = <0x00124f80>;
                    regulator-ramp-delay = <0x000030d4>;
                    regulator-name = "avdd_1v2_s0";
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
            };
        };
    };
    spi@feb30000 {
        compatible = "rockchip,rk3066-spi";
        reg = <0x00000000 0xfeb30000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000149 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x00000002 0x000000a6 0x00000002 0x000000a1>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x000000cc 0x00000011 0x000000cc 0x00000012>;
        dma-names = "tx", "rx";
        pinctrl-names = "default";
        pinctrl-0 = <0x00000142 0x00000143 0x00000144>;
        num-cs = <0x00000002>;
        status = "disabled";
    };
    serial@feb40000 {
        compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfeb40000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000014c 0x00000004>;
        clocks = <0x00000002 0x000000b7 0x00000002 0x000000ab>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000005b 0x00000008 0x0000005b 0x00000009>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000145>;
        status = "disabled";
    };
    serial@feb50000 {
        compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfeb50000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000014d 0x00000004>;
        clocks = <0x00000002 0x000000bb 0x00000002 0x000000ac>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000005b 0x0000000a 0x0000005b 0x0000000b>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000146>;
        status = "disabled";
    };
    serial@feb60000 {
        compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfeb60000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000014e 0x00000004>;
        clocks = <0x00000002 0x000000bf 0x00000002 0x000000ad>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000005b 0x0000000c 0x0000005b 0x0000000d>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000147>;
        status = "disabled";
    };
    serial@feb70000 {
        compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfeb70000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000014f 0x00000004>;
        clocks = <0x00000002 0x000000c3 0x00000002 0x000000ae>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x000000cc 0x00000009 0x000000cc 0x0000000a>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000148>;
        status = "disabled";
    };
    serial@feb80000 {
        compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfeb80000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000150 0x00000004>;
        clocks = <0x00000002 0x000000c7 0x00000002 0x000000af>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x000000cc 0x0000000b 0x000000cc 0x0000000c>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000149>;
        status = "disabled";
    };
    serial@feb90000 {
        compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfeb90000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000151 0x00000004>;
        clocks = <0x00000002 0x000000cb 0x00000002 0x000000b0>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x000000cc 0x0000000d 0x000000cc 0x0000000e>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000014a>;
        status = "disabled";
    };
    serial@feba0000 {
        compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfeba0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000152 0x00000004>;
        clocks = <0x00000002 0x000000cf 0x00000002 0x000000b1>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x000000cd 0x00000007 0x000000cd 0x00000008>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000014b>;
        status = "disabled";
    };
    serial@febb0000 {
        compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfebb0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000153 0x00000004>;
        clocks = <0x00000002 0x000000d3 0x00000002 0x000000b2>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x000000cd 0x00000009 0x000000cd 0x0000000a>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000014c>;
        status = "disabled";
    };
    serial@febc0000 {
        compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfebc0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000154 0x00000004>;
        clocks = <0x00000002 0x000000d7 0x00000002 0x000000b3>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x000000cd 0x0000000b 0x000000cd 0x0000000c>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000014d>;
        status = "disabled";
    };
    pwm@febd0000 {
        compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfebd0000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x0000014e>;
        clocks = <0x00000002 0x00000054 0x00000002 0x00000053>;
        clock-names = "pwm", "pclk";
        status = "disabled";
    };
    pwm@febd0010 {
        compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfebd0010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x0000014f>;
        clocks = <0x00000002 0x00000054 0x00000002 0x00000053>;
        clock-names = "pwm", "pclk";
        status = "disabled";
    };
    pwm@febd0020 {
        compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfebd0020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000150>;
        clocks = <0x00000002 0x00000054 0x00000002 0x00000053>;
        clock-names = "pwm", "pclk";
        status = "okay";
    };
    pwm@febd0030 {
        compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfebd0030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x0000015a 0x00000004 0x00000000 0x0000015b 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000151>;
        clocks = <0x00000002 0x00000054 0x00000002 0x00000053>;
        clock-names = "pwm", "pclk";
        status = "disabled";
    };
    pwm@febe0000 {
        compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfebe0000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000152>;
        clocks = <0x00000002 0x00000057 0x00000002 0x00000056>;
        clock-names = "pwm", "pclk";
        status = "disabled";
    };
    pwm@febe0010 {
        compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfebe0010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000153>;
        clocks = <0x00000002 0x00000057 0x00000002 0x00000056>;
        clock-names = "pwm", "pclk";
        status = "disabled";
    };
    pwm@febe0020 {
        compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfebe0020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000154>;
        clocks = <0x00000002 0x00000057 0x00000002 0x00000056>;
        clock-names = "pwm", "pclk";
        status = "disabled";
    };
    pwm@febe0030 {
        compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfebe0030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x0000015c 0x00000004 0x00000000 0x0000015d 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000155>;
        clocks = <0x00000002 0x00000057 0x00000002 0x00000056>;
        clock-names = "pwm", "pclk";
        status = "disabled";
    };
    pwm@febf0000 {
        compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfebf0000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000156>;
        clocks = <0x00000002 0x0000005a 0x00000002 0x00000059>;
        clock-names = "pwm", "pclk";
        status = "okay";
    };
    pwm@febf0010 {
        compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfebf0010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000157>;
        clocks = <0x00000002 0x0000005a 0x00000002 0x00000059>;
        clock-names = "pwm", "pclk";
        status = "disabled";
    };
    pwm@febf0020 {
        compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfebf0020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000158>;
        clocks = <0x00000002 0x0000005a 0x00000002 0x00000059>;
        clock-names = "pwm", "pclk";
        status = "okay";
    };
    pwm@febf0030 {
        compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfebf0030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x0000015e 0x00000004 0x00000000 0x0000015f 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000159>;
        clocks = <0x00000002 0x0000005a 0x00000002 0x00000059>;
        clock-names = "pwm", "pclk";
        status = "okay";
        phandle = <0x000001a6>;
    };
    tsadc@fec00000 {
        compatible = "rockchip,rk3588-tsadc";
        reg = <0x00000000 0xfec00000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000018d 0x00000004>;
        clocks = <0x00000002 0x000000aa 0x00000002 0x000000a9>;
        clock-names = "tsadc", "apb_pclk";
        assigned-clocks = <0x00000002 0x000000aa>;
        assigned-clock-rates = <0x001e8480>;
        resets = <0x00000002 0x000000c1 0x00000002 0x000000c0>;
        reset-names = "tsadc", "tsadc-apb";
        #thermal-sensor-cells = <0x00000001>;
        rockchip,hw-tshut-temp = <0x0001d4c0>;
        rockchip,hw-tshut-mode = <0x00000000>;
        rockchip,hw-tshut-polarity = <0x00000000>;
        pinctrl-names = "gpio", "otpout";
        pinctrl-0 = <0x0000015a>;
        pinctrl-1 = <0x0000015b>;
        status = "okay";
        phandle = <0x00000044>;
    };
    saradc@fec10000 {
        compatible = "rockchip,rk3588-saradc";
        reg = <0x00000000 0xfec10000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x0000018e 0x00000004>;
        #io-channel-cells = <0x00000001>;
        clocks = <0x00000002 0x0000009d 0x00000002 0x0000009c>;
        clock-names = "saradc", "apb_pclk";
        resets = <0x00000002 0x000000be>;
        reset-names = "saradc-apb";
        status = "okay";
        vref-supply = <0x0000015c>;
        phandle = <0x000001a9>;
    };
    mailbox@fec60000 {
        compatible = "rockchip,rk3588-mailbox", "rockchip,rk3368-mailbox";
        reg = <0x00000000 0xfec60000 0x00000000 0x00000200>;
        interrupts = <0x00000000 0x0000003d 0x00000004 0x00000000 0x0000003e 0x00000004 0x00000000 0x0000003f 0x00000004 0x00000000 0x00000040 0x00000004>;
        clocks = <0x00000002 0x0000004c>;
        clock-names = "pclk_mailbox";
        #mbox-cells = <0x00000001>;
        status = "disabled";
    };
    mailbox@fec70000 {
        compatible = "rockchip,rk3588-mailbox", "rockchip,rk3368-mailbox";
        reg = <0x00000000 0xfec70000 0x00000000 0x00000200>;
        interrupts = <0x00000000 0x00000045 0x00000004 0x00000000 0x00000046 0x00000004 0x00000000 0x00000047 0x00000004 0x00000000 0x00000048 0x00000004>;
        clocks = <0x00000002 0x0000004d>;
        clock-names = "pclk_mailbox";
        #mbox-cells = <0x00000001>;
        status = "disabled";
    };
    i2c@fec80000 {
        compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfec80000 0x00000000 0x00001000>;
        clocks = <0x00000002 0x00000092 0x00000002 0x0000008a>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000143 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000015d>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        clock-frequency = <0x00061a80>;
        anx7411@2c {
            status = "okay";
            compatible = "analogix,anx7411";
            reg = <0x0000002c>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            interrupt-parent = <0x0000011a>;
            interrupts = <0x0000000f 0x00000008>;
            extcon = <0x00000126>;
            pinctrl-names = "default";
            pinctrl-0 = <0x0000015e>;
            phandle = <0x00000124>;
            port {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000015f>;
                    phandle = <0x00000181>;
                };
            };
            connector@0 {
                compatible = "usb-c-connector";
                reg = <0x00000000>;
                power-role = "dual";
                data-role = "dual";
                try-power-role = "sink";
                altmodes {
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    altmode@0 {
                        reg = <0x00000000>;
                        svid = <0x0000ff01>;
                        vdo = <0xffffffff>;
                    };
                };
                ports {
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    port@0 {
                        reg = <0x00000000>;
                        endpoint {
                            remote-endpoint = <0x00000160>;
                            phandle = <0x000001a1>;
                        };
                    };
                    port@1 {
                        reg = <0x00000001>;
                        endpoint {
                            remote-endpoint = <0x00000161>;
                            phandle = <0x000001a2>;
                        };
                    };
                };
            };
        };
    };
    i2c@fec90000 {
        compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfec90000 0x00000000 0x00001000>;
        clocks = <0x00000002 0x00000093 0x00000002 0x0000008b>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000144 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000162>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        clock-frequency = <0x00061a80>;
        touchpanel@10 {
            compatible = "hid-over-i2c";
            hid-descr-addr = <0x00000010>;
            interrupt-parent = <0x00000122>;
            interrupts = <0x0000001b 0x00000008>;
            pinctrl-0 = <0x00000163>;
            reset-gpios = <0x00000122 0x0000001a 0x00000001>;
            status = "okay";
        };
    };
    i2c@feca0000 {
        compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfeca0000 0x00000000 0x00001000>;
        clocks = <0x00000002 0x00000094 0x00000002 0x0000008c>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000145 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000164>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
    };
    spi@fecb0000 {
        compatible = "rockchip,rk3066-spi";
        reg = <0x00000000 0xfecb0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x0000014a 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x00000002 0x000000a7 0x00000002 0x000000a2>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x000000cd 0x0000000d 0x000000cd 0x0000000e>;
        dma-names = "tx", "rx";
        pinctrl-names = "default";
        pinctrl-0 = <0x00000165 0x00000166 0x00000167>;
        num-cs = <0x00000002>;
        status = "disabled";
    };
    otp@fecc0000 {
        compatible = "rockchip,rk3588-otp";
        reg = <0x00000000 0xfecc0000 0x00000000 0x00000400>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        clocks = <0x00000002 0x00000096 0x00000002 0x00000095 0x00000002 0x00000097 0x00000002 0x00000099>;
        clock-names = "otpc", "apb", "arb", "phy";
        resets = <0x00000002 0x0000012a 0x00000002 0x00000129 0x00000002 0x0000012b>;
        reset-names = "otpc", "apb", "arb";
        cpu-code@2 {
            reg = <0x00000002 0x00000002>;
            phandle = <0x00000027>;
        };
        id@7 {
            reg = <0x00000007 0x00000010>;
            phandle = <0x00000025>;
        };
        cpu-version@1c {
            reg = <0x0000001c 0x00000001>;
            bits = <0x00000003 0x00000003>;
            phandle = <0x00000026>;
        };
    };
    mailbox@fece0000 {
        compatible = "rockchip,rk3588-mailbox", "rockchip,rk3368-mailbox";
        reg = <0x00000000 0xfece0000 0x00000000 0x00000200>;
        interrupts = <0x00000000 0x0000004d 0x00000004 0x00000000 0x0000004e 0x00000004 0x00000000 0x0000004f 0x00000004 0x00000000 0x00000050 0x00000004>;
        clocks = <0x00000002 0x0000004e>;
        clock-names = "pclk_mailbox";
        #mbox-cells = <0x00000001>;
        status = "disabled";
    };
    dma-controller@fed10000 {
        compatible = "arm,pl330", "arm,primecell";
        reg = <0x00000000 0xfed10000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x0000005a 0x00000004 0x00000000 0x0000005b 0x00000004>;
        clocks = <0x00000002 0x0000007a>;
        clock-names = "apb_pclk";
        #dma-cells = <0x00000001>;
        arm,pl330-periph-burst;
        phandle = <0x000000cd>;
    };
    phy@fed60000 {
        compatible = "rockchip,rk3588-hdptx-phy";
        reg = <0x00000000 0xfed60000 0x00000000 0x00002000>;
        clocks = <0x00000002 0x000002b5 0x00000002 0x00000267>;
        clock-names = "ref", "apb";
        resets = <0x00000002 0x00000485 0x00000002 0x000c003b 0x00000002 0x000c003c 0x00000002 0x000c003d>;
        reset-names = "apb", "init", "cmn", "lane";
        rockchip,grf = <0x00000168>;
        #phy-cells = <0x00000000>;
        status = "okay";
        lane-polarity-invert = <0x00000000 0x00000000 0x00000000 0x00000000>;
        phandle = <0x000000dd>;
    };
    hdmiphy@fed60000 {
        compatible = "rockchip,rk3588-hdptx-phy-hdmi";
        reg = <0x00000000 0xfed60000 0x00000000 0x00002000>;
        clocks = <0x00000002 0x000002b5 0x00000002 0x00000267>;
        clock-names = "ref", "apb";
        resets = <0x00000002 0x0000048e 0x00000002 0x00000485 0x00000002 0x000c003b 0x00000002 0x000c003c 0x00000002 0x000c003d 0x00000002 0x0000048c 0x00000002 0x0000048d>;
        reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";
        rockchip,grf = <0x00000168>;
        #phy-cells = <0x00000000>;
        #clock-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000000af>;
    };
    phy@fed80000 {
        compatible = "rockchip,rk3588-usbdp-phy";
        reg = <0x00000000 0xfed80000 0x00000000 0x00010000>;
        rockchip,u2phy-grf = <0x00000169>;
        rockchip,usb-grf = <0x00000057>;
        rockchip,usbdpphy-grf = <0x0000016a>;
        rockchip,vo-grf = <0x0000016b>;
        clocks = <0x00000002 0x000002b6 0x00000002 0x0000027f 0x00000002 0x00000269 0x0000011b>;
        clock-names = "refclk", "immortal", "pclk", "utmi";
        resets = <0x00000002 0x00000028 0x00000002 0x00000029 0x00000002 0x0000002a 0x00000002 0x0000002b 0x00000002 0x00000482>;
        reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
        status = "okay";
        orientation-switch;
        svid = <0x0000ff01>;
        dp-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            phandle = <0x000000d2>;
        };
        u3-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            phandle = <0x0000004d>;
        };
        port {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            endpoint@0 {
                reg = <0x00000000>;
                remote-endpoint = <0x0000016c>;
                phandle = <0x0000011e>;
            };
            endpoint@1 {
                reg = <0x00000001>;
                remote-endpoint = <0x0000016d>;
                phandle = <0x0000011f>;
            };
        };
    };
    phy@feda0000 {
        compatible = "rockchip,rk3588-mipi-dcphy";
        reg = <0x00000000 0xfeda0000 0x00000000 0x00000b00>;
        rockchip,grf = <0x0000016e>;
        clocks = <0x00000002 0x00000108 0x00000002 0x000002b6>;
        clock-names = "pclk", "ref";
        resets = <0x00000002 0x000c0043 0x00000002 0x0000003e 0x00000002 0x0000003f>;
        reset-names = "phy", "apb", "grf";
        #phy-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000000ce>;
    };
    csi2-dcphy0-hw@feda0b00 {
        compatible = "rockchip,rk3588-csi2-dcphy-hw";
        reg = <0x00000000 0xfeda0b00 0x00000000 0x0000f500>;
        clocks = <0x00000002 0x00000108>;
        clock-names = "pclk";
        resets = <0x00000002 0x000c0044>;
        reset-names = "phy";
        rockchip,grf = <0x0000016e>;
        status = "disabled";
        phandle = <0x00000028>;
    };
    phy@fedb0000 {
        compatible = "rockchip,rk3588-mipi-dcphy";
        reg = <0x00000000 0xfedb0000 0x00000000 0x00000b00>;
        rockchip,grf = <0x0000016f>;
        clocks = <0x00000002 0x00000109 0x00000002 0x000002b6>;
        clock-names = "pclk", "ref";
        resets = <0x00000002 0x000c0045 0x00000002 0x00000043 0x00000002 0x00000044>;
        reset-names = "phy", "apb", "grf";
        #phy-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000000d0>;
    };
    csi2-dcphy1-hw@fedb0b00 {
        compatible = "rockchip,rk3588-csi2-dcphy-hw";
        reg = <0x00000000 0xfedb0b00 0x00000000 0x0000f500>;
        clocks = <0x00000002 0x00000109>;
        clock-names = "pclk";
        resets = <0x00000002 0x000c0046>;
        reset-names = "phy";
        rockchip,grf = <0x0000016f>;
        status = "disabled";
        phandle = <0x00000029>;
    };
    csi2-dphy0-hw@fedc0000 {
        compatible = "rockchip,rk3588-csi2-dphy-hw";
        reg = <0x00000000 0xfedc0000 0x00000000 0x00008000>;
        clocks = <0x00000002 0x0000010c>;
        clock-names = "pclk";
        resets = <0x00000002 0x00000017 0x00000002 0x00000016>;
        reset-names = "srst_csiphy0", "srst_p_csiphy0";
        rockchip,grf = <0x00000170>;
        rockchip,sys_grf = <0x000000ae>;
        status = "disabled";
        phandle = <0x0000002a>;
    };
    phy@fee00000 {
        compatible = "rockchip,rk3588-naneng-combphy";
        reg = <0x00000000 0xfee00000 0x00000000 0x00000100>;
        #phy-cells = <0x00000001>;
        clocks = <0x00000002 0x000002bd 0x00000002 0x00000185 0x00000002 0x00000166>;
        clock-names = "refclk", "apbclk", "phpclk";
        assigned-clocks = <0x00000002 0x000002bd>;
        assigned-clock-rates = <0x05f5e100>;
        resets = <0x00000002 0x00020005 0x00000002 0x000004d6>;
        reset-names = "combphy-apb", "combphy";
        rockchip,pipe-grf = <0x00000059>;
        rockchip,pipe-phy-grf = <0x00000171>;
        status = "okay";
        phandle = <0x000000e5>;
    };
    phy@fee20000 {
        compatible = "rockchip,rk3588-naneng-combphy";
        reg = <0x00000000 0xfee20000 0x00000000 0x00000100>;
        #phy-cells = <0x00000001>;
        clocks = <0x00000002 0x000002bf 0x00000002 0x00000187 0x00000002 0x00000166>;
        clock-names = "refclk", "apbclk", "phpclk";
        assigned-clocks = <0x00000002 0x000002bf>;
        assigned-clock-rates = <0x05f5e100>;
        resets = <0x00000002 0x00020007 0x00000002 0x000004d8>;
        reset-names = "combphy-apb", "combphy";
        rockchip,pipe-grf = <0x00000059>;
        rockchip,pipe-phy-grf = <0x00000172>;
        rockchip,pcie1ln-sel-bits = <0x00000100 0x00000001 0x00000001 0x00000000>;
        status = "okay";
        phandle = <0x00000053>;
    };
    pinctrl {
        compatible = "rockchip,rk3588-pinctrl";
        rockchip,grf = <0x00000173>;
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        phandle = <0x00000174>;
        gpio@fd8a0000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfd8a0000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000115 0x00000004>;
            clocks = <0x00000002 0x00000284 0x00000002 0x00000285>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000174 0x00000000 0x00000000 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x00000122>;
        };
        gpio@fec20000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfec20000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000116 0x00000004>;
            clocks = <0x00000002 0x0000007d 0x00000002 0x0000007e>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000174 0x00000000 0x00000020 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x000000d4>;
        };
        gpio@fec30000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfec30000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000117 0x00000004>;
            clocks = <0x00000002 0x0000007f 0x00000002 0x00000080>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000174 0x00000000 0x00000040 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
        };
        gpio@fec40000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfec40000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000118 0x00000004>;
            clocks = <0x00000002 0x00000081 0x00000002 0x00000082>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000174 0x00000000 0x00000060 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x000001a7>;
        };
        gpio@fec50000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfec50000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000119 0x00000004>;
            clocks = <0x00000002 0x00000083 0x00000002 0x00000084>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000174 0x00000000 0x00000080 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x0000011a>;
        };
        pcfg-pull-up {
            bias-pull-up;
            phandle = <0x00000178>;
        };
        pcfg-pull-none {
            bias-disable;
            phandle = <0x00000175>;
        };
        pcfg-pull-none-drv-level-2 {
            bias-disable;
            drive-strength = <0x00000002>;
            phandle = <0x0000017a>;
        };
        pcfg-pull-up-drv-level-1 {
            bias-pull-up;
            drive-strength = <0x00000001>;
            phandle = <0x00000179>;
        };
        pcfg-pull-up-drv-level-2 {
            bias-pull-up;
            drive-strength = <0x00000002>;
            phandle = <0x00000176>;
        };
        pcfg-pull-none-smt {
            bias-disable;
            input-schmitt-enable;
            phandle = <0x00000177>;
        };
        pcfg-output-high {
            output-high;
            phandle = <0x0000017b>;
        };
        auddsm {
            auddsm-pins {
                rockchip,pins = <0x00000003 0x00000001 0x00000004 0x00000175 0x00000003 0x00000002 0x00000004 0x00000175 0x00000003 0x00000003 0x00000004 0x00000175 0x00000003 0x00000004 0x00000004 0x00000175>;
                phandle = <0x00000115>;
            };
        };
        bt1120 {
            bt1120-pins {
                rockchip,pins = <0x00000004 0x00000008 0x00000002 0x00000175 0x00000004 0x00000000 0x00000002 0x00000175 0x00000004 0x00000001 0x00000002 0x00000175 0x00000004 0x00000002 0x00000002 0x00000175 0x00000004 0x00000003 0x00000002 0x00000175 0x00000004 0x00000004 0x00000002 0x00000175 0x00000004 0x00000005 0x00000002 0x00000175 0x00000004 0x00000006 0x00000002 0x00000175 0x00000004 0x00000007 0x00000002 0x00000175 0x00000004 0x0000000a 0x00000002 0x00000175 0x00000004 0x0000000b 0x00000002 0x00000175 0x00000004 0x0000000c 0x00000002 0x00000175 0x00000004 0x0000000d 0x00000002 0x00000175 0x00000004 0x0000000e 0x00000002 0x00000175 0x00000004 0x0000000f 0x00000002 0x00000175 0x00000004 0x00000010 0x00000002 0x00000175 0x00000004 0x00000011 0x00000002 0x00000175>;
                phandle = <0x00000054>;
            };
        };
        can0 {
            can0m0-pins {
                rockchip,pins = <0x00000000 0x00000010 0x0000000b 0x00000175 0x00000000 0x0000000f 0x0000000b 0x00000175>;
                phandle = <0x00000116>;
            };
        };
        can1 {
            can1m0-pins {
                rockchip,pins = <0x00000003 0x0000000d 0x00000009 0x00000175 0x00000003 0x0000000e 0x00000009 0x00000175>;
                phandle = <0x00000117>;
            };
        };
        can2 {
            can2m0-pins {
                rockchip,pins = <0x00000003 0x00000014 0x00000009 0x00000175 0x00000003 0x00000015 0x00000009 0x00000175>;
                phandle = <0x00000118>;
            };
        };
        hdmi {
            hdmim0-tx0-cec {
                rockchip,pins = <0x00000004 0x00000011 0x00000005 0x00000175>;
                phandle = <0x000000d7>;
            };
            hdmim0-tx0-hpd {
                rockchip,pins = <0x00000001 0x00000005 0x00000005 0x00000175>;
                phandle = <0x000000d8>;
            };
            hdmim0-tx0-scl {
                rockchip,pins = <0x00000004 0x0000000f 0x00000005 0x00000175>;
                phandle = <0x000000d9>;
            };
            hdmim0-tx0-sda {
                rockchip,pins = <0x00000004 0x00000010 0x00000005 0x00000175>;
                phandle = <0x000000da>;
            };
            hdmim0-tx1-hpd {
                rockchip,pins = <0x00000001 0x00000006 0x00000005 0x00000175>;
                phandle = <0x00000187>;
            };
            hdmim1-rx-cec {
                rockchip,pins = <0x00000003 0x00000019 0x00000005 0x00000175>;
                phandle = <0x00000190>;
            };
            hdmim1-rx-hpdin {
                rockchip,pins = <0x00000003 0x0000001c 0x00000005 0x00000175>;
                phandle = <0x00000191>;
            };
            hdmim1-rx-scl {
                rockchip,pins = <0x00000003 0x0000001a 0x00000005 0x00000175>;
                phandle = <0x00000192>;
            };
            hdmim1-rx-sda {
                rockchip,pins = <0x00000003 0x0000001b 0x00000005 0x00000175>;
                phandle = <0x00000193>;
            };
            hdmim1-tx1-scl {
                rockchip,pins = <0x00000003 0x00000016 0x00000005 0x00000175>;
                phandle = <0x00000188>;
            };
            hdmim1-tx1-sda {
                rockchip,pins = <0x00000003 0x00000015 0x00000005 0x00000175>;
                phandle = <0x00000189>;
            };
            hdmim2-tx1-cec {
                rockchip,pins = <0x00000003 0x00000014 0x00000005 0x00000175>;
                phandle = <0x00000186>;
            };
        };
        i2c0 {
            i2c0m0-xfer {
                rockchip,pins = <0x00000000 0x0000000b 0x00000002 0x00000177 0x00000000 0x00000006 0x00000002 0x00000177>;
                phandle = <0x0000005a>;
            };
        };
        i2c1 {
            i2c1m0-xfer {
                rockchip,pins = <0x00000000 0x0000000d 0x00000009 0x00000177 0x00000000 0x0000000e 0x00000009 0x00000177>;
                phandle = <0x00000119>;
            };
        };
        i2c2 {
            i2c2m0-xfer {
                rockchip,pins = <0x00000000 0x0000000f 0x00000009 0x00000177 0x00000000 0x00000010 0x00000009 0x00000177>;
                phandle = <0x00000120>;
            };
        };
        i2c3 {
            i2c3m0-xfer {
                rockchip,pins = <0x00000001 0x00000011 0x00000009 0x00000177 0x00000001 0x00000010 0x00000009 0x00000177>;
                phandle = <0x00000127>;
            };
        };
        i2c4 {
            i2c4m3-xfer {
                rockchip,pins = <0x00000001 0x00000003 0x00000009 0x00000177 0x00000001 0x00000002 0x00000009 0x00000177>;
                phandle = <0x0000012b>;
            };
        };
        i2c5 {
            i2c5m0-xfer {
                rockchip,pins = <0x00000003 0x00000017 0x00000009 0x00000177 0x00000003 0x00000018 0x00000009 0x00000177>;
                phandle = <0x0000012d>;
            };
        };
        i2c6 {
            i2c6m0-xfer {
                rockchip,pins = <0x00000000 0x00000018 0x00000009 0x00000177 0x00000000 0x00000017 0x00000009 0x00000177>;
                phandle = <0x0000015d>;
            };
        };
        i2c7 {
            i2c7m2-xfer {
                rockchip,pins = <0x00000003 0x0000001a 0x00000009 0x00000177 0x00000003 0x0000001b 0x00000009 0x00000177>;
                phandle = <0x00000162>;
            };
        };
        i2c8 {
            i2c8m0-xfer {
                rockchip,pins = <0x00000004 0x0000001a 0x00000009 0x00000177 0x00000004 0x0000001b 0x00000009 0x00000177>;
                phandle = <0x00000164>;
            };
        };
        i2s0 {
            i2s0-lrck {
                rockchip,pins = <0x00000001 0x00000015 0x00000001 0x00000175>;
                phandle = <0x000000f1>;
            };
            i2s0-mclk {
                rockchip,pins = <0x00000001 0x00000012 0x00000001 0x00000175>;
                phandle = <0x00000128>;
            };
            i2s0-sclk {
                rockchip,pins = <0x00000001 0x00000013 0x00000001 0x00000175>;
                phandle = <0x000000f2>;
            };
            i2s0-sdi0 {
                rockchip,pins = <0x00000001 0x0000001c 0x00000002 0x00000175>;
                phandle = <0x000000f3>;
            };
            i2s0-sdo0 {
                rockchip,pins = <0x00000001 0x00000017 0x00000001 0x00000175>;
                phandle = <0x000000f4>;
            };
        };
        i2s1 {
            i2s1m0-lrck {
                rockchip,pins = <0x00000004 0x00000002 0x00000003 0x00000175>;
                phandle = <0x000000f5>;
            };
            i2s1m0-sclk {
                rockchip,pins = <0x00000004 0x00000001 0x00000003 0x00000175>;
                phandle = <0x000000f6>;
            };
            i2s1m0-sdi0 {
                rockchip,pins = <0x00000004 0x00000005 0x00000003 0x00000175>;
                phandle = <0x000000f7>;
            };
            i2s1m0-sdi1 {
                rockchip,pins = <0x00000004 0x00000006 0x00000003 0x00000175>;
                phandle = <0x000000f8>;
            };
            i2s1m0-sdi2 {
                rockchip,pins = <0x00000004 0x00000007 0x00000003 0x00000175>;
                phandle = <0x000000f9>;
            };
            i2s1m0-sdi3 {
                rockchip,pins = <0x00000004 0x00000008 0x00000003 0x00000175>;
                phandle = <0x000000fa>;
            };
            i2s1m0-sdo0 {
                rockchip,pins = <0x00000004 0x00000009 0x00000003 0x00000175>;
                phandle = <0x000000fb>;
            };
            i2s1m0-sdo1 {
                rockchip,pins = <0x00000004 0x0000000a 0x00000003 0x00000175>;
                phandle = <0x000000fc>;
            };
            i2s1m0-sdo2 {
                rockchip,pins = <0x00000004 0x0000000b 0x00000003 0x00000175>;
                phandle = <0x000000fd>;
            };
            i2s1m0-sdo3 {
                rockchip,pins = <0x00000004 0x0000000c 0x00000003 0x00000175>;
                phandle = <0x000000fe>;
            };
        };
        i2s2 {
            i2s2m1-lrck {
                rockchip,pins = <0x00000003 0x0000000e 0x00000003 0x00000175>;
                phandle = <0x000000ff>;
            };
            i2s2m1-sclk {
                rockchip,pins = <0x00000003 0x0000000d 0x00000003 0x00000175>;
                phandle = <0x00000100>;
            };
            i2s2m1-sdi {
                rockchip,pins = <0x00000003 0x0000000a 0x00000003 0x00000175>;
                phandle = <0x00000101>;
            };
            i2s2m1-sdo {
                rockchip,pins = <0x00000003 0x0000000b 0x00000003 0x00000175>;
                phandle = <0x00000102>;
            };
        };
        i2s3 {
            i2s3-lrck {
                rockchip,pins = <0x00000003 0x00000002 0x00000003 0x00000175>;
                phandle = <0x00000103>;
            };
            i2s3-sclk {
                rockchip,pins = <0x00000003 0x00000001 0x00000003 0x00000175>;
                phandle = <0x00000104>;
            };
            i2s3-sdi {
                rockchip,pins = <0x00000003 0x00000004 0x00000003 0x00000175>;
                phandle = <0x00000105>;
            };
            i2s3-sdo {
                rockchip,pins = <0x00000003 0x00000003 0x00000003 0x00000175>;
                phandle = <0x00000106>;
            };
        };
        pdm0 {
            pdm0m0-clk {
                rockchip,pins = <0x00000001 0x00000016 0x00000003 0x00000175>;
                phandle = <0x00000107>;
            };
            pdm0m0-clk1 {
                rockchip,pins = <0x00000001 0x00000014 0x00000003 0x00000175>;
                phandle = <0x00000108>;
            };
            pdm0m0-sdi0 {
                rockchip,pins = <0x00000001 0x0000001d 0x00000003 0x00000175>;
                phandle = <0x00000109>;
            };
            pdm0m0-sdi1 {
                rockchip,pins = <0x00000001 0x00000019 0x00000003 0x00000175>;
                phandle = <0x0000010a>;
            };
            pdm0m0-sdi2 {
                rockchip,pins = <0x00000001 0x0000001a 0x00000003 0x00000175>;
                phandle = <0x0000010b>;
            };
            pdm0m0-sdi3 {
                rockchip,pins = <0x00000001 0x0000001b 0x00000003 0x00000175>;
                phandle = <0x0000010c>;
            };
        };
        pdm1 {
            pdm1m0-clk {
                rockchip,pins = <0x00000004 0x0000001d 0x00000002 0x00000175>;
                phandle = <0x0000010d>;
            };
            pdm1m0-clk1 {
                rockchip,pins = <0x00000004 0x0000001c 0x00000002 0x00000175>;
                phandle = <0x0000010e>;
            };
            pdm1m0-sdi0 {
                rockchip,pins = <0x00000004 0x0000001b 0x00000002 0x00000175>;
                phandle = <0x0000010f>;
            };
            pdm1m0-sdi1 {
                rockchip,pins = <0x00000004 0x0000001a 0x00000002 0x00000175>;
                phandle = <0x00000110>;
            };
            pdm1m0-sdi2 {
                rockchip,pins = <0x00000004 0x00000019 0x00000002 0x00000175>;
                phandle = <0x00000111>;
            };
            pdm1m0-sdi3 {
                rockchip,pins = <0x00000004 0x00000018 0x00000002 0x00000175>;
                phandle = <0x00000112>;
            };
        };
        pmic {
            pmic-pins {
                rockchip,pins = <0x00000000 0x00000007 0x00000000 0x00000178 0x00000000 0x00000002 0x00000001 0x00000175 0x00000000 0x00000003 0x00000001 0x00000175 0x00000000 0x00000011 0x00000001 0x00000175 0x00000000 0x00000012 0x00000001 0x00000175 0x00000000 0x00000013 0x00000001 0x00000175 0x00000000 0x0000001e 0x00000001 0x00000175>;
                phandle = <0x00000137>;
            };
        };
        pwm0 {
            pwm0m0-pins {
                rockchip,pins = <0x00000000 0x0000000f 0x00000003 0x00000175>;
                phandle = <0x0000005d>;
            };
        };
        pwm1 {
            pwm1m0-pins {
                rockchip,pins = <0x00000000 0x00000010 0x00000003 0x00000175>;
                phandle = <0x0000005e>;
            };
        };
        pwm2 {
            pwm2m0-pins {
                rockchip,pins = <0x00000000 0x00000014 0x00000003 0x00000175>;
                phandle = <0x0000005f>;
            };
        };
        pwm3 {
            pwm3m0-pins {
                rockchip,pins = <0x00000000 0x0000001c 0x00000003 0x00000175>;
                phandle = <0x00000060>;
            };
        };
        pwm4 {
            pwm4m0-pins {
                rockchip,pins = <0x00000000 0x00000015 0x0000000b 0x00000175>;
                phandle = <0x0000014e>;
            };
        };
        pwm5 {
            pwm5m0-pins {
                rockchip,pins = <0x00000000 0x00000009 0x00000003 0x00000175>;
                phandle = <0x0000014f>;
            };
        };
        pwm6 {
            pwm6m1-pins {
                rockchip,pins = <0x00000004 0x00000011 0x0000000b 0x00000175>;
                phandle = <0x00000150>;
            };
        };
        pwm7 {
            pwm7m0-pins {
                rockchip,pins = <0x00000000 0x00000018 0x0000000b 0x00000175>;
                phandle = <0x00000151>;
            };
        };
        pwm8 {
            pwm8m0-pins {
                rockchip,pins = <0x00000003 0x00000007 0x0000000b 0x00000175>;
                phandle = <0x00000152>;
            };
        };
        pwm9 {
            pwm9m0-pins {
                rockchip,pins = <0x00000003 0x00000008 0x0000000b 0x00000175>;
                phandle = <0x00000153>;
            };
        };
        pwm10 {
            pwm10m0-pins {
                rockchip,pins = <0x00000003 0x00000000 0x0000000b 0x00000175>;
                phandle = <0x00000154>;
            };
        };
        pwm11 {
            pwm11m0-pins {
                rockchip,pins = <0x00000003 0x00000001 0x0000000b 0x00000175>;
                phandle = <0x00000155>;
            };
        };
        pwm12 {
            pwm12m0-pins {
                rockchip,pins = <0x00000003 0x0000000d 0x0000000b 0x00000175>;
                phandle = <0x00000156>;
            };
        };
        pwm13 {
            pwm13m0-pins {
                rockchip,pins = <0x00000003 0x0000000e 0x0000000b 0x00000175>;
                phandle = <0x00000157>;
            };
        };
        pwm14 {
            pwm14m2-pins {
                rockchip,pins = <0x00000001 0x0000001e 0x0000000b 0x00000175>;
                phandle = <0x00000158>;
            };
        };
        pwm15 {
            pwm15m1-pins {
                rockchip,pins = <0x00000004 0x0000000b 0x0000000b 0x00000175>;
                phandle = <0x00000159>;
            };
        };
        sdio {
            sdiom1-pins {
                rockchip,pins = <0x00000003 0x00000005 0x00000002 0x00000175 0x00000003 0x00000004 0x00000002 0x00000175 0x00000003 0x00000000 0x00000002 0x00000175 0x00000003 0x00000001 0x00000002 0x00000175 0x00000003 0x00000002 0x00000002 0x00000175 0x00000003 0x00000003 0x00000002 0x00000175>;
                phandle = <0x000000ef>;
            };
        };
        sdmmc {
            sdmmc-bus4 {
                rockchip,pins = <0x00000004 0x00000018 0x00000001 0x00000176 0x00000004 0x00000019 0x00000001 0x00000176 0x00000004 0x0000001a 0x00000001 0x00000176 0x00000004 0x0000001b 0x00000001 0x00000176>;
                phandle = <0x000000ec>;
            };
            sdmmc-clk {
                rockchip,pins = <0x00000004 0x0000001d 0x00000001 0x00000176>;
                phandle = <0x000000e9>;
            };
            sdmmc-cmd {
                rockchip,pins = <0x00000004 0x0000001c 0x00000001 0x00000176>;
                phandle = <0x000000ea>;
            };
            sdmmc-det {
                rockchip,pins = <0x00000000 0x00000004 0x00000001 0x00000178>;
                phandle = <0x000000eb>;
            };
        };
        spdif0 {
            spdif0m0-tx {
                rockchip,pins = <0x00000001 0x0000000e 0x00000003 0x00000175>;
                phandle = <0x00000113>;
            };
        };
        spdif1 {
            spdif1m0-tx {
                rockchip,pins = <0x00000001 0x0000000f 0x00000003 0x00000175>;
                phandle = <0x00000114>;
            };
        };
        spi0 {
            spi0m0-pins {
                rockchip,pins = <0x00000000 0x00000016 0x00000008 0x00000179 0x00000000 0x00000017 0x00000008 0x00000179 0x00000000 0x00000010 0x00000008 0x00000179>;
                phandle = <0x00000130>;
            };
            spi0m0-cs0 {
                rockchip,pins = <0x00000000 0x00000019 0x00000008 0x00000179>;
                phandle = <0x0000012e>;
            };
            spi0m0-cs1 {
                rockchip,pins = <0x00000000 0x0000000f 0x00000008 0x00000179>;
                phandle = <0x0000012f>;
            };
        };
        spi1 {
            spi1m1-pins {
                rockchip,pins = <0x00000003 0x00000011 0x00000008 0x00000179 0x00000003 0x00000010 0x00000008 0x00000179 0x00000003 0x0000000f 0x00000008 0x00000179>;
                phandle = <0x00000133>;
            };
            spi1m1-cs0 {
                rockchip,pins = <0x00000003 0x00000012 0x00000008 0x00000179>;
                phandle = <0x00000131>;
            };
            spi1m1-cs1 {
                rockchip,pins = <0x00000003 0x00000013 0x00000008 0x00000179>;
                phandle = <0x00000132>;
            };
        };
        spi2 {
            spi2m2-pins {
                rockchip,pins = <0x00000000 0x00000005 0x00000001 0x00000179 0x00000000 0x0000000b 0x00000001 0x00000179 0x00000000 0x00000006 0x00000001 0x00000179>;
                phandle = <0x00000136>;
            };
            spi2m2-cs0 {
                rockchip,pins = <0x00000000 0x00000009 0x00000001 0x00000179>;
                phandle = <0x00000134>;
            };
            spi2m2-cs1 {
                rockchip,pins = <0x00000000 0x00000008 0x00000001 0x00000179>;
                phandle = <0x00000135>;
            };
        };
        spi3 {
            spi3m1-pins {
                rockchip,pins = <0x00000004 0x0000000f 0x00000008 0x00000179 0x00000004 0x0000000d 0x00000008 0x00000179 0x00000004 0x0000000e 0x00000008 0x00000179>;
                phandle = <0x00000144>;
            };
            spi3m1-cs0 {
                rockchip,pins = <0x00000004 0x00000010 0x00000008 0x00000179>;
                phandle = <0x00000142>;
            };
            spi3m1-cs1 {
                rockchip,pins = <0x00000004 0x00000011 0x00000008 0x00000179>;
                phandle = <0x00000143>;
            };
        };
        spi4 {
            spi4m0-pins {
                rockchip,pins = <0x00000001 0x00000012 0x00000008 0x00000179 0x00000001 0x00000010 0x00000008 0x00000179 0x00000001 0x00000011 0x00000008 0x00000179>;
                phandle = <0x00000167>;
            };
            spi4m0-cs0 {
                rockchip,pins = <0x00000001 0x00000013 0x00000008 0x00000179>;
                phandle = <0x00000165>;
            };
            spi4m0-cs1 {
                rockchip,pins = <0x00000001 0x00000014 0x00000008 0x00000179>;
                phandle = <0x00000166>;
            };
        };
        tsadc {
            tsadc-shut {
                rockchip,pins = <0x00000000 0x00000001 0x00000002 0x00000175>;
                phandle = <0x0000015b>;
            };
        };
        uart0 {
            uart0m1-xfer {
                rockchip,pins = <0x00000000 0x00000008 0x00000004 0x00000178 0x00000000 0x00000009 0x00000004 0x00000178>;
                phandle = <0x0000005c>;
            };
        };
        uart1 {
            uart1m1-xfer {
                rockchip,pins = <0x00000001 0x0000000f 0x0000000a 0x00000178 0x00000001 0x0000000e 0x0000000a 0x00000178>;
                phandle = <0x00000145>;
            };
        };
        uart2 {
            uart2m1-xfer {
                rockchip,pins = <0x00000004 0x00000019 0x0000000a 0x00000178 0x00000004 0x00000018 0x0000000a 0x00000178>;
                phandle = <0x00000146>;
            };
        };
        uart3 {
            uart3m1-xfer {
                rockchip,pins = <0x00000003 0x0000000e 0x0000000a 0x00000178 0x00000003 0x0000000d 0x0000000a 0x00000178>;
                phandle = <0x00000147>;
            };
        };
        uart4 {
            uart4m1-xfer {
                rockchip,pins = <0x00000003 0x00000018 0x0000000a 0x00000178 0x00000003 0x00000019 0x0000000a 0x00000178>;
                phandle = <0x00000148>;
            };
        };
        uart5 {
            uart5m1-xfer {
                rockchip,pins = <0x00000003 0x00000015 0x0000000a 0x00000178 0x00000003 0x00000014 0x0000000a 0x00000178>;
                phandle = <0x00000149>;
            };
        };
        uart6 {
            uart6m1-xfer {
                rockchip,pins = <0x00000001 0x00000000 0x0000000a 0x00000178 0x00000001 0x00000001 0x0000000a 0x00000178>;
                phandle = <0x0000014a>;
            };
        };
        uart7 {
            uart7m1-xfer {
                rockchip,pins = <0x00000003 0x00000011 0x0000000a 0x00000178 0x00000003 0x00000010 0x0000000a 0x00000178>;
                phandle = <0x0000014b>;
            };
        };
        uart8 {
            uart8m1-xfer {
                rockchip,pins = <0x00000003 0x00000003 0x0000000a 0x00000178 0x00000003 0x00000002 0x0000000a 0x00000178>;
                phandle = <0x0000014c>;
            };
        };
        uart9 {
            uart9m1-xfer {
                rockchip,pins = <0x00000004 0x0000000d 0x0000000a 0x00000178 0x00000004 0x0000000c 0x0000000a 0x00000178>;
                phandle = <0x0000014d>;
            };
        };
        gpio-func {
            tsadc-gpio-func {
                rockchip,pins = <0x00000000 0x00000001 0x00000000 0x00000175>;
                phandle = <0x0000015a>;
            };
        };
        hp_det {
            hp-det-gpio {
                rockchip,pins = <0x00000001 0x0000001d 0x00000000 0x00000178>;
                phandle = <0x00000129>;
            };
        };
        hym8563 {
            hym8563-int {
                rockchip,pins = <0x00000000 0x0000001c 0x00000000 0x00000178>;
                phandle = <0x00000121>;
            };
        };
        sc8886 {
            charger-ok {
                rockchip,pins = <0x00000000 0x00000014 0x00000000 0x00000178>;
                phandle = <0x00000125>;
            };
        };
        sbs {
            sbs-detect {
                rockchip,pins = <0x00000001 0x00000008 0x00000000 0x00000175>;
            };
        };
        sensor {
            mh248-irq-gpio {
                rockchip,pins = <0x00000001 0x0000000c 0x00000000 0x00000178>;
                phandle = <0x000001af>;
            };
        };
        spk_ctl {
            spk-ctl-gpio {
                rockchip,pins = <0x00000001 0x0000001b 0x00000000 0x00000175>;
                phandle = <0x0000012a>;
            };
        };
        touchpad {
            touchpad_irq_gpio {
                rockchip,pins = <0x00000001 0x0000000a 0x00000000 0x00000178>;
                phandle = <0x0000012c>;
            };
        };
        touchpanel {
            touchpanel_pwr_en {
                rockchip,pins = <0x00000003 0x0000001c 0x00000000 0x0000017b>;
                phandle = <0x00000163>;
            };
        };
        usb {
            vcc5v0-host-en {
                rockchip,pins = <0x00000004 0x00000008 0x00000000 0x00000175 0x00000003 0x00000009 0x00000000 0x0000017b>;
                phandle = <0x000001b5>;
            };
        };
        keys {
            sw-lid {
                rockchip,pins = <0x00000001 0x0000000c 0x00000000 0x00000175>;
                phandle = <0x000001b6>;
            };
        };
        usb-typec {
            usbc0-int {
                rockchip,pins = <0x00000004 0x00000009 0x00000000 0x00000178>;
                phandle = <0x0000011c>;
            };
            usbc1-int {
                rockchip,pins = <0x00000004 0x0000000f 0x00000000 0x00000178>;
                phandle = <0x0000015e>;
            };
            typec5v-pwren {
                rockchip,pins = <0x00000003 0x00000008 0x00000000 0x00000175>;
            };
        };
        dp {
            dp0-hpd {
                rockchip,pins = <0x00000001 0x00000000 0x00000000 0x00000175>;
                phandle = <0x000000d3>;
            };
            dp1-hpd {
                rockchip,pins = <0x00000001 0x00000001 0x00000000 0x00000175>;
                phandle = <0x00000183>;
            };
        };
    };
    csi2-dphy3 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x0000017c>;
        status = "disabled";
    };
    csi2-dphy4 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x0000017c>;
        status = "disabled";
    };
    csi2-dphy5 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x0000017c>;
        status = "disabled";
    };
    rkcif-mipi-lvds4 {
        compatible = "rockchip,rkcif-mipi-lvds";
        rockchip,hw = <0x00000039>;
        iommus = <0x0000003a>;
        status = "disabled";
        phandle = <0x0000017d>;
    };
    rkcif-mipi-lvds4-sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x0000017d>;
        status = "disabled";
    };
    rkcif-mipi-lvds5 {
        compatible = "rockchip,rkcif-mipi-lvds";
        rockchip,hw = <0x00000039>;
        iommus = <0x0000003a>;
        status = "disabled";
        phandle = <0x0000017e>;
    };
    rkcif-mipi-lvds5-sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x0000017e>;
        status = "disabled";
    };
    usbdrd3_1 {
        compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
        clocks = <0x00000002 0x000001a6 0x00000002 0x000001a5 0x00000002 0x000001a4>;
        clock-names = "ref", "suspend", "bus";
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        status = "okay";
        usb@fc400000 {
            compatible = "snps,dwc3";
            reg = <0x00000000 0xfc400000 0x00000000 0x00400000>;
            interrupts = <0x00000000 0x000000dd 0x00000004>;
            power-domains = <0x00000047 0x0000001f>;
            resets = <0x00000002 0x000002a7>;
            reset-names = "usb3-otg";
            dr_mode = "otg";
            phys = <0x0000017f 0x00000180>;
            phy-names = "usb2-phy", "usb3-phy";
            phy_type = "utmi_wide";
            snps,dis_enblslpm_quirk;
            snps,dis-u2-freeclk-exists-quirk;
            snps,dis-del-phy-power-chg-quirk;
            snps,dis-tx-ipgap-linecheck-quirk;
            status = "disabled";
            usb-role-switch;
            port {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000181>;
                    phandle = <0x0000015f>;
                };
            };
        };
    };
    syscon@fd5b8000 {
        compatible = "rockchip,pcie30-phy-grf", "syscon";
        reg = <0x00000000 0xfd5b8000 0x00000000 0x00010000>;
        phandle = <0x000001a5>;
    };
    syscon@fd5c0000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x00000000 0xfd5c0000 0x00000000 0x00000100>;
        phandle = <0x000001a4>;
    };
    syscon@fd5cc000 {
        compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
        reg = <0x00000000 0xfd5cc000 0x00000000 0x00004000>;
        phandle = <0x000001a0>;
    };
    syscon@fd5d4000 {
        compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
        reg = <0x00000000 0xfd5d4000 0x00000000 0x00004000>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        phandle = <0x0000019f>;
        usb2-phy@4000 {
            compatible = "rockchip,rk3588-usb2phy";
            reg = <0x00004000 0x00000010>;
            interrupts = <0x00000000 0x0000018a 0x00000004>;
            resets = <0x00000002 0x000c0048 0x00000002 0x00000489>;
            reset-names = "phy", "apb";
            clocks = <0x00000002 0x000002b5>;
            clock-names = "phyclk";
            clock-output-names = "usb480m_phy1";
            #clock-cells = <0x00000000>;
            rockchip,usbctrl-grf = <0x00000057>;
            status = "okay";
            phandle = <0x00000126>;
            otg-port {
                #phy-cells = <0x00000000>;
                status = "okay";
                phandle = <0x0000017f>;
            };
        };
    };
    syscon@fd5e4000 {
        compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
        reg = <0x00000000 0xfd5e4000 0x00000000 0x00000100>;
        phandle = <0x0000019e>;
    };
    mipi4-csi2@fdd50000 {
        compatible = "rockchip,rk3588-mipi-csi2";
        reg = <0x00000000 0xfdd50000 0x00000000 0x00010000>;
        reg-names = "csihost_regs";
        interrupts = <0x00000000 0x00000097 0x00000004 0x00000000 0x00000098 0x00000004>;
        interrupt-names = "csi-intr1", "csi-intr2";
        clocks = <0x00000002 0x000001d3>;
        clock-names = "pclk_csi2host";
        resets = <0x00000002 0x00000328 0x00000002 0x00000338>;
        reset-names = "srst_csihost_p", "srst_csihost_vicap";
        status = "disabled";
    };
    mipi5-csi2@fdd60000 {
        compatible = "rockchip,rk3588-mipi-csi2";
        reg = <0x00000000 0xfdd60000 0x00000000 0x00010000>;
        reg-names = "csihost_regs";
        interrupts = <0x00000000 0x00000099 0x00000004 0x00000000 0x0000009a 0x00000004>;
        interrupt-names = "csi-intr1", "csi-intr2";
        clocks = <0x00000002 0x000001d4>;
        clock-names = "pclk_csi2host";
        resets = <0x00000002 0x00000329 0x00000002 0x00000339>;
        reset-names = "srst_csihost_p", "srst_csihost_vicap";
        status = "disabled";
    };
    spdif-tx@fddb8000 {
        compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
        reg = <0x00000000 0xfddb8000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000c6 0x00000004>;
        dmas = <0x000000cc 0x00000016>;
        dma-names = "tx";
        clock-names = "mclk", "hclk";
        clocks = <0x00000002 0x0000020f 0x00000002 0x0000020a>;
        assigned-clocks = <0x00000002 0x0000020b>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        power-domains = <0x00000047 0x00000019>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    i2s@fddc8000 {
        compatible = "rockchip,rk3588-i2s-tdm";
        reg = <0x00000000 0xfddc8000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000bc 0x00000004>;
        clocks = <0x00000002 0x00000201 0x00000002 0x000001fe>;
        clock-names = "mclk_tx", "hclk";
        assigned-clocks = <0x00000002 0x000001ff>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        dmas = <0x000000cd 0x00000016>;
        dma-names = "tx";
        power-domains = <0x00000047 0x00000019>;
        resets = <0x00000002 0x00000391>;
        reset-names = "tx-m";
        rockchip,playback-only;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    spdif-tx@fdde8000 {
        compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
        reg = <0x00000000 0xfdde8000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000c5 0x00000004>;
        dmas = <0x000000cc 0x00000008>;
        dma-names = "tx";
        clock-names = "mclk", "hclk";
        clocks = <0x00000002 0x0000025c 0x00000002 0x00000258>;
        assigned-clocks = <0x00000002 0x00000259>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        power-domains = <0x00000047 0x0000001a>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    i2s@fddf4000 {
        compatible = "rockchip,rk3588-i2s-tdm";
        reg = <0x00000000 0xfddf4000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000ba 0x00000004>;
        clocks = <0x00000002 0x0000024c 0x00000002 0x0000024c 0x00000002 0x00000252>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        assigned-clocks = <0x00000002 0x00000249>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        dmas = <0x000000cd 0x00000004>;
        dma-names = "tx";
        power-domains = <0x00000047 0x0000001a>;
        resets = <0x00000002 0x000003ef>;
        reset-names = "tx-m";
        rockchip,playback-only;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000001b0>;
    };
    i2s@fddf8000 {
        compatible = "rockchip,rk3588-i2s-tdm";
        reg = <0x00000000 0xfddf8000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000bb 0x00000004>;
        clocks = <0x00000002 0x0000023c 0x00000002 0x0000023c 0x00000002 0x00000238>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        assigned-clocks = <0x00000002 0x00000239>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        dmas = <0x000000cd 0x00000015>;
        dma-names = "rx";
        power-domains = <0x00000047 0x0000001a>;
        resets = <0x00000002 0x000003c3>;
        reset-names = "rx-m";
        rockchip,capture-only;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    i2s@fde00000 {
        compatible = "rockchip,rk3588-i2s-tdm";
        reg = <0x00000000 0xfde00000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000be 0x00000004>;
        clocks = <0x00000002 0x00000237 0x00000002 0x00000237 0x00000002 0x00000233>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        assigned-clocks = <0x00000002 0x00000234>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        dmas = <0x000000cd 0x00000018>;
        dma-names = "rx";
        power-domains = <0x00000047 0x0000001a>;
        resets = <0x00000002 0x00000417>;
        reset-names = "rx-m";
        rockchip,capture-only;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    spdif-rx@fde10000 {
        compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
        reg = <0x00000000 0xfde10000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000c8 0x00000004>;
        clocks = <0x00000002 0x00000260 0x00000002 0x0000025f>;
        clock-names = "mclk", "hclk";
        assigned-clocks = <0x00000002 0x00000260>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        dmas = <0x0000005b 0x00000016>;
        dma-names = "rx";
        power-domains = <0x00000047 0x0000001a>;
        resets = <0x00000002 0x000003ff>;
        reset-names = "spdifrx-m";
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    spdif-rx@fde18000 {
        compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
        reg = <0x00000000 0xfde18000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000c9 0x00000004>;
        clocks = <0x00000002 0x00000262 0x00000002 0x00000261>;
        clock-names = "mclk", "hclk";
        assigned-clocks = <0x00000002 0x00000262>;
        assigned-clock-parents = <0x00000002 0x00000005>;
        dmas = <0x0000005b 0x00000017>;
        dma-names = "rx";
        power-domains = <0x00000047 0x0000001a>;
        resets = <0x00000002 0x00000401>;
        reset-names = "spdifrx-m";
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
    };
    dp@fde60000 {
        compatible = "rockchip,rk3588-dp";
        reg = <0x00000000 0xfde60000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x000000a2 0x00000004>;
        clocks = <0x00000002 0x000001e7 0x00000002 0x000002cd 0x00000002 0x00000201 0x00000002 0x0000020d 0x00000004 0x00000002 0x000001eb>;
        clock-names = "apb", "aux", "i2s", "spdif", "hclk", "hdcp";
        assigned-clocks = <0x00000002 0x000002cd>;
        assigned-clock-rates = <0x00f42400>;
        resets = <0x00000002 0x00000389>;
        phys = <0x00000182>;
        power-domains = <0x00000047 0x00000019>;
        #sound-dai-cells = <0x00000001>;
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <0x00000183>;
        hpd-gpios = <0x000000d4 0x00000001 0x00000000>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000184>;
                    status = "disabled";
                    phandle = <0x000000b8>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000033>;
                    status = "disabled";
                    phandle = <0x000000be>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x00000185>;
                    status = "okay";
                    phandle = <0x000000c6>;
                };
            };
        };
    };
    hdmi@fdea0000 {
        compatible = "rockchip,rk3588-dw-hdmi";
        reg = <0x00000000 0xfdea0000 0x00000000 0x00020000>;
        interrupts = <0x00000000 0x000000ad 0x00000004 0x00000000 0x000000ae 0x00000004 0x00000000 0x000000af 0x00000004 0x00000000 0x000000b0 0x00000004 0x00000000 0x00000169 0x00000004>;
        clocks = <0x00000002 0x00000224 0x00000002 0x00000266 0x00000002 0x00000225 0x00000002 0x00000226 0x00000002 0x0000024c 0x00000002 0x00000274 0x00000002 0x00000275 0x00000002 0x00000276 0x00000002 0x00000277 0x00000005>;
        clock-names = "pclk", "hpd", "earc", "hdmitx_ref", "aud", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3", "hclk_vo1";
        resets = <0x00000002 0x000003d7 0x00000002 0x0000049d>;
        reset-names = "ref", "hdp";
        power-domains = <0x00000047 0x0000001a>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000186 0x00000187 0x00000188 0x00000189>;
        reg-io-width = <0x00000004>;
        rockchip,grf = <0x000000ae>;
        rockchip,vo1_grf = <0x000000b3>;
        phys = <0x000000b0>;
        phy-names = "hdmi";
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000001b1>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000018a>;
                    status = "disabled";
                    phandle = <0x000000ba>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000034>;
                    status = "disabled";
                    phandle = <0x000000c0>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x0000018b>;
                    status = "disabled";
                    phandle = <0x000000c8>;
                };
            };
        };
    };
    edp@fded0000 {
        compatible = "rockchip,rk3588-edp";
        reg = <0x00000000 0xfded0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000a4 0x00000004>;
        clocks = <0x00000002 0x00000214 0x00000002 0x00000213 0x00000002 0x00000215 0x00000005>;
        clock-names = "dp", "pclk", "spdif", "hclk";
        resets = <0x00000002 0x000003e4 0x00000002 0x000003e3>;
        reset-names = "dp", "apb";
        phys = <0x0000018c>;
        phy-names = "dp";
        power-domains = <0x00000047 0x0000001a>;
        rockchip,grf = <0x000000b3>;
        status = "disabled";
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000018d>;
                    status = "disabled";
                    phandle = <0x000000b9>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x0000018e>;
                    status = "disabled";
                    phandle = <0x000000bf>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x0000018f>;
                    status = "disabled";
                    phandle = <0x000000c7>;
                };
            };
        };
    };
    hdmirx-controller@fdee0000 {
        compatible = "rk3588,hdmirx-ctrler", "rockchip,hdmirx-ctrler";
        reg = <0x00000000 0xfdee0000 0x00000000 0x00006000>;
        reg-names = "hdmirx_regs";
        power-domains = <0x00000047 0x0000001a>;
        rockchip,grf = <0x000000ae>;
        rockchip,vo1_grf = <0x000000b3>;
        interrupts = <0x00000000 0x000000b1 0x00000004 0x00000000 0x000001b4 0x00000004 0x00000000 0x000000b3 0x00000004>;
        interrupt-names = "cec", "hdmi", "dma";
        clocks = <0x00000002 0x0000021a 0x00000002 0x0000021f 0x00000002 0x000002b2 0x00000002 0x0000021b 0x00000002 0x0000021c 0x00000005>;
        clock-names = "aclk", "audio", "cr_para", "pclk", "ref", "hclk_vo1";
        resets = <0x00000002 0x000003d9 0x00000002 0x000003da 0x00000002 0x000003db 0x00000002 0x000003b7>;
        reset-names = "rst_a", "rst_p", "rst_ref", "rst_biu";
        pinctrl-0 = <0x00000190 0x00000191 0x00000192 0x00000193>;
        pinctrl-names = "default";
        status = "disabled";
    };
    pcie@fe150000 {
        compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
        #address-cells = <0x00000003>;
        #size-cells = <0x00000002>;
        bus-range = <0x00000000 0x0000000f>;
        clocks = <0x00000002 0x0000014e 0x00000002 0x00000153 0x00000002 0x00000149 0x00000002 0x00000158 0x00000002 0x0000015e 0x00000002 0x00000183>;
        clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux", "pipe";
        device_type = "pci";
        interrupts = <0x00000000 0x00000107 0x00000004 0x00000000 0x00000106 0x00000004 0x00000000 0x00000105 0x00000004 0x00000000 0x00000104 0x00000004 0x00000000 0x00000103 0x00000004>;
        interrupt-names = "sys", "pmc", "msg", "legacy", "err";
        #interrupt-cells = <0x00000001>;
        interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
        interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000194 0x00000000 0x00000000 0x00000000 0x00000000 0x00000002 0x00000194 0x00000001 0x00000000 0x00000000 0x00000000 0x00000003 0x00000194 0x00000002 0x00000000 0x00000000 0x00000000 0x00000004 0x00000194 0x00000003>;
        linux,pci-domain = <0x00000000>;
        num-ib-windows = <0x00000010>;
        num-ob-windows = <0x00000010>;
        num-viewport = <0x00000008>;
        max-link-speed = <0x00000003>;
        msi-map = <0x00000000 0x00000195 0x00000000 0x00001000>;
        num-lanes = <0x00000004>;
        phys = <0x00000196>;
        phy-names = "pcie-phy";
        power-domains = <0x00000047 0x00000022>;
        ranges = <0x00000800 0x00000000 0xf0000000 0x00000000 0xf0000000 0x00000000 0x00100000 0x81000000 0x00000000 0xf0100000 0x00000000 0xf0100000 0x00000000 0x00100000 0x82000000 0x00000000 0xf0200000 0x00000000 0xf0200000 0x00000000 0x00e00000 0xc3000000 0x00000009 0x00000000 0x00000009 0x00000000 0x00000000 0x40000000>;
        reg = <0x00000000 0xfe150000 0x00000000 0x00010000 0x0000000a 0x40000000 0x00000000 0x00400000>;
        reg-names = "pcie-apb", "pcie-dbi";
        resets = <0x00000002 0x0000020d 0x00000002 0x0000021c>;
        reset-names = "pcie", "periph";
        rockchip,pipe-grf = <0x00000059>;
        status = "okay";
        reset-gpios = <0x0000011a 0x0000001e 0x00000000>;
        vpcie3v3-supply = <0x00000197>;
        legacy-interrupt-controller {
            interrupt-controller;
            #address-cells = <0x00000000>;
            #interrupt-cells = <0x00000001>;
            interrupt-parent = <0x00000001>;
            interrupts = <0x00000000 0x00000104 0x00000001>;
            phandle = <0x00000194>;
        };
    };
    pcie@fe160000 {
        compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
        #address-cells = <0x00000003>;
        #size-cells = <0x00000002>;
        bus-range = <0x00000010 0x0000001f>;
        clocks = <0x00000002 0x0000014f 0x00000002 0x00000154 0x00000002 0x0000014a 0x00000002 0x00000159 0x00000002 0x0000015f 0x00000002 0x00000184>;
        clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux", "pipe";
        device_type = "pci";
        interrupts = <0x00000000 0x00000102 0x00000004 0x00000000 0x00000101 0x00000004 0x00000000 0x00000100 0x00000004 0x00000000 0x000000ff 0x00000004 0x00000000 0x000000fe 0x00000004>;
        interrupt-names = "sys", "pmc", "msg", "legacy", "err";
        #interrupt-cells = <0x00000001>;
        interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
        interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000198 0x00000000 0x00000000 0x00000000 0x00000000 0x00000002 0x00000198 0x00000001 0x00000000 0x00000000 0x00000000 0x00000003 0x00000198 0x00000002 0x00000000 0x00000000 0x00000000 0x00000004 0x00000198 0x00000003>;
        linux,pci-domain = <0x00000001>;
        num-ib-windows = <0x00000010>;
        num-ob-windows = <0x00000010>;
        num-viewport = <0x00000008>;
        max-link-speed = <0x00000003>;
        msi-map = <0x00001000 0x00000195 0x00001000 0x00001000>;
        num-lanes = <0x00000002>;
        phys = <0x00000196>;
        phy-names = "pcie-phy";
        power-domains = <0x00000047 0x00000022>;
        ranges = <0x00000800 0x00000000 0xf1000000 0x00000000 0xf1000000 0x00000000 0x00100000 0x81000000 0x00000000 0xf1100000 0x00000000 0xf1100000 0x00000000 0x00100000 0x82000000 0x00000000 0xf1200000 0x00000000 0xf1200000 0x00000000 0x00e00000 0xc3000000 0x00000009 0x40000000 0x00000009 0x40000000 0x00000000 0x40000000>;
        reg = <0x00000000 0xfe160000 0x00000000 0x00010000 0x0000000a 0x40400000 0x00000000 0x00400000>;
        reg-names = "pcie-apb", "pcie-dbi";
        resets = <0x00000002 0x0000020e 0x00000002 0x0000021d>;
        reset-names = "pcie", "periph";
        rockchip,pipe-grf = <0x00000059>;
        status = "disabled";
        legacy-interrupt-controller {
            interrupt-controller;
            #address-cells = <0x00000000>;
            #interrupt-cells = <0x00000001>;
            interrupt-parent = <0x00000001>;
            interrupts = <0x00000000 0x000000ff 0x00000001>;
            phandle = <0x00000198>;
        };
    };
    pcie@fe170000 {
        compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
        #address-cells = <0x00000003>;
        #size-cells = <0x00000002>;
        bus-range = <0x00000020 0x0000002f>;
        clocks = <0x00000002 0x00000150 0x00000002 0x00000155 0x00000002 0x0000014b 0x00000002 0x0000015b 0x00000002 0x00000160 0x00000002 0x000002c4>;
        clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux", "pipe";
        device_type = "pci";
        interrupts = <0x00000000 0x000000f3 0x00000004 0x00000000 0x000000f2 0x00000004 0x00000000 0x000000f1 0x00000004 0x00000000 0x000000f0 0x00000004 0x00000000 0x000000ef 0x00000004>;
        interrupt-names = "sys", "pmc", "msg", "legacy", "err";
        #interrupt-cells = <0x00000001>;
        interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
        interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000199 0x00000000 0x00000000 0x00000000 0x00000000 0x00000002 0x00000199 0x00000001 0x00000000 0x00000000 0x00000000 0x00000003 0x00000199 0x00000002 0x00000000 0x00000000 0x00000000 0x00000004 0x00000199 0x00000003>;
        linux,pci-domain = <0x00000002>;
        num-ib-windows = <0x00000008>;
        num-ob-windows = <0x00000008>;
        num-viewport = <0x00000004>;
        max-link-speed = <0x00000002>;
        msi-map = <0x00002000 0x000000e3 0x00002000 0x00001000>;
        num-lanes = <0x00000001>;
        phys = <0x0000019a 0x00000002>;
        phy-names = "pcie-phy";
        ranges = <0x00000800 0x00000000 0xf2000000 0x00000000 0xf2000000 0x00000000 0x00100000 0x81000000 0x00000000 0xf2100000 0x00000000 0xf2100000 0x00000000 0x00100000 0x82000000 0x00000000 0xf2200000 0x00000000 0xf2200000 0x00000000 0x00e00000 0xc3000000 0x00000009 0x80000000 0x00000009 0x80000000 0x00000000 0x40000000>;
        reg = <0x00000000 0xfe170000 0x00000000 0x00010000 0x0000000a 0x40800000 0x00000000 0x00400000>;
        reg-names = "pcie-apb", "pcie-dbi";
        resets = <0x00000002 0x0000020f 0x00000002 0x0000021e>;
        reset-names = "pcie", "periph";
        rockchip,pipe-grf = <0x00000059>;
        status = "okay";
        reset-gpios = <0x0000011a 0x00000005 0x00000000>;
        legacy-interrupt-controller {
            interrupt-controller;
            #address-cells = <0x00000000>;
            #interrupt-cells = <0x00000001>;
            interrupt-parent = <0x00000001>;
            interrupts = <0x00000000 0x000000f0 0x00000001>;
            phandle = <0x00000199>;
        };
    };
    ethernet@fe1b0000 {
        compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
        reg = <0x00000000 0xfe1b0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x000000e3 0x00000004 0x00000000 0x000000e2 0x00000004>;
        interrupt-names = "macirq", "eth_wake_irq";
        rockchip,grf = <0x000000ae>;
        rockchip,php_grf = <0x00000059>;
        clocks = <0x00000002 0x00000144 0x00000002 0x00000145 0x00000002 0x00000167 0x00000002 0x0000016c 0x00000002 0x00000142>;
        clock-names = "stmmaceth", "clk_mac_ref", "pclk_mac", "aclk_mac", "ptp_ref";
        resets = <0x00000002 0x0000020a>;
        reset-names = "stmmaceth";
        power-domains = <0x00000047 0x00000021>;
        snps,mixed-burst;
        snps,tso;
        snps,axi-config = <0x0000019b>;
        snps,mtl-rx-config = <0x0000019c>;
        snps,mtl-tx-config = <0x0000019d>;
        status = "disabled";
        mdio {
            compatible = "snps,dwmac-mdio";
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
        };
        stmmac-axi-config {
            snps,wr_osr_lmt = <0x00000004>;
            snps,rd_osr_lmt = <0x00000008>;
            snps,blen = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000010 0x00000008 0x00000004>;
            phandle = <0x0000019b>;
        };
        rx-queues-config {
            snps,rx-queues-to-use = <0x00000002>;
            phandle = <0x0000019c>;
            queue0 {
            };
            queue1 {
            };
        };
        tx-queues-config {
            snps,tx-queues-to-use = <0x00000002>;
            phandle = <0x0000019d>;
            queue0 {
            };
            queue1 {
            };
        };
    };
    sata@fe220000 {
        compatible = "rockchip,rk-ahci", "snps,dwc-ahci";
        reg = <0x00000000 0xfe220000 0x00000000 0x00001000>;
        clocks = <0x00000002 0x00000172 0x00000002 0x0000016f 0x00000002 0x00000175 0x00000002 0x00000164 0x00000002 0x0000017f>;
        clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
        interrupts = <0x00000000 0x00000112 0x00000004>;
        interrupt-names = "hostc";
        phys = <0x0000019a 0x00000001>;
        phy-names = "sata-phy";
        ports-implemented = <0x00000001>;
        status = "disabled";
    };
    phy@fed70000 {
        compatible = "rockchip,rk3588-hdptx-phy";
        reg = <0x00000000 0xfed70000 0x00000000 0x00002000>;
        clocks = <0x00000002 0x000002b5 0x00000002 0x00000268>;
        clock-names = "ref", "apb";
        resets = <0x00000002 0x00000486 0x00000002 0x000c003f 0x00000002 0x000c0040 0x00000002 0x000c0041>;
        reset-names = "apb", "init", "cmn", "lane";
        rockchip,grf = <0x0000019e>;
        #phy-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x0000018c>;
    };
    hdmiphy@fed70000 {
        compatible = "rockchip,rk3588-hdptx-phy-hdmi";
        reg = <0x00000000 0xfed70000 0x00000000 0x00002000>;
        clocks = <0x00000002 0x000002b5 0x00000002 0x00000268>;
        clock-names = "ref", "apb";
        resets = <0x00000002 0x00000491 0x00000002 0x00000486 0x00000002 0x000c003f 0x00000002 0x000c0040 0x00000002 0x000c0041 0x00000002 0x0000048f 0x00000002 0x00000490>;
        reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";
        rockchip,grf = <0x0000019e>;
        #phy-cells = <0x00000000>;
        #clock-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000000b0>;
    };
    phy@fed90000 {
        compatible = "rockchip,rk3588-usbdp-phy";
        reg = <0x00000000 0xfed90000 0x00000000 0x00010000>;
        rockchip,u2phy-grf = <0x0000019f>;
        rockchip,usb-grf = <0x00000057>;
        rockchip,usbdpphy-grf = <0x000001a0>;
        rockchip,vo-grf = <0x0000016b>;
        clocks = <0x00000002 0x000002b6 0x00000002 0x00000280 0x00000002 0x0000026a 0x00000126>;
        clock-names = "refclk", "immortal", "pclk", "utmi";
        resets = <0x00000002 0x0000002f 0x00000002 0x00000030 0x00000002 0x00000031 0x00000002 0x00000032 0x00000002 0x00000484>;
        reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
        status = "okay";
        orientation-switch;
        svid = <0x0000ff01>;
        dp-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            phandle = <0x00000182>;
        };
        u3-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            phandle = <0x00000180>;
        };
        port {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            endpoint@0 {
                reg = <0x00000000>;
                remote-endpoint = <0x000001a1>;
                phandle = <0x00000160>;
            };
            endpoint@1 {
                reg = <0x00000001>;
                remote-endpoint = <0x000001a2>;
                phandle = <0x00000161>;
            };
        };
    };
    csi2-dphy1-hw@fedc8000 {
        compatible = "rockchip,rk3588-csi2-dphy-hw";
        reg = <0x00000000 0xfedc8000 0x00000000 0x00008000>;
        clocks = <0x00000002 0x0000010d>;
        clock-names = "pclk";
        resets = <0x00000002 0x00000019 0x00000002 0x00000018>;
        reset-names = "srst_csiphy1", "srst_p_csiphy1";
        rockchip,grf = <0x000001a3>;
        rockchip,sys_grf = <0x000000ae>;
        status = "disabled";
        phandle = <0x0000017c>;
    };
    phy@fee10000 {
        compatible = "rockchip,rk3588-naneng-combphy";
        reg = <0x00000000 0xfee10000 0x00000000 0x00000100>;
        #phy-cells = <0x00000001>;
        clocks = <0x00000002 0x000002be 0x00000002 0x00000186 0x00000002 0x00000166>;
        clock-names = "refclk", "apbclk", "phpclk";
        assigned-clocks = <0x00000002 0x000002be>;
        assigned-clock-rates = <0x05f5e100>;
        resets = <0x00000002 0x00020006 0x00000002 0x000004d7>;
        reset-names = "combphy-apb", "combphy";
        rockchip,pipe-grf = <0x00000059>;
        rockchip,pipe-phy-grf = <0x000001a4>;
        rockchip,pcie1ln-sel-bits = <0x00000100 0x00000000 0x00000000 0x00000000>;
        status = "okay";
        phandle = <0x0000019a>;
    };
    phy@fee80000 {
        compatible = "rockchip,rk3588-pcie3-phy";
        reg = <0x00000000 0xfee80000 0x00000000 0x00020000>;
        #phy-cells = <0x00000000>;
        clocks = <0x00000002 0x00000188>;
        clock-names = "pclk";
        resets = <0x00000002 0x0002000a>;
        reset-names = "phy";
        rockchip,pipe-grf = <0x00000059>;
        rockchip,phy-grf = <0x000001a5>;
        status = "okay";
        rockchip,pcie30-phymode = <0x00000004>;
        phandle = <0x00000196>;
    };
    cspmu@fd10c000 {
        compatible = "rockchip,cspmu";
        reg = <0x00000000 0xfd10c000 0x00000000 0x00001000 0x00000000 0xfd10d000 0x00000000 0x00001000 0x00000000 0xfd10e000 0x00000000 0x00001000 0x00000000 0xfd10f000 0x00000000 0x00001000 0x00000000 0xfd12c000 0x00000000 0x00001000 0x00000000 0xfd12d000 0x00000000 0x00001000 0x00000000 0xfd12e000 0x00000000 0x00001000 0x00000000 0xfd12f000 0x00000000 0x00001000>;
    };
    debug@fd104000 {
        compatible = "rockchip,debug";
        reg = <0x00000000 0xfd104000 0x00000000 0x00001000 0x00000000 0xfd105000 0x00000000 0x00001000 0x00000000 0xfd106000 0x00000000 0x00001000 0x00000000 0xfd107000 0x00000000 0x00001000 0x00000000 0xfd124000 0x00000000 0x00001000 0x00000000 0xfd125000 0x00000000 0x00001000 0x00000000 0xfd126000 0x00000000 0x00001000 0x00000000 0xfd127000 0x00000000 0x00001000>;
    };
    fiq-debugger {
        compatible = "rockchip,fiq-debugger";
        rockchip,serial-id = <0x00000002>;
        rockchip,wake-irq = <0x00000000>;
        rockchip,irq-mode-enable = <0x00000001>;
        rockchip,baudrate = <0x0016e360>;
        interrupts = <0x00000000 0x000001a7 0x00000008>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000146>;
        status = "okay";
    };
    ramoops@110000 {
        compatible = "ramoops";
        reg = <0x00000000 0x00110000 0x00000000 0x000f0000>;
        record-size = <0x00020000>;
        console-size = <0x00080000>;
        ftrace-size = <0x00000000>;
        pmsg-size = <0x00050000>;
    };
    reserved-memory {
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        cma {
            compatible = "shared-dma-pool";
            reusable;
            size = <0x00000000 0x00800000>;
            linux,cma-default;
        };
        drm-logo@00000000 {
            compatible = "rockchip,drm-logo";
            reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
            phandle = <0x0000002c>;
        };
        drm-cubic-lut@00000000 {
            compatible = "rockchip,drm-cubic-lut";
            reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
        };
    };
    backlight {
        compatible = "pwm-backlight";
        brightness-levels = <0x00000000 0x00000014 0x00000014 0x00000015 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018 0x00000018 0x00000019 0x00000019 0x0000001a 0x0000001a 0x0000001b 0x0000001b 0x0000001c 0x0000001c 0x0000001d 0x0000001d 0x0000001e 0x0000001e 0x0000001f 0x0000001f 0x00000020 0x00000020 0x00000021 0x00000021 0x00000022 0x00000022 0x00000023 0x00000023 0x00000024 0x00000024 0x00000025 0x00000025 0x00000026 0x00000026 0x00000027 0x00000028 0x00000029 0x0000002a 0x0000002b 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030 0x00000031 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f 0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047 0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004e 0x0000004f 0x00000050 0x00000051 0x00000052 0x00000053 0x00000054 0x00000055 0x00000056 0x00000057 0x00000058 0x00000059 0x0000005a 0x0000005b 0x0000005c 0x0000005d 0x0000005e 0x0000005f 0x00000060 0x00000061 0x00000062 0x00000063 0x00000064 0x00000065 0x00000066 0x00000067 0x00000068 0x00000069 0x0000006a 0x0000006b 0x0000006c 0x0000006d 0x0000006e 0x0000006f 0x00000070 0x00000071 0x00000072 0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000007a 0x0000007b 0x0000007c 0x0000007d 0x0000007e 0x0000007f 0x00000080 0x00000081 0x00000082 0x00000083 0x00000084 0x00000085 0x00000086 0x00000087 0x00000088 0x00000089 0x0000008a 0x0000008b 0x0000008c 0x0000008d 0x0000008e 0x0000008f 0x00000090 0x00000091 0x00000092 0x00000093 0x00000094 0x00000095 0x00000096 0x00000097 0x00000098 0x00000099 0x0000009a 0x0000009b 0x0000009c 0x0000009d 0x0000009e 0x0000009f 0x000000a0 0x000000a1 0x000000a2 0x000000a3 0x000000a4 0x000000a5 0x000000a6 0x000000a7 0x000000a8 0x000000a9 0x000000aa 0x000000ab 0x000000ac 0x000000ad 0x000000ae 0x000000af 0x000000b0 0x000000b1 0x000000b2 0x000000b3 0x000000b4 0x000000b5 0x000000b6 0x000000b7 0x000000b8 0x000000b9 0x000000ba 0x000000bb 0x000000bc 0x000000bd 0x000000be 0x000000bf 0x000000c0 0x000000c1 0x000000c2 0x000000c3 0x000000c4 0x000000c5 0x000000c6 0x000000c7 0x000000c8 0x000000c9 0x000000ca 0x000000cb 0x000000cc 0x000000cd 0x000000ce 0x000000cf 0x000000d0 0x000000d1 0x000000d2 0x000000d3 0x000000d4 0x000000d5 0x000000d6 0x000000d7 0x000000d8 0x000000d9 0x000000da 0x000000db 0x000000dc 0x000000dd 0x000000de 0x000000df 0x000000e0 0x000000e1 0x000000e2 0x000000e3 0x000000e4 0x000000e5 0x000000e6 0x000000e7 0x000000e8 0x000000e9 0x000000ea 0x000000eb 0x000000ec 0x000000ed 0x000000ee 0x000000ef 0x000000f0 0x000000f1 0x000000f2 0x000000f3 0x000000f4 0x000000f5 0x000000f6 0x000000f7 0x000000f8 0x000000f9 0x000000fa 0x000000fb 0x000000fc 0x000000fd 0x000000fe 0x000000ff>;
        default-brightness-level = <0x000000c8>;
        status = "okay";
        pwms = <0x000001a6 0x00000000 0x000061a8 0x00000000>;
        enable-gpios = <0x000001a7 0x00000004 0x00000000>;
        phandle = <0x000001ac>;
    };
    vcc12v-dcin {
        compatible = "regulator-fixed";
        regulator-name = "vcc12v_dcin";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x00b71b00>;
        regulator-max-microvolt = <0x00b71b00>;
        phandle = <0x000001a8>;
    };
    vcc5v0-sys {
        compatible = "regulator-fixed";
        regulator-name = "vcc5v0_sys";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x004c4b40>;
        regulator-max-microvolt = <0x004c4b40>;
        vin-supply = <0x000001a8>;
        phandle = <0x0000013c>;
    };
    vcc5v0-usbdcin {
        compatible = "regulator-fixed";
        regulator-name = "vcc5v0_usbdcin";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x004c4b40>;
        regulator-max-microvolt = <0x004c4b40>;
        vin-supply = <0x000001a8>;
        phandle = <0x000001b2>;
    };
    adc-keys {
        compatible = "adc-keys";
        io-channels = <0x000001a9 0x00000001>;
        io-channel-names = "buttons";
        keyup-threshold-microvolt = <0x001b7740>;
        poll-interval = <0x00000064>;
        vol-up-key {
            label = "volume up";
            linux,code = <0x00000073>;
            press-threshold-microvolt = <0x00004268>;
        };
    };
    es8326-sound {
        status = "okay";
        compatible = "rockchip,multicodecs-card";
        rockchip,card-name = "rockchip,es8326-sound";
        rockchip,codec-hp-det;
        rockchip,format = "i2s";
        rockchip,mclk-fs = <0x00000100>;
        rockchip,cpu = <0x000001aa>;
        rockchip,codec = <0x000001ab>;
    };
    panel-edp0 {
        compatible = "simple-panel";
        backlight = <0x000001ac>;
        enable-gpios = <0x000001a7 0x00000005 0x00000000>;
        power-supply = <0x000001ad>;
        prepare-delay-ms = <0x000000d2>;
        enable-delay-ms = <0x00000032>;
        unprepare-delay-ms = <0x000000a0>;
        disable-delay-ms = <0x00000078>;
        width-mm = <0x00000135>;
        height-mm = <0x000000ae>;
        panel-timing {
            clock-frequency = <0x098dfbe0>;
            hactive = <0x000008c0>;
            vactive = <0x00000578>;
            hfront-porch = <0x00000030>;
            hsync-len = <0x00000020>;
            hback-porch = <0x000000c8>;
            vfront-porch = <0x00000003>;
            vsync-len = <0x00000005>;
            vback-porch = <0x0000003c>;
            hsync-active = <0x00000000>;
            vsync-active = <0x00000000>;
            de-active = <0x00000000>;
            pixelclk-active = <0x00000000>;
        };
        port {
            endpoint {
                remote-endpoint = <0x000001ae>;
                phandle = <0x000000e0>;
            };
        };
    };
    hall-mh248 {
        compatible = "hall-mh248";
        pinctrl-names = "default";
        pinctrl-0 = <0x000001af>;
        irq-gpio = <0x000000d4 0x0000000c 0x00000008>;
        hall-active = <0x00000000>;
        status = "okay";
    };
    hdmi1-sound {
        status = "disabled";
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,mclk-fs = <0x00000080>;
        simple-audio-card,name = "rockchip,hdmi1";
        simple-audio-card,cpu {
            sound-dai = <0x000001b0>;
        };
        simple-audio-card,codec {
            sound-dai = <0x000001b1>;
        };
    };
    test-power {
        status = "okay";
    };
    vcc3v3-pcie30 {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_pcie30";
        regulator-min-microvolt = <0x00325aa0>;
        regulator-max-microvolt = <0x00325aa0>;
        enable-active-high;
        gpios = <0x000001a7 0x00000016 0x00000000>;
        startup-delay-us = <0x00001388>;
        vin-supply = <0x000001a8>;
        phandle = <0x00000197>;
    };
    vcc5v0-usb {
        compatible = "regulator-fixed";
        regulator-name = "vcc5v0_usb";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x004c4b40>;
        regulator-max-microvolt = <0x004c4b40>;
        vin-supply = <0x000001b2>;
        phandle = <0x000001b4>;
    };
    vcc3v3-lcd {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_lcd";
        vin-supply = <0x000001b3>;
        phandle = <0x000001ad>;
    };
    vcc5v0-host {
        compatible = "regulator-fixed";
        regulator-name = "vcc5v0_host";
        regulator-boot-on;
        regulator-always-on;
        regulator-min-microvolt = <0x004c4b40>;
        regulator-max-microvolt = <0x004c4b40>;
        enable-active-high;
        gpio = <0x0000011a 0x00000008 0x00000000>;
        vin-supply = <0x000001b4>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000001b5>;
        phandle = <0x00000058>;
    };
    gpio-keys {
        compatible = "gpio-keys";
        pinctrl-names = "default";
        pinctrl-0 = <0x000001b6>;
        hall-sensor {
            wakeup-event-action = <0x00000002>;
            wakeup-source;
            gpios = <0x000000d4 0x0000000c 0x00000001>;
            debounce-interval = <0x00000014>;
            label = "sw_lid";
            linux,input-type = <0x00000005>;
            linux,code = <0x00000000>;
        };
    };
};