#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Fri Apr  9 01:03:12 2021
# Process ID: 41744
# Current directory: G:/FPGA/AX7020/VivadoPro/Zynq7020_PS
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent54340 G:\FPGA\AX7020\VivadoPro\Zynq7020_PS\Zynq7020_PS.xpr
# Log file: G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/vivado.log
# Journal file: G:/FPGA/AX7020/VivadoPro/Zynq7020_PS\vivado.jou
#-----------------------------------------------------------
start_gui
open_project G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'F:/zhoutao/xilinx/Vivado/2017.4/data/ip'.
open_project: Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 844.820 ; gain = 128.184
update_compile_order -fileset sources_1
create_peripheral xilinx.com user steph_axi_pwm 1.0 -dir G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/StephenZhou_IP
add_peripheral_interface S00_AXI -interface_mode slave -axi_type lite [ipx::find_open_core xilinx.com:user:steph_axi_pwm:1.0]
generate_peripheral -driver -bfm_example_design -debug_hw_example_design [ipx::find_open_core xilinx.com:user:steph_axi_pwm:1.0]
write_peripheral [ipx::find_open_core xilinx.com:user:steph_axi_pwm:1.0]
set_property  ip_repo_paths  G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/StephenZhou_IP/steph_axi_pwm_1.0 [current_project]
update_ip_catalog -rebuild
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'g:/FPGA/AX7020/VivadoPro/Zynq7020_PS/StephenZhou_IP/steph_axi_pwm_1.0'.
open_bd_design {G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd}
Adding cell -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_50M
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_1
Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Successfully read diagram <design_1> from BD file <G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd>
open_bd_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 971.309 ; gain = 76.035
ipx::edit_ip_in_project -upgrade true -name steph_axi_pwm_v1_0_project -directory G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.tmp/steph_axi_pwm_v1_0_project g:/FPGA/AX7020/VivadoPro/Zynq7020_PS/StephenZhou_IP/steph_axi_pwm_1.0/component.xml
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'F:/zhoutao/xilinx/Vivado/2017.4/data/ip'.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'g:/FPGA/AX7020/VivadoPro/Zynq7020_PS/StephenZhou_IP/steph_axi_pwm_1.0'.
INFO: [IP_Flow 19-795] Syncing license key meta-data
ipx::edit_ip_in_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1015.516 ; gain = 16.781
update_compile_order -fileset sources_1
add_files -norecurse -copy_to g:/FPGA/AX7020/VivadoPro/Zynq7020_PS/StephenZhou_IP/steph_axi_pwm_1.0/src G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/StephenZhou_IP/steph_axi_pwm_1.0/hdl/stephen_axi_pwm.v
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
ipx::merge_project_changes files [ipx::current_core]
ipx::merge_project_changes hdl_parameters [ipx::current_core]
set_property core_revision 2 [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
close_project -delete
update_ip_catalog -rebuild -repo_path g:/FPGA/AX7020/VivadoPro/Zynq7020_PS/StephenZhou_IP/steph_axi_pwm_1.0
INFO: [IP_Flow 19-725] Reloaded user IP repository 'g:/FPGA/AX7020/VivadoPro/Zynq7020_PS/StephenZhou_IP/steph_axi_pwm_1.0'
startgroup
create_bd_cell -type ip -vlnv xilinx.com:user:steph_axi_pwm:1.0 steph_axi_pwm_0
endgroup
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "/ps7_0_axi_periph" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" }  [get_bd_intf_pins steph_axi_pwm_0/S00_AXI]
</steph_axi_pwm_0/S00_AXI/S00_AXI_reg> is being mapped into </processing_system7_0/Data> at <0x43C00000 [ 64K ]>
startgroup
make_bd_pins_external  [get_bd_pins steph_axi_pwm_0/pwm]
endgroup
regenerate_bd_layout -routing
set_property location {2 389 399} [get_bd_cells steph_axi_pwm_0]
regenerate_bd_layout -routing
save_bd_design
Wrote  : <G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd> 
Wrote  : <G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui> 
set_property location {2 575 252} [get_bd_cells processing_system7_0]
set_property location {1 162 558} [get_bd_cells processing_system7_0]
set_property location {1.5 686 561} [get_bd_cells rst_ps7_0_50M]
set_property location {2 691 607} [get_bd_cells rst_ps7_0_50M]
set_property location {3 1187 693} [get_bd_cells rst_ps7_0_50M]
set_property location {1.5 724 554} [get_bd_cells rst_ps7_0_50M]
set_property location {3 1238 490} [get_bd_cells ps7_0_axi_periph]
set_property location {3 1195 129} [get_bd_cells ps7_0_axi_periph]
regenerate_bd_layout -routing
set_property location {0.5 -175 362} [get_bd_cells processing_system7_0]
set_property location {2 301 299} [get_bd_cells ps7_0_axi_periph]
set_property location {3.5 930 189} [get_bd_cells axi_gpio_1]
set_property location {4 988 340} [get_bd_cells axi_gpio_0]
set_property location {4 985 486} [get_bd_cells steph_axi_pwm_0]
set_property location {2 244 597} [get_bd_cells rst_ps7_0_50M]
set_property location {2.5 614 602} [get_bd_cells rst_ps7_0_50M]
set_property location {1 -196 50} [get_bd_cells rst_ps7_0_50M]
set_property location {2 275 572} [get_bd_cells ps7_0_axi_periph]
set_property location {2.5 507 494} [get_bd_cells ps7_0_axi_periph]
set_property location {1.5 336 466} [get_bd_cells ps7_0_axi_periph]
regenerate_bd_layout -routing
save_bd_design
Wrote  : <G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui> 
generate_target all [get_files  G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd]
Wrote  : <G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd> 
VHDL Output written to : G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/synth/design_1.v
VHDL Output written to : G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/sim/design_1.v
VHDL Output written to : G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_50M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block steph_axi_pwm_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'g:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh
Generated Block Design Tcl file G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
Generated Hardware Definition File G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/synth/design_1.hwdef
generate_target: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1250.426 ; gain = 77.551
catch { config_ip_cache -export [get_ips -all design_1_xbar_0] }
catch { config_ip_cache -export [get_ips -all design_1_steph_axi_pwm_0_0] }
catch { config_ip_cache -export [get_ips -all design_1_auto_pc_0] }
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_auto_pc_0, cache-ID = af58add539c7abeb; cache size = 5.299 MB.
export_ip_user_files -of_objects [get_files G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd]
launch_runs -jobs 4 {design_1_xbar_0_synth_1 design_1_steph_axi_pwm_0_0_synth_1}
[Fri Apr  9 01:13:53 2021] Launched design_1_xbar_0_synth_1, design_1_steph_axi_pwm_0_0_synth_1...
Run output will be captured here:
design_1_xbar_0_synth_1: G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.runs/design_1_xbar_0_synth_1/runme.log
design_1_steph_axi_pwm_0_0_synth_1: G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.runs/design_1_steph_axi_pwm_0_0_synth_1/runme.log
export_simulation -of_objects [get_files G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd] -directory G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.ip_user_files/sim_scripts -ip_user_files_dir G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.ip_user_files -ipstatic_source_dir G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.ip_user_files/ipstatic -lib_map_path [list {modelsim=G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.cache/compile_simlib/modelsim} {questa=G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.cache/compile_simlib/questa} {riviera=G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.cache/compile_simlib/riviera} {activehdl=G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
generate_target all [get_files  G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd]
INFO: [BD 41-1637] Generated targets are already up-to-date for bd-design 'design_1' - hence not re-generating.
export_ip_user_files -of_objects [get_files G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd]
export_simulation -of_objects [get_files G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd] -directory G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.ip_user_files/sim_scripts -ip_user_files_dir G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.ip_user_files -ipstatic_source_dir G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.ip_user_files/ipstatic -lib_map_path [list {modelsim=G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.cache/compile_simlib/modelsim} {questa=G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.cache/compile_simlib/questa} {riviera=G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.cache/compile_simlib/riviera} {activehdl=G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr  9 01:16:01 2021] Launched synth_1...
Run output will be captured here: G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.runs/synth_1/runme.log
[Fri Apr  9 01:16:01 2021] Launched impl_1...
Run output will be captured here: G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.runs/impl_1/runme.log
open_bd_design {G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd}
file copy -force G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.runs/impl_1/design_1_wrapper.sysdef G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.sdk/design_1_wrapper.hdf

launch_sdk -workspace G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.sdk -hwspec G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-393] Launching SDK...
INFO: [Vivado 12-417] Running xsdk -workspace G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.sdk -hwspec G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-3157] SDK launch initiated. Please check console for any further messages.
exit
INFO: [Common 17-206] Exiting Vivado at Fri Apr  9 01:34:46 2021...