#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Fri Apr  9 01:03:12 2021
# Process ID: 41744
# Current directory: G:/FPGA/AX7020/VivadoPro/Zynq7020_PS
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent54340 G:\FPGA\AX7020\VivadoPro\Zynq7020_PS\Zynq7020_PS.xpr
# Log file: G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/vivado.log
# Journal file: G:/FPGA/AX7020/VivadoPro/Zynq7020_PS\vivado.jou
#-----------------------------------------------------------
start_gui
open_project G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.xpr
update_compile_order -fileset sources_1
create_peripheral xilinx.com user steph_axi_pwm 1.0 -dir G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/StephenZhou_IP
add_peripheral_interface S00_AXI -interface_mode slave -axi_type lite [ipx::find_open_core xilinx.com:user:steph_axi_pwm:1.0]
generate_peripheral -driver -bfm_example_design -debug_hw_example_design [ipx::find_open_core xilinx.com:user:steph_axi_pwm:1.0]
write_peripheral [ipx::find_open_core xilinx.com:user:steph_axi_pwm:1.0]
set_property  ip_repo_paths  G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/StephenZhou_IP/steph_axi_pwm_1.0 [current_project]
update_ip_catalog -rebuild
open_bd_design {G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd}
ipx::edit_ip_in_project -upgrade true -name steph_axi_pwm_v1_0_project -directory G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.tmp/steph_axi_pwm_v1_0_project g:/FPGA/AX7020/VivadoPro/Zynq7020_PS/StephenZhou_IP/steph_axi_pwm_1.0/component.xml
update_compile_order -fileset sources_1
add_files -norecurse -copy_to g:/FPGA/AX7020/VivadoPro/Zynq7020_PS/StephenZhou_IP/steph_axi_pwm_1.0/src G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/StephenZhou_IP/steph_axi_pwm_1.0/hdl/stephen_axi_pwm.v
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
ipx::merge_project_changes files [ipx::current_core]
ipx::merge_project_changes hdl_parameters [ipx::current_core]
set_property core_revision 2 [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
close_project -delete
update_ip_catalog -rebuild -repo_path g:/FPGA/AX7020/VivadoPro/Zynq7020_PS/StephenZhou_IP/steph_axi_pwm_1.0
startgroup
create_bd_cell -type ip -vlnv xilinx.com:user:steph_axi_pwm:1.0 steph_axi_pwm_0
endgroup
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "/ps7_0_axi_periph" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" }  [get_bd_intf_pins steph_axi_pwm_0/S00_AXI]
startgroup
make_bd_pins_external  [get_bd_pins steph_axi_pwm_0/pwm]
endgroup
regenerate_bd_layout -routing
set_property location {2 389 399} [get_bd_cells steph_axi_pwm_0]
regenerate_bd_layout -routing
save_bd_design
set_property location {2 575 252} [get_bd_cells processing_system7_0]
set_property location {1 162 558} [get_bd_cells processing_system7_0]
set_property location {1.5 686 561} [get_bd_cells rst_ps7_0_50M]
set_property location {2 691 607} [get_bd_cells rst_ps7_0_50M]
set_property location {3 1187 693} [get_bd_cells rst_ps7_0_50M]
set_property location {1.5 724 554} [get_bd_cells rst_ps7_0_50M]
set_property location {3 1238 490} [get_bd_cells ps7_0_axi_periph]
set_property location {3 1195 129} [get_bd_cells ps7_0_axi_periph]
regenerate_bd_layout -routing
set_property location {0.5 -175 362} [get_bd_cells processing_system7_0]
set_property location {2 301 299} [get_bd_cells ps7_0_axi_periph]
set_property location {3.5 930 189} [get_bd_cells axi_gpio_1]
set_property location {4 988 340} [get_bd_cells axi_gpio_0]
set_property location {4 985 486} [get_bd_cells steph_axi_pwm_0]
set_property location {2 244 597} [get_bd_cells rst_ps7_0_50M]
set_property location {2.5 614 602} [get_bd_cells rst_ps7_0_50M]
set_property location {1 -196 50} [get_bd_cells rst_ps7_0_50M]
set_property location {2 275 572} [get_bd_cells ps7_0_axi_periph]
set_property location {2.5 507 494} [get_bd_cells ps7_0_axi_periph]
set_property location {1.5 336 466} [get_bd_cells ps7_0_axi_periph]
regenerate_bd_layout -routing
save_bd_design
generate_target all [get_files  G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd]
catch { config_ip_cache -export [get_ips -all design_1_xbar_0] }
catch { config_ip_cache -export [get_ips -all design_1_steph_axi_pwm_0_0] }
catch { config_ip_cache -export [get_ips -all design_1_auto_pc_0] }
export_ip_user_files -of_objects [get_files G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd]
launch_runs -jobs 4 {design_1_xbar_0_synth_1 design_1_steph_axi_pwm_0_0_synth_1}
export_simulation -of_objects [get_files G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd] -directory G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.ip_user_files/sim_scripts -ip_user_files_dir G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.ip_user_files -ipstatic_source_dir G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.ip_user_files/ipstatic -lib_map_path [list {modelsim=G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.cache/compile_simlib/modelsim} {questa=G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.cache/compile_simlib/questa} {riviera=G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.cache/compile_simlib/riviera} {activehdl=G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
generate_target all [get_files  G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd]
export_ip_user_files -of_objects [get_files G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd]
export_simulation -of_objects [get_files G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd] -directory G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.ip_user_files/sim_scripts -ip_user_files_dir G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.ip_user_files -ipstatic_source_dir G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.ip_user_files/ipstatic -lib_map_path [list {modelsim=G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.cache/compile_simlib/modelsim} {questa=G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.cache/compile_simlib/questa} {riviera=G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.cache/compile_simlib/riviera} {activehdl=G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
wait_on_run impl_1
open_bd_design {G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.srcs/sources_1/bd/design_1/design_1.bd}
file copy -force G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.runs/impl_1/design_1_wrapper.sysdef G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.sdk/design_1_wrapper.hdf

launch_sdk -workspace G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.sdk -hwspec G:/FPGA/AX7020/VivadoPro/Zynq7020_PS/Zynq7020_PS.sdk/design_1_wrapper.hdf