a reference project for simulation/debug xilinx mig_axi_ddr3 with vcs/verdi
最近更新: 11个月前logic synthesis backend fork from berkeley-abc and try to sync. with its main line.
最近更新: 接近3年前logic synthesis tool for FPGA & ASIC design fork from github/yosysHQ/yosys.git and try to sync with main line.
最近更新: 接近3年前