export SIMULATOR=vcs
export TB_TOP=tb
export UVM_HOME=/opt/eda/uvm/uvm-1.2
export WAVES=fsdb
export dut_instance=tb.dut

proj_root=$(echo `pwd`)
export dv_root=${proj_root}/dv

uvm_test=flash_ctrl_base_test
uvm_test_seq=flash_ctrl_rw_vseq
seed=53897452866105699844496578546020618279480783630190420697915274837870846339955

make -f ./dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=${proj_root} run_cmd=./simv run_dir=. run_opts='+scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do ./dv/tools/sim.tcl +ntb_random_seed=2662001523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq' seed=${seed} sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=${uvm_test} uvm_test_seq=${uvm_test_seq}