module D(clk,rst,ina,inb,inc,outa,outb,outc,outa1,outa2,outb1,outb2,outc1,outc1,outc2)
input clk,rst;
input reg [7:0] ina,inb,inc;
output reg [7:0] outa,outb,outc;
output reg [7:0] outa1,outa2,outb1,outb2,outc1,outc1,outc2;
always@(posedge clk or negedge rst)
begin
if(!rst)
outa1<=8'b0;
else
outa1<=ina;
end
always@(posedge clk or negedge rst)
begin
if(!rst)
outa2<=8'b0;
else
outa2<=outa1;
end
always@(posedge clk or negedge rst)
begin
if(!rst)
outb1<=8'b0;
else
outb2<=inb;
end
always@(posedge clk or negedge rst)
begin
if(!rst)
outb2<=8'b0;
else
outb2<=outb1;
end
always@(posedge clk or negedge rst)
begin
if(!rst)
outc1<=8'b0;
else
outc1<=inc;
end
always@(posedge clk or negedge rst)
begin
if(!rst)
outc2<=8'b0;
else
outc2<=outc1;
end
assign outa=ina;
assign outb=inb;
assign outc=inc;
endmodule