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enable-virtio-device-mmio-access-and-wait-util-virti.patch 3.08 KB
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From 0a179313fde1f71a8a7520c3d3149aa2dc4e66b2 Mon Sep 17 00:00:00 2001
From: fangyi <eric.fangyi@huawei.com>
Date: Sat, 26 Oct 2024 15:32:02 +0800
Subject: [PATCH] enable virtio device mmio access and wait util virtio device
reset done
---
roms/seabios/src/hw/blockcmd.h | 2 +-
roms/seabiossrc/hw/virtio-pci.c | 32 +++++++++++++++++++++++++++-----
2 files changed, 28 insertions(+), 6 deletions(-)
diff --git a/roms/seabios/src/hw/blockcmd.h b/roms/seabios/src/hw/blockcmd.h
index f18543ed..1063e6ab 100644
--- a/roms/seabios/src/hw/blockcmd.h
+++ b/roms/seabios/src/hw/blockcmd.h
@@ -30,7 +30,7 @@ struct cdb_read_capacity {
struct cdbres_read_capacity {
u32 sectors;
u32 blksize;
-} PACKED;
+} __attribute__((aligned(4)));
#define CDB_CMD_TEST_UNIT_READY 0x00
#define CDB_CMD_INQUIRY 0x12
diff --git a/roms/seabios/src/hw/virtio-pci.c b/roms/seabios/src/hw/virtio-pci.c
index 89a4f505..5d7b8428 100644
--- a/roms/seabios/src/hw/virtio-pci.c
+++ b/roms/seabios/src/hw/virtio-pci.c
@@ -15,6 +15,7 @@
* See the COPYING file in the top-level directory.
*/
+#include "util.h" // msleep
#include "config.h" // CONFIG_DEBUG_LEVEL
#include "malloc.h" // free
#include "output.h" // dprintf
@@ -271,6 +272,10 @@ void vp_reset(struct vp_device *vp)
vp_read(&vp->common, virtio_mmio_cfg, irq_status);
} else if (vp->use_modern) {
vp_write(&vp->common, virtio_pci_common_cfg, device_status, 0);
+ dprintf(1, "vp start reset\n");
+ while (vp_get_status(vp) != 0)
+ msleep(2);
+ dprintf(1, "vp reset finished\n");
vp_read(&vp->isr, virtio_pci_isr, isr);
} else {
vp_write(&vp->legacy, virtio_pci_legacy, status, 0);
@@ -535,14 +540,31 @@ void vp_init_simple(struct vp_device *vp, struct pci_device *pci)
} else {
dprintf(1, "pci dev %pP using legacy (0.9.5) virtio mode\n", pci);
vp->legacy.bar = 0;
- vp->legacy.ioaddr = pci_enable_iobar(pci, PCI_BASE_ADDRESS_0);
- if (!vp->legacy.ioaddr)
- return;
- vp->legacy.mode = VP_ACCESS_IO;
+
+ /*
+ * Extend the legacy virtio interface to support MMIO bar which
+ * is required by SR-IOV.
+ */
+ addr = pci_config_readl(pci->bdf, PCI_BASE_ADDRESS_0);
+ if (addr & PCI_BASE_ADDRESS_SPACE_IO) {
+ dprintf(1, "legacy virtio: I/O BAR used\n");
+ vp->legacy.ioaddr = pci_enable_iobar(pci, PCI_BASE_ADDRESS_0);
+ if (!vp->legacy.ioaddr)
+ return;
+ vp->legacy.mode = VP_ACCESS_IO;
+ } else {
+ dprintf(1, "legacy virtio: MMIO BAR used\n");
+ vp->legacy.memaddr = pci_enable_membar(pci, PCI_BASE_ADDRESS_0);
+ if (!vp->legacy.memaddr)
+ return;
+ vp->legacy.mode = VP_ACCESS_MMIO;
+ }
}
- vp_reset(vp);
pci_enable_busmaster(pci);
+ dprintf(1, "pci dev %pP start reset\n", pci);
+ vp_reset(vp);
+ dprintf(1, "pci dev %pP finish reset\n", pci);
vp_set_status(vp, VIRTIO_CONFIG_S_ACKNOWLEDGE |
VIRTIO_CONFIG_S_DRIVER );
}
--
2.43.0
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