From 5a23eb0a55775901a4056e5f12fc97ad266b0ffe Mon Sep 17 00:00:00 2001
From: Xing Li <lixing@loongson.cn>
Date: Thu, 1 Dec 2022 15:46:52 +0800
Subject: [PATCH] LoongArch: Add missing opcode

Signed-off-by: Xing Li <lixing@loongson.cn>
---
 opcodes/loongarch-opc.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
index 2c543027..fb36e561 100644
--- a/opcodes/loongarch-opc.c
+++ b/opcodes/loongarch-opc.c
@@ -778,6 +778,18 @@ static struct loongarch_opcode loongarch_jmp_opcodes[] =
 };
 static struct loongarch_opcode loongarch_128vec_opcodes[] = {
 /* match,    mask,       name, format, macro, include, exclude, pinfo */
+{0x2c000000, 0xffc00000, "vld", "v0:5,r5:5,s10:12", 0, 0, 0, 0},
+{0x2c400000, 0xffc00000, "vst", "v0:5,r5:5,s10:12", 0, 0, 0, 0},
+{0x30100000, 0xfff80000, "vldrepl.d", "v0:5,r5:5,s10:9<<3", 0, 0, 0, 0},
+{0x30200000, 0xfff00000, "vldrepl.w", "v0:5,r5:5,s10:10<<2", 0, 0, 0, 0},
+{0x30400000, 0xffe00000, "vldrepl.h", "v0:5,r5:5,s10:11<<1", 0, 0, 0, 0},
+{0x30800000, 0xffc00000, "vldrepl.b", "v0:5,r5:5,s10:12", 0, 0, 0, 0},
+{0x31100000, 0xfff80000, "vstelm.d", "v0:5,r5:5,s10:8<<3,u18:1", 0, 0, 0, 0},
+{0x31200000, 0xfff00000, "vstelm.w", "v0:5,r5:5,s10:8<<2,u18:2", 0, 0, 0, 0},
+{0x31400000, 0xffe00000, "vstelm.h", "v0:5,r5:5,s10:8<<1,u18:3", 0, 0, 0, 0},
+{0x31800000, 0xffc00000, "vstelm.b", "v0:5,r5:5,s10:8,u18:4", 0, 0, 0, 0},
+{0x38400000, 0xffff8000, "vldx", "v0:5,r5:5,r10:5", 0, 0, 0, 0},
+{0x38440000, 0xffff8000, "vstx", "v0:5,r5:5,r10:5", 0, 0, 0, 0},
 {0x70000000, 0xffff8000, "vseq.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0},
 {0x70008000, 0xffff8000, "vseq.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0},
 {0x70010000, 0xffff8000, "vseq.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0},
@@ -1434,6 +1446,18 @@ static struct loongarch_opcode loongarch_128vec_opcodes[] = {
 
 static struct loongarch_opcode loongarch_256vec_opcodes[] = {
 /* match,    mask,       name, format, macro, include, exclude, pinfo */
+{0x2c800000, 0xffc00000, "xvld", "x0:5,r5:5,s10:12", 0, 0, 0, 0},
+{0x2cc00000, 0xffc00000, "xvst", "x0:5,r5:5,s10:12", 0, 0, 0, 0},
+{0x32100000, 0xfff80000, "xvldrepl.d", "x0:5,r5:5,s10:9<<3", 0, 0, 0, 0},
+{0x32200000, 0xfff00000, "xvldrepl.w", "x0:5,r5:5,s10:10<<2", 0, 0, 0, 0},
+{0x32400000, 0xffe00000, "xvldrepl.h", "x0:5,r5:5,s10:11<<1", 0, 0, 0, 0},
+{0x32800000, 0xffc00000, "xvldrepl.b", "x0:5,r5:5,s10:12", 0, 0, 0, 0},
+{0x33100000, 0xfff00000, "xvstelm.d", "x0:5,r5:5,s10:8<<3,u18:2", 0, 0, 0, 0},
+{0x33200000, 0xffe00000, "xvstelm.w", "x0:5,r5:5,s10:8<<2,u18:3", 0, 0, 0, 0},
+{0x33400000, 0xffc00000, "xvstelm.h", "x0:5,r5:5,s10:8<<1,u18:4", 0, 0, 0, 0},
+{0x33800000, 0xff800000, "xvstelm.b", "x0:5,r5:5,s10:8,u18:5", 0, 0, 0, 0},
+{0x38480000, 0xffff8000, "xvldx", "x0:5,r5:5,r10:5", 0, 0, 0, 0},
+{0x384c0000, 0xffff8000, "xvstx", "x0:5,r5:5,r10:5", 0, 0, 0, 0},
 {0x74000000, 0xffff8000, "xvseq.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0},
 {0x74008000, 0xffff8000, "xvseq.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0},
 {0x74010000, 0xffff8000, "xvseq.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0},
-- 
2.27.0