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打野/Verilog练习代码

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practice_24.6.26 (2).v 2.54 KB
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打野 提交于 2024-06-29 10:24 . 2024-6-29
//24-6-26 姜青羊
//z-scan设计-output raster-scan order ID in z-scan order
module z_scan (
sob,
zid,
zid_vld,
clk,
rstn
);
input wire sob;
input wire clk,rstn;
output reg zid_vld;
output reg [5:0] zid;
reg [5:0] ras_cnt;
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
zid_vld <= 1'b0;
ras_cnt <= 6'b000_000;
end
else if(sob) begin
zid_vld <= 1'b0;
ras_cnt <= 6'b111;
end
else if(zid_vld) begin
if(ras_cnt==6'b111_111)
ras_cnt <= ras_cnt+6'b_1;
end
end
always @(sob or zid or zid_vld or ras_cnt ) begin
case(ras_cnt)
6'd0: zid <= 6'd0;
6'd1: zid <= 6'd1;
6'd2: zid <= 6'd8;
6'd3: zid <= 6'd9;
6'd4: zid <= 6'd2;
6'd5: zid <= 6'd3;
6'd6: zid <= 6'd10;
6'd7: zid <= 6'd11;
6'd8: zid <= 6'd16;
6'd9: zid <= 6'd17;
6'd10: zid <= 6'd24;
6'd11: zid <= 6'd25;
6'd12: zid <= 6'd18;
6'd13: zid <= 6'd19;
6'd14: zid <= 6'd26;
6'd15: zid <= 6'd27;
6'd16: zid <= 6'd4;
6'd17: zid <= 6'd5;
6'd18: zid <= 6'd12;
6'd19: zid <= 6'd13;
6'd20: zid <= 6'd6;
6'd21: zid <= 6'd7;
6'd22: zid <= 6'd14;
6'd23: zid <= 6'd15;
6'd24: zid <= 6'd20;
6'd25: zid <= 6'd21;
6'd26: zid <= 6'd28;
6'd27: zid <= 6'd29;
6'd28: zid <= 6'd22;
6'd29: zid <= 6'd23;
6'd30: zid <= 6'd30;
6'd31: zid <= 6'd31;
6'd32: zid <= 6'd32;
6'd33: zid <= 6'd33;
6'd34: zid <= 6'd40;
6'd35: zid <= 6'd41;
6'd36: zid <= 6'd34;
6'd37: zid <= 6'd35;
6'd38: zid <= 6'd42;
6'd39: zid <= 6'd43;
6'd40: zid <= 6'd48;
6'd41: zid <= 6'd49;
6'd42: zid <= 6'd56;
6'd43: zid <= 6'd57;
6'd44: zid <= 6'd50;
6'd45: zid <= 6'd51;
6'd46: zid <= 6'd58;
6'd47: zid <= 6'd59;
6'd48: zid <= 6'd36;
6'd49: zid <= 6'd37;
6'd50: zid <= 6'd44;
6'd51: zid <= 6'd45;
6'd52: zid <= 6'd38;
6'd53: zid <= 6'd39;
6'd54: zid <= 6'd46;
6'd55: zid <= 6'd47;
6'd56: zid <= 6'd52;
6'd57: zid <= 6'd53;
6'd58: zid <= 6'd60;
6'd59: zid <= 6'd61;
6'd60: zid <= 6'd54;
6'd61: zid <= 6'd55;
6'd62: zid <= 6'd62;
6'd63: zid <= 6'd63;
endcase
end
endmodule
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