//2024-6-24 姜青羊
//日常练习
`timescale 1ns/10ps
module inv (
                    A,
                    Y
                );

input               A;
output              Y;

assign              Y=~A;
    
endmodule

//------testbench-----

module tb_inv ();

reg                  a;
wire                 y;

inv u_inv (
                    .A(a),
                    .Y(y)
                );

initial begin
                     a<=0;
                #10  a<=1;
                #10  a<=0;
                #10  a<=1;
                     $stop;
end

endmodule