//2024-3-5 姜青羊
//日常练习

module counter (
                        res,
                        clk,
                        y
                    );

input                   res,clk;
output[7:0]                y;

reg[7:0]                y;

always @(posedge clk or negedge res) begin
    if(!res)
       y<=0;
    else
       y<=y+1;
end
    
endmodule


//------testbench------

module tb_counter ();

reg                     res,clk;
wire[7:0]               y;

counter tb_counter (
                        .res(res),
                        .clk(clk),
                        .y(y)
                    );

initial begin
                        res<=0; clk<=0;
            #10         clk<=1;
            #3000       $stop;
end                    

always      #5          clk=~clk;
    
endmodule