//2024-1-27, ()
//nand_gate(Ÿϰ)

`timescale 1ns/10ps
module nand_gate (
                    A,
                    B,
                    Y
                    );

input               A,B;
output              Y;

assign              Y=~(A&B);

endmodule


//------testbench--------

module tb_nand_gate ();

reg                     a,b;
wire                    y;

initial begin
                        a<=0;b<=0;
                  #10   a<=0;b<=1;
                  #10   a<=1;b<=0;
                  #10   a<=1;b<=1;
                  #10   $stop;
end      



nand_gate u_nand_gate (
                       .A(a),
                       .B(b),
                       .Y(y)
                       );

   
endmodule