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/*
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6q.dtsi"
#include <dt-bindings/input/input.h>
/*---------------------------------------------------------------------------------------------------------------------
core
-----------------------------------------------------------------------------------------------------------------------*/
/ {
model = "Freescale i.MX6 Quad Sbc";
compatible = "fsl,imx6q-sbc", "fsl,imx6q";
};
/*---------------------------------------------------------------------------------------------------------------------
memory
-----------------------------------------------------------------------------------------------------------------------*/
/ {
memory {
reg = <0x10000000 0x40000000>;
};
};
/*---------------------------------------------------------------------------------------------------------------------
iomuxc
-----------------------------------------------------------------------------------------------------------------------*/
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pin: imx6qdl-sabreauto {
pinctrl_hog: hotgrp {
fsl,pins = <
/* CLKOUT[1:2] */
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x1b030
MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x1b030
/* RES_TOUCH_INTn */
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
/* CAP_TOUCH_INTn */
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000
/* CAP_TOUCH_RESETn */
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
>;
};
};
};
/*---------------------------------------------------------------------------------------------------------------------
regulators
-----------------------------------------------------------------------------------------------------------------------*/
/ {
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vdd_5v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "vdd_5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
vdd_2p8v: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "vdd_2p8v";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_3p3v_delay: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "vdd_3p3v_delay";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
usbotg_vbus: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "usbotg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
audio_avdd_3p3v: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "audio_avdd_3p3v";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
avdd_2p8v: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
regulator-name = "avdd_2p8v";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
vdd_1p5v: regulator@6 {
compatible = "regulator-fixed";
reg = <6>;
regulator-name = "vdd_1p5v";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
};
};
/*---------------------------------------------------------------------------------------------------------------------
uart
-----------------------------------------------------------------------------------------------------------------------*/
&pin {
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
/*---------------------------------------------------------------------------------------------------------------------
ethnet
-----------------------------------------------------------------------------------------------------------------------*/
&pin {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
fsl,magic-packet;
status = "okay";
};
/*---------------------------------------------------------------------------------------------------------------------
display
MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
-----------------------------------------------------------------------------------------------------------------------*/
&pin {
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x80000000
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};
pinctrl_hdmi_cec: hdmicecgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
>;
};
};
/ {
aliases {
mxcfb0 = &mxcfb0;
mxcfb1 = &mxcfb1;
mxcfb2 = &mxcfb2;
};
mxcfb0: fb@0 {
compatible = "fsl,mxc_sdc_fb";
disp_dev = "lcd";
interface_pix_fmt = "RGB24";
mode_str = "AT070";
default_bpp = <24>;
int_clk = <0>;
late_init = <0>;
status = "okay";
};
mxcfb1: fb@1 {
compatible = "fsl,mxc_sdc_fb";
disp_dev = "ldb";
interface_pix_fmt = "RGB666";
default_bpp = <16>;
int_clk = <0>;
late_init = <0>;
status = "okay";
};
mxcfb2: fb@2 {
compatible = "fsl,mxc_sdc_fb";
disp_dev = "hdmi";
interface_pix_fmt = "RGB24";
mode_str = "640x480M@50";
default_bpp = <24>;
int_clk = <0>;
late_init = <0>;
status = "okay";
};
lcd@0 {
compatible = "fsl,lcd";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
default_ifmt = "RGB24";
ipu_id = <0>;
disp_id = <0>;
status = "okay";
};
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
primary;
crtc = "ipu2-di0";
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "disable";
display-timings {
native-mode = <&timing1>;
timing1: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&dcic1 {
dcic_id = <0>;
dcic_mux = "dcic-hdmi";
status = "okay";
};
&hdmi_cec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_cec>;
status = "okay";
};
&hdmi_core {
ipu_id = <0>;
disp_id = <1>;
status = "okay";
};
&hdmi_audio {
status = "okay";
};
&hdmi_video {
fsl,phy_reg_vlev = <0x0294>;
fsl,phy_reg_cksymtx = <0x800d>;
status = "okay";
};
&i2c3 {
hdmi: edid@50 {
compatible = "fsl,imx6-hdmi-i2c";
reg = <0x50>;
};
};
/*---------------------------------------------------------------------------------------------------------------------
usb
-----------------------------------------------------------------------------------------------------------------------*/
&pin {
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>;
};
};
&usbh1 {
vbus-supply = <&vdd_5v>;
status = "disabled";
};
&usbotg {
vbus-supply = <&usbotg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
status = "okay";
};
/*-----------------------------------------------------------------------------------------------------------------------------------------
mmc
------------------------------------------------------------------------------------------------------------------------------------------*/
&pin {
pinctrl_sd1: sd1grp {
fsl,pins = <
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
>;
};
pinctrl_sd2: sd2grp {
fsl,pins = <
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
>;
};
pinctrl_sd3: sd3grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17071
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17071
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17071
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17071
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071
MX6QDL_PAD_SD3_RST__SD3_RESET 0x17071
>;
};
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd1>;
cd-gpios = <&gpio1 28 0>;
bus-width = <4>;
no-1-8-v;
keep-power-in-suspend;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd2>;
bus-width = <4>;
non-removable;
keep-power-in-suspend;
wl18xx-mode;
status = "disabled";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd3>;
bus-width = <8>;
keep-power-in-suspend;
status = "okay";
};
/*-----------------------------------------------------------------------------------------------------------------------------------------
i2c
------------------------------------------------------------------------------------------------------------------------------------------*/
&pin {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x40000039
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x40000039
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <100000>;
status = "okay";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
/*-----------------------------------------------------------------------------------------------------------------------------------------
spi
------------------------------------------------------------------------------------------------------------------------------------------*/
&pin {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
/* cs */
MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x80000000
>;
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio5 25 0>;
status = "okay";
};
/*-----------------------------------------------------------------------------------------------------------------------------------------
touchscreen
------------------------------------------------------------------------------------------------------------------------------------------*/
&ecspi1 {
tsc2046@0 {
compatible = "ti,tsc2046";
spi-max-frequency = <1500000>;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <4 0>;
pendown-gpio = <&gpio1 4 0>;
ti,vref-mv = <33000>;
ti,settle-delay-usec = <100>;
ti,x-plate-ohms = <1000>;
ti,x-max = <0xfff>;
ti,y-max = <0xfff>;
ti,debounce-max = <10>;
ti,debounce-tol = <3>;
ti,debounce-rep = <1>;
ti,keep-vref-on;
};
};
/*
&i2c1 {
captouch@0b {
compatible = "edt,ft5x06";
reg = <0x38>;
interrupt-parent= <&gpio7>;
interrupts = <13 0>;
int-gpios = <&gpio7 13 0>;
rst-gpios = <&gpio1 9 0>;
};
};
*/
/*-----------------------------------------------------------------------------------------------------------------------------------------
esai
------------------------------------------------------------------------------------------------------------------------------------------*/
&pin {
pinctrl_esai: esaigrp {
fsl,pins = <
MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x1b030
MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x1b030
>;
};
};
&esai {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esai>;
fsl,fifo-depth = <32>;
status = "okay";
};
/*-----------------------------------------------------------------------------------------------------------------------------------------
sata
------------------------------------------------------------------------------------------------------------------------------------------*/
&sata {
status = "okay";
};
/*-----------------------------------------------------------------------------------------------------------------------------------------
audio codec
------------------------------------------------------------------------------------------------------------------------------------------*/
&i2c3 {
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO2>;
VDDA-supply = <&audio_avdd_3p3v>;
VDDIO-supply = <&vdd_3p3v_delay>;
};
};
/*-----------------------------------------------------------------------------------------------------------------------------------------
sound
------------------------------------------------------------------------------------------------------------------------------------------*/
/ {
sound {
compatible = "fsl,imx-audio-sgtl5000";
model = "imx6q-sbc-sgtl5000";
cpu-dai = <&esai>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <4>;
};
sound-hdmi {
compatible = "fsl,imx6q-audio-hdmi",
"fsl,imx-audio-hdmi";
model = "imx-audio-hdmi";
hdmi-controller = <&hdmi_audio>;
};
};
/*-----------------------------------------------------------------------------------------------------------------------------------------
mipi_csi
------------------------------------------------------------------------------------------------------------------------------------------*/
&mipi_csi {
status = "okay";
ipu_id = <0>;
csi_id = <1>;
v_channel = <2>;
lanes = <2>;
};
/*-----------------------------------------------------------------------------------------------------------------------------------------
ov5640 csi
------------------------------------------------------------------------------------------------------------------------------------------*/
&pin {
pinctrl_ov5640: ov5640grp {
fsl,pins = <
/* rst */
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x80000000
/* pwd */
MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000
/* csi */
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
>;
};
};
&i2c3 {
ov5640@3c {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640>;
compatible = "ov564x";
reg = <0x3c>;
pwn-gpios = <&gpio7 11 1>;
rst-gpios = <&gpio1 7 0>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "csi_mclk";
csi_id = <0>;
mclk = <24000000>;
mclk_source = <0>;
};
};
/ {
v4l2_cap_0 {
compatible = "fsl,imx6q-v4l2-capture";
ipu_id = <0>;
csi_id = <0>;
mclk_source = <0>;
status = "okay";
};
};
/*-----------------------------------------------------------------------------------------------------------------------------------------
ov5640 mipi
------------------------------------------------------------------------------------------------------------------------------------------*/
&pin {
pinctrl_ov5640_mipi: ov5640_mipigrp {
fsl,pins = <
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000
MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x80000000
>;
};
};
&i2c1 {
ov5640_mipi: ov5640_mipi@3c {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640_mipi>;
compatible = "ovti,ov5640_mipi";
reg = <0x3c>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "csi_mclk";
DOVDD-supply = <&vdd_2p8v>;
AVDD-supply = <&avdd_2p8v>;
DVDD-supply = <&vdd_1p5v>;
pwn-gpios = <&gpio6 31 1>;
rst-gpios = <&gpio2 23 0>;
csi_id = <1>;
mclk = <24000000>;
mclk_source = <0>;
};
};
/ {
v4l2_cap_1 {
compatible = "fsl,imx6q-v4l2-capture";
ipu_id = <0>;
csi_id = <1>;
mclk_source = <0>;
status = "okay";
};
};
/*-----------------------------------------------------------------------------------------------------------------------------------------
can
------------------------------------------------------------------------------------------------------------------------------------------*/
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
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