library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram is
port (
       addr:in std_logic_vector(4 downto 0);
       wr:in std_logic;
       rd:in std_logic;
       cs:in std_logic;
       datain:in std_logic_vector(7 downto 0);
       dataout:out std_logic_vector(7 downto 0));
end ram;
architecture one of ram is
type memory is array(0 to 31)of std_logic_vector(7 downto 0);
signal data1:memory;
signal addr1:integer range 0 to 31;
begin
      addr1<=conv_integer(addr);
      process(wr,cs,addr1,data1,datain)
      begin
        if cs='0' and wr='1' then
 	  data1(addr1)<=datain;
        end if;
      end process;
      process(rd,cs,addr1,data1)
      begin 
      if cs='0' and rd='1' then
	dataout<=data1(addr1);
      else
	dataout<=(others=>'Z');
      end if;
      end process;
end one;