From 6f08530cae5de66fabfae4cb29729a18b0e86365 Mon Sep 17 00:00:00 2001
From: Yixing Liu <liuyixing1@huawei.com>
Date: Mon, 17 Apr 2023 09:48:10 +0800
Subject: [PATCH 2/2] libhns: Add support for SVE Direct WQE

driver inclusion
category: bugfix
bugzilla: https://gitee.com/src-openeuler/rdma-core/issues/I6VLLM

---------------------------------------------------------------

Some Kunpeng SoCs do not support the DWQE through NEON
instructions. In this case, the IO path works normally,
but the performance will deteriorate.

For these SoCs that do not support NEON DWQE, they support
DWQE through SVE instructions. This patch supports SVE DWQE
to guarantee the performance of these SoCs. In addition, in
this scenario, DWQE only supports acceleration through SVE's
ldr and str instructions. Other load and store instructions
also cause performance degradation.

Signed-off-by: Yixing Liu <liuyixing1@huawei.com>
Reviewed-by: Yangyang Li <liyangyang20@huawei.com>
---
 CMakeLists.txt                   |  1 +
 buildlib/RDMA_EnableCStd.cmake   | 17 +++++++++++++++++
 providers/hns/CMakeLists.txt     |  5 +++++
 providers/hns/hns_roce_u_hw_v2.c | 21 ++++++++++++++++++++-
 4 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 787c8be..bc4437b 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -399,6 +399,7 @@ if (NOT HAVE_SPARSE)
 endif()
 
 RDMA_Check_SSE(HAVE_TARGET_SSE)
+RDMA_Check_SVE(HAVE_TARGET_SVE)
 
 # Enable development support features
 # Prune unneeded shared libraries during linking
diff --git a/buildlib/RDMA_EnableCStd.cmake b/buildlib/RDMA_EnableCStd.cmake
index 3c42824..2b56f42 100644
--- a/buildlib/RDMA_EnableCStd.cmake
+++ b/buildlib/RDMA_EnableCStd.cmake
@@ -127,3 +127,20 @@ int main(int argc, char *argv[])
   endif()
   set(${TO_VAR} "${HAVE_TARGET_SSE}" PARENT_SCOPE)
 endFunction()
+
+function(RDMA_Check_SVE TO_VAR)
+  set(SVE_CHECK_PROGRAM "
+int main(int argc, char *argv[])
+{
+	return 0;
+}
+")
+
+  RDMA_Check_C_Compiles(HAVE_TARGET_SVE "${SVE_CHECK_PROGRAM}" "-march=armv8.2-a+sve")
+  if(NOT HAVE_TARGET_SVE)
+    message("SVE is not supported")
+  else()
+    set(SVE_FLAGS "-march=armv8.2-a+sve" PARENT_SCOPE)
+  endif()
+  set(${TO_VAR} "${HAVE_TARGET_SVE}" PARENT_SCOPE)
+endFunction()
\ No newline at end of file
diff --git a/providers/hns/CMakeLists.txt b/providers/hns/CMakeLists.txt
index 160e1ff..ef031a8 100644
--- a/providers/hns/CMakeLists.txt
+++ b/providers/hns/CMakeLists.txt
@@ -11,4 +11,9 @@ publish_headers(infiniband
 	hnsdv.h
 )
 
+if (HAVE_TARGET_SVE)
+  add_definitions("-DHNS_SVE")
+  set_source_files_properties(hns_roce_u_hw_v2.c PROPERTIES COMPILE_FLAGS "${SVE_FLAGS}")
+endif()
+
 rdma_pkg_config("hns" "libibverbs" "${CMAKE_THREAD_LIBS_INIT}")
diff --git a/providers/hns/hns_roce_u_hw_v2.c b/providers/hns/hns_roce_u_hw_v2.c
index d0067d3..a49b50d 100644
--- a/providers/hns/hns_roce_u_hw_v2.c
+++ b/providers/hns/hns_roce_u_hw_v2.c
@@ -321,6 +321,22 @@ static void hns_roce_write512(uint64_t *dest, uint64_t *val)
 	mmio_memcpy_x64(dest, val, sizeof(struct hns_roce_rc_sq_wqe));
 }
 
+#if defined(HNS_SVE)
+static void hns_roce_sve_write512(uint64_t *dest, uint64_t *val)
+{
+	asm volatile(
+		"ldr z0, [%0]\n"
+		"str z0, [%1]\n"
+		::"r" (val), "r"(dest):"cc", "memory"
+	);
+}
+#else
+static void hns_roce_sve_write512(uint64_t *dest, uint64_t *val)
+{
+	return;
+}
+#endif
+
 static void hns_roce_write_dwqe(struct hns_roce_qp *qp, void *wqe)
 {
 	struct hns_roce_rc_sq_wqe *rc_sq_wqe = wqe;
@@ -337,7 +353,10 @@ static void hns_roce_write_dwqe(struct hns_roce_qp *qp, void *wqe)
 	hr_reg_write(rc_sq_wqe, RCWQE_DB_SL_H, qp->sl >> HNS_ROCE_SL_SHIFT);
 	hr_reg_write(rc_sq_wqe, RCWQE_WQE_IDX, qp->sq.head);
 
-	hns_roce_write512(qp->sq.db_reg, wqe);
+	if (qp->flags & HNS_ROCE_QP_CAP_SVE_DIRECT_WQE)
+		hns_roce_sve_write512(qp->sq.db_reg, wqe);
+	else
+		hns_roce_write512(qp->sq.db_reg, wqe);
 }
 
 static void update_cq_db(struct hns_roce_context *ctx, struct hns_roce_cq *cq)
-- 
2.25.1