diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/gui_handlers.wdf b/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/gui_handlers.wdf index 5a657a4e55c378842d809f8481758c50e70cec3c..b4003371a9d4bb5f16e2dd46c67d61fa0a1b8280 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/gui_handlers.wdf +++ b/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/gui_handlers.wdf @@ -1,16 +1,18 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:616273747261637466696c65766965775f72656c6f6164:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:33:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:35:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f70656e5f6d657373616765735f76696577:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3135:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3234:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3230:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763636f6566696c656469616c6f675f73617665:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763636f6566696c657769646765745f62726f777365:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763636f6566696c657769646765745f62726f777365:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763636f6566696c657769646765745f65646974:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763697073796d626f6c5f73686f775f64697361626c65645f706f727473:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6f70656e66696c65616374696f6e5f6f6b:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f627265616b:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72756e:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72756e5f616c6c:31:00:00 @@ -20,11 +22,11 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:3130:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f70726f70657274696573:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72646976696577735f77617665666f726d5f766965776572:3331:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6c69766572756e666f72636f6d705f737065636966795f74696d655f616e645f756e697473:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6f626a6563747370616e656c5f73696d756c6174696f6e5f6f626a656374735f747265655f7461626c65:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e73636f70657370616e656c5f73696d756c6174655f73636f70655f7461626c65:3435:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6e616d65747265655f77617665666f726d5f6e616d655f74726565:3533:00:00 -eof:1473047586 +eof:575768204 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/java_command_handlers.wdf b/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/java_command_handlers.wdf index e4b6a16ce5d24f94a4bf95c66992a1888a288dae..de5798e4b59c3b485b92690e161f60a40b88f1ad 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/java_command_handlers.wdf +++ b/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/java_command_handlers.wdf @@ -1,10 +1,11 @@ version:1 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697470726f70657274696573:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:34:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:31:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e627265616b:31:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72656c61756e6368:3131:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:3135:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e616c6c:31:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e666f7274696d65:34:00:00 -eof:1008766096 +eof:2611831502 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/project.wpc b/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/project.wpc index 87638c79031b151c6261ee4677e130ffa4a95c31..8bb26a8d61dd37b65fc205861341a3ca49f5bf74 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/project.wpc +++ b/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/project.wpc @@ -1,9 +1,8 @@ version:1 09090909:0 -0909090909fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0f:0 0909090909fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0f:0 -0909090909fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0f:0 +0909090909ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0f:0 26262626:0 -2626262626ffffffffffffffffffffffffffffffffffff0f:0 -6d6f64655f636f756e7465727c4755494d6f6465:59 +2626262626ffffffffffffffffffffffffffffffffffffffffffffffffffffff0f:0 +6d6f64655f636f756e7465727c4755494d6f6465:60 eof: diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/synthesis.wdf b/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/synthesis.wdf index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..e55186b838e5f9d5d9c982458ec61bebc0070468 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/synthesis.wdf +++ b/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/synthesis.wdf @@ -0,0 +1,39 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b333235746666673930302d32:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:696e73745f726f6d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:6f75745f6f665f636f6e74657874:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a353873:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313136372e3234324d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3836342e3438304d42:00:00 +eof:3431598763 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/webtalk_pa.xml b/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/webtalk_pa.xml index d41a1b5ad28d8a21db6b80d7671290121d8b6210..f23c4ff90441efea59a7c309ec64cae065682270 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/webtalk_pa.xml +++ b/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -18,7 +18,8 @@ This means code written to parse this file will need to be revisited each subseq - + + @@ -28,17 +29,19 @@ This means code written to parse this file will need to be revisited each subseq - - + + - + + - + + @@ -48,7 +51,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -57,9 +60,9 @@ This means code written to parse this file will need to be revisited each subseq - + - +
diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/xsim.wdf b/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/xsim.wdf index 50afb2c7aebfafa7cc5fa823be2031ae4ebbf3af..51d5206f7011f2f0764fb661278617e58456141a 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/xsim.wdf +++ b/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/xsim.wdf @@ -1,4 +1,4 @@ version:1 -7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 -eof:241934075 +eof:2427094519 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/ip/inst_rom/inst_rom_stub.v b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/ip/inst_rom/inst_rom_stub.v new file mode 100644 index 0000000000000000000000000000000000000000..9f3d3e24dc01139eb73287061a395e1bc40c1d24 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/ip/inst_rom/inst_rom_stub.v @@ -0,0 +1,23 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +// Date : Thu Nov 11 21:46:31 2021 +// Host : DESKTOP-B2469GJ running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v +// Design : inst_rom +// Purpose : Stub declaration of top-level module interface +// Device : xc7k325tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2019.2" *) +module inst_rom(clka, ena, addra, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,addra[10:0],douta[31:0]" */; + input clka; + input ena; + input [10:0]addra; + output [31:0]douta; +endmodule diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/ip/inst_rom/inst_rom_stub.vhdl b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/ip/inst_rom/inst_rom_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..7d1db92f3cde788c798f0c856ba49ced8a2c25b4 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/ip/inst_rom/inst_rom_stub.vhdl @@ -0,0 +1,33 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +-- Date : Thu Nov 11 21:46:31 2021 +-- Host : DESKTOP-B2469GJ running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub +-- F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl +-- Design : inst_rom +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k325tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity inst_rom is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end inst_rom; + +architecture stub of inst_rom is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,addra[10:0],douta[31:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2019.2"; +begin +end; diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/README.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/README.txt index e9ef368a594a5ccad025fc9144bdf3f34a3be343..1e8162ec8558b5c775f512e0c95f041ca5aa2ea7 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/README.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu Nov 11 21:00:13 +0800 2021 +# Generated by export_simulation on Thu Nov 11 21:45:26 +0800 2021 # ################################################################################ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/compile.do b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/compile.do index 5676c20fd61e17cbba568e6dcbe67ff006857c21..fd60353e86abfe99997e130aec9e7f4f48d70cfa 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/compile.do +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/compile.do @@ -10,11 +10,11 @@ vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 vmap xil_defaultlib activehdl/xil_defaultlib vlog -work xpm -sv2k12 \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -93 \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work blk_mem_gen_v8_4_4 -v2k5 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/file_info.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/file_info.txt index 1d40a9ad4cd07cc5a6026ea76297f7065923d11a..428eee3a8a326bb209ec8e4e77578adc05165446 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/file_info.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, inst_rom.v,verilog,xil_defaultlib,../../../../MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/inst_rom.sh b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/inst_rom.sh index d11f1f04b9459eca4680f5a7d2ac94531642c671..169573836a152e01dadd191cccc9bb70db44166c 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/inst_rom.sh +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/inst_rom.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu Nov 11 21:00:13 +0800 2021 +# Generated by Vivado on Thu Nov 11 21:45:26 +0800 2021 # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -96,7 +96,7 @@ map_setup_file() if [[ ($1 != "") ]]; then lib_map_path="$1" else - lib_map_path="G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/compile_simlib/activehdl" + lib_map_path="F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/compile_simlib/activehdl" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/README.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/README.txt index fd15c1c2d8595e427dd4054cb0036de652d16deb..318469838bd20d3d484c4d7704a41e1e902fb05b 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/README.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu Nov 11 21:00:13 +0800 2021 +# Generated by export_simulation on Thu Nov 11 21:45:26 +0800 2021 # ################################################################################ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/file_info.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/file_info.txt index 1d40a9ad4cd07cc5a6026ea76297f7065923d11a..428eee3a8a326bb209ec8e4e77578adc05165446 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/file_info.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, inst_rom.v,verilog,xil_defaultlib,../../../../MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/inst_rom.sh b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/inst_rom.sh index aeb6fce607109bc5b84758ffe73db8aabced2b68..954b0b23660655e328e00efda7d560d57d2afd54 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/inst_rom.sh +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/inst_rom.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu Nov 11 21:00:13 +0800 2021 +# Generated by Vivado on Thu Nov 11 21:45:26 +0800 2021 # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/run.f b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/run.f index ced7e8d051886244ba743714d4d67452e93dc046..26309e5d58d9ed705a86d60e6d1beaed78612ec8 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/run.f +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/run.f @@ -1,9 +1,9 @@ -makelib ies_lib/xpm -sv \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ -endlib -makelib ies_lib/xpm \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ -endlib -makelib ies_lib/blk_mem_gen_v8_4_4 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/README.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/README.txt index e9ef368a594a5ccad025fc9144bdf3f34a3be343..1e8162ec8558b5c775f512e0c95f041ca5aa2ea7 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/README.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu Nov 11 21:00:13 +0800 2021 +# Generated by export_simulation on Thu Nov 11 21:45:26 +0800 2021 # ################################################################################ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/compile.do b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/compile.do index 52bb69bcc11cd918fcebec28e5c8773e54c9126d..359f0912d02cd50bc716edbe80dde661a72ab365 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/compile.do +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/compile.do @@ -10,11 +10,11 @@ vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib vlog -work xpm -64 -incr -sv \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -64 -93 \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work blk_mem_gen_v8_4_4 -64 -incr \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/file_info.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/file_info.txt index 1d40a9ad4cd07cc5a6026ea76297f7065923d11a..428eee3a8a326bb209ec8e4e77578adc05165446 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/file_info.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, inst_rom.v,verilog,xil_defaultlib,../../../../MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/inst_rom.sh b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/inst_rom.sh index 868aa0efc12ea08c80b0d5fe605cf3fefb40e172..aa006cb64cc88e25c6106e105acb81fac9cfde75 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/inst_rom.sh +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/inst_rom.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu Nov 11 21:00:13 +0800 2021 +# Generated by Vivado on Thu Nov 11 21:45:26 +0800 2021 # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -98,7 +98,7 @@ copy_setup_file() if [[ ($1 != "") ]]; then lib_map_path="$1" else - lib_map_path="G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/compile_simlib/modelsim" + lib_map_path="F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/compile_simlib/modelsim" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/README.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/README.txt index e9ef368a594a5ccad025fc9144bdf3f34a3be343..1e8162ec8558b5c775f512e0c95f041ca5aa2ea7 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/README.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu Nov 11 21:00:13 +0800 2021 +# Generated by export_simulation on Thu Nov 11 21:45:26 +0800 2021 # ################################################################################ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/compile.do b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/compile.do index 080440532e9b15ef289adb69cd594b37f7c26a03..f80f561d26ec2b0c0a1c2fb1fb51497992a16242 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/compile.do +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/compile.do @@ -10,11 +10,11 @@ vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 vmap xil_defaultlib questa_lib/msim/xil_defaultlib vlog -work xpm -64 -sv \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -64 -93 \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work blk_mem_gen_v8_4_4 -64 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/file_info.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/file_info.txt index 1d40a9ad4cd07cc5a6026ea76297f7065923d11a..428eee3a8a326bb209ec8e4e77578adc05165446 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/file_info.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, inst_rom.v,verilog,xil_defaultlib,../../../../MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/inst_rom.sh b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/inst_rom.sh index 1ef0c576d2665c9b4656d1070f5c0a7c359cb5b9..d90fe57ad18a98e160a0ed5855ebe098c82cdd7c 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/inst_rom.sh +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/inst_rom.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu Nov 11 21:00:13 +0800 2021 +# Generated by Vivado on Thu Nov 11 21:45:26 +0800 2021 # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -105,7 +105,7 @@ copy_setup_file() if [[ ($1 != "") ]]; then lib_map_path="$1" else - lib_map_path="G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/compile_simlib/questa" + lib_map_path="F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/compile_simlib/questa" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/README.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/README.txt index e9ef368a594a5ccad025fc9144bdf3f34a3be343..1e8162ec8558b5c775f512e0c95f041ca5aa2ea7 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/README.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu Nov 11 21:00:13 +0800 2021 +# Generated by export_simulation on Thu Nov 11 21:45:26 +0800 2021 # ################################################################################ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/compile.do b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/compile.do index 890235985cf51bdfd675ff68a7ed7845c772898d..64e39660fb82a01e5ce669979e46f7bf62564c42 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/compile.do +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/compile.do @@ -10,11 +10,11 @@ vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 vmap xil_defaultlib riviera/xil_defaultlib vlog -work xpm -sv2k12 \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -93 \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work blk_mem_gen_v8_4_4 -v2k5 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/file_info.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/file_info.txt index 1d40a9ad4cd07cc5a6026ea76297f7065923d11a..428eee3a8a326bb209ec8e4e77578adc05165446 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/file_info.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, inst_rom.v,verilog,xil_defaultlib,../../../../MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/inst_rom.sh b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/inst_rom.sh index fe61b39c82787c492352fea691cc60fc5e8ac93d..d104b3f313be794af7548b36f24b469919b1b76f 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/inst_rom.sh +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/inst_rom.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu Nov 11 21:00:13 +0800 2021 +# Generated by Vivado on Thu Nov 11 21:45:26 +0800 2021 # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -96,7 +96,7 @@ map_setup_file() if [[ ($1 != "") ]]; then lib_map_path="$1" else - lib_map_path="G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/compile_simlib/riviera" + lib_map_path="F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/compile_simlib/riviera" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/README.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/README.txt index e9ef368a594a5ccad025fc9144bdf3f34a3be343..1e8162ec8558b5c775f512e0c95f041ca5aa2ea7 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/README.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu Nov 11 21:00:13 +0800 2021 +# Generated by export_simulation on Thu Nov 11 21:45:26 +0800 2021 # ################################################################################ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/file_info.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/file_info.txt index 1d40a9ad4cd07cc5a6026ea76297f7065923d11a..428eee3a8a326bb209ec8e4e77578adc05165446 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/file_info.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, inst_rom.v,verilog,xil_defaultlib,../../../../MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/inst_rom.sh b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/inst_rom.sh index 89e59cbbba7487b1333253f1756407a91a7dc4a1..0a899957ffcb402c273aab5e6f86ef16fcaded8d 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/inst_rom.sh +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/inst_rom.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu Nov 11 21:00:13 +0800 2021 +# Generated by Vivado on Thu Nov 11 21:45:26 +0800 2021 # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -71,12 +71,12 @@ compile() { # Compile design files vlogan -work xpm $vlogan_opts -sverilog \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ 2>&1 | tee -a vlogan.log vhdlan -work xpm $vhdlan_opts \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ 2>&1 | tee -a vhdlan.log vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k \ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/README.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/README.txt index fd15c1c2d8595e427dd4054cb0036de652d16deb..318469838bd20d3d484c4d7704a41e1e902fb05b 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/README.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu Nov 11 21:00:13 +0800 2021 +# Generated by export_simulation on Thu Nov 11 21:45:26 +0800 2021 # ################################################################################ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/file_info.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/file_info.txt index 1d40a9ad4cd07cc5a6026ea76297f7065923d11a..428eee3a8a326bb209ec8e4e77578adc05165446 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/file_info.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, inst_rom.v,verilog,xil_defaultlib,../../../../MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/inst_rom.sh b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/inst_rom.sh index 93c5bc7f07494f65f4eec29f7f32bf52f84bb7ae..87f11d742855fa4cb5dc04394c9d0c090fa530a2 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/inst_rom.sh +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/inst_rom.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu Nov 11 21:00:13 +0800 2021 +# Generated by Vivado on Thu Nov 11 21:45:26 +0800 2021 # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/run.f b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/run.f index c88b5537fd3eea01de0a11f206b434c704644d46..addd3aa64881d3dc4331720f47fa06b0ae6cae0e 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/run.f +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/run.f @@ -1,9 +1,9 @@ -makelib xcelium_lib/xpm -sv \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ -endlib -makelib xcelium_lib/xpm \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ -endlib -makelib xcelium_lib/blk_mem_gen_v8_4_4 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xsim/README.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xsim/README.txt index e9ef368a594a5ccad025fc9144bdf3f34a3be343..1e8162ec8558b5c775f512e0c95f041ca5aa2ea7 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xsim/README.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu Nov 11 21:00:13 +0800 2021 +# Generated by export_simulation on Thu Nov 11 21:45:26 +0800 2021 # ################################################################################ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xsim/inst_rom.sh b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xsim/inst_rom.sh index 4c6cd2d2c0894c42ee7987887751ead15ab28cab..75c3ef80a60c717ce413bb10e2146b033c181f7a 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xsim/inst_rom.sh +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xsim/inst_rom.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu Nov 11 21:00:13 +0800 2021 +# Generated by Vivado on Thu Nov 11 21:45:26 +0800 2021 # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -22,7 +22,7 @@ #********************************************************************************************************* # Command line options -xv_boost_lib_path=F:/vivado/Vivado/2019.2/tps/boost_1_64_0 +xv_boost_lib_path=E:/xlinx/Vivado/2019.2/tps/boost_1_64_0 xvlog_opts="--relax" @@ -92,7 +92,7 @@ setup() copy_setup_file() { file="xsim.ini" - lib_map_path="F:/vivado/Vivado/2019.2/data/xsim" + lib_map_path="E:/xlinx/Vivado/2019.2/data/xsim" if [[ ($1 != "") ]]; then lib_map_path="$1" fi diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/.jobs/vrs_config_18.xml b/CPU_core/MiniMIPS32/MiniMIPS32.runs/.jobs/vrs_config_18.xml new file mode 100644 index 0000000000000000000000000000000000000000..54ec90a21466857c3e3ead4bb456c7728937528c --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/.jobs/vrs_config_18.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/.Vivado_Synthesis.queue.rst b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/.vivado.begin.rst b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/.vivado.begin.rst new file mode 100644 index 0000000000000000000000000000000000000000..a37d044041ecfa186e843d4201225898457af938 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/.vivado.end.rst b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/.vivado.end.rst new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/ISEWrap.js b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/ISEWrap.js new file mode 100644 index 0000000000000000000000000000000000000000..97a2ecbc3b6454b50f20bbc83f476fbd1d4e2b67 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/ISEWrap.sh b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/ISEWrap.sh new file mode 100644 index 0000000000000000000000000000000000000000..f679f2e86873e3482adf4a51d722e917f3d4aab2 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/__synthesis_is_complete__ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc new file mode 100644 index 0000000000000000000000000000000000000000..b8f15097422a204fafa77a5e8c78d9a654463f72 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc @@ -0,0 +1,16 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xci +# IP: The module: 'inst_rom' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'inst_rom'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# IP: F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xci +# IP: The module: 'inst_rom' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'inst_rom'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/gen_run.xml b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/gen_run.xml new file mode 100644 index 0000000000000000000000000000000000000000..3bd38344e2bba25f4e1453e90559b09eedf499a0 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/gen_run.xml @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/htr.txt b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/htr.txt new file mode 100644 index 0000000000000000000000000000000000000000..7a507760ef82f9eb11967e3107aa89d39d0b2586 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log inst_rom.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_rom.tcl diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp new file mode 100644 index 0000000000000000000000000000000000000000..43daa17c25116bda22ed2f737476870fbd327c25 Binary files /dev/null and b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp differ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.tcl b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.tcl new file mode 100644 index 0000000000000000000000000000000000000000..12fc38b8d4b4f6caa2f52e57ab887fbb43928e89 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.tcl @@ -0,0 +1,170 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7k325tffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt [current_project] +set_property parent.project_path F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xci +set_property used_in_implementation false [get_files -all f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1 -new_name inst_rom -ip [get_ips inst_rom]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top inst_rom -part xc7k325tffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix inst_rom_ inst_rom.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ inst_rom_stub.v + lappend ipCachedFiles inst_rom_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ inst_rom_stub.vhdl + lappend ipCachedFiles inst_rom_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ inst_rom_sim_netlist.v + lappend ipCachedFiles inst_rom_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ inst_rom_sim_netlist.vhdl + lappend ipCachedFiles inst_rom_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp inst_rom.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips inst_rom] +} + +rename_ref -prefix_all inst_rom_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef inst_rom.dcp +create_report "inst_rom_synth_1_synth_report_utilization_0" "report_utilization -file inst_rom_utilization_synth.rpt -pb inst_rom_utilization_synth.pb" + +if { [catch { + file copy -force F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.dcp +} _RESULT ] } { + send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + write_verilog -force -mode synth_stub F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +if { [catch { + file copy -force F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.dcp +} _RESULT ] } { + send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + file rename -force F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_stub.v F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_stub.vhdl F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_sim_netlist.v F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + file rename -force F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_sim_netlist.vhdl F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +}; # end if cached_ip + +if {[file isdir F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/ip/inst_rom]} { + catch { + file copy -force F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/ip/inst_rom + } +} + +if {[file isdir F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/ip/inst_rom]} { + catch { + file copy -force F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/ip/inst_rom + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.vds b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.vds new file mode 100644 index 0000000000000000000000000000000000000000..bbc0a8eef326156818a65039f12e7031f2830235 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.vds @@ -0,0 +1,456 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Thu Nov 11 21:45:28 2021 +# Process ID: 7060 +# Current directory: F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1 +# Command line: vivado.exe -log inst_rom.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_rom.tcl +# Log file: F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.vds +# Journal file: F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1\vivado.jou +#----------------------------------------------------------- +source inst_rom.tcl -notrace +Command: synth_design -top inst_rom -part xc7k325tffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' +INFO: [Device 21-403] Loading part xc7k325tffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 4240 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 866.430 ; gain = 235.070 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'inst_rom' [f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/synth/inst_rom.vhd:68] + Parameter C_FAMILY bound to: kintex7 - type: string + Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string + Parameter C_ELABORATION_DIR bound to: ./ - type: string + Parameter C_INTERFACE_TYPE bound to: 0 - type: integer + Parameter C_AXI_TYPE bound to: 1 - type: integer + Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer + Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer + Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer + Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string + Parameter C_HAS_AXI_ID bound to: 0 - type: integer + Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer + Parameter C_MEM_TYPE bound to: 3 - type: integer + Parameter C_BYTE_SIZE bound to: 9 - type: integer + Parameter C_ALGORITHM bound to: 1 - type: integer + Parameter C_PRIM_TYPE bound to: 1 - type: integer + Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer + Parameter C_INIT_FILE_NAME bound to: inst_rom.mif - type: string + Parameter C_INIT_FILE bound to: inst_rom.mem - type: string + Parameter C_USE_DEFAULT_DATA bound to: 0 - type: integer + Parameter C_DEFAULT_DATA bound to: 0 - type: string + Parameter C_HAS_RSTA bound to: 0 - type: integer + Parameter C_RST_PRIORITY_A bound to: CE - type: string + Parameter C_RSTRAM_A bound to: 0 - type: integer + Parameter C_INITA_VAL bound to: 0 - type: string + Parameter C_HAS_ENA bound to: 1 - type: integer + Parameter C_HAS_REGCEA bound to: 0 - type: integer + Parameter C_USE_BYTE_WEA bound to: 0 - type: integer + Parameter C_WEA_WIDTH bound to: 1 - type: integer + Parameter C_WRITE_MODE_A bound to: WRITE_FIRST - type: string + Parameter C_WRITE_WIDTH_A bound to: 32 - type: integer + Parameter C_READ_WIDTH_A bound to: 32 - type: integer + Parameter C_WRITE_DEPTH_A bound to: 2048 - type: integer + Parameter C_READ_DEPTH_A bound to: 2048 - type: integer + Parameter C_ADDRA_WIDTH bound to: 11 - type: integer + Parameter C_HAS_RSTB bound to: 0 - type: integer + Parameter C_RST_PRIORITY_B bound to: CE - type: string + Parameter C_RSTRAM_B bound to: 0 - type: integer + Parameter C_INITB_VAL bound to: 0 - type: string + Parameter C_HAS_ENB bound to: 0 - type: integer + Parameter C_HAS_REGCEB bound to: 0 - type: integer + Parameter C_USE_BYTE_WEB bound to: 0 - type: integer + Parameter C_WEB_WIDTH bound to: 1 - type: integer + Parameter C_WRITE_MODE_B bound to: WRITE_FIRST - type: string + Parameter C_WRITE_WIDTH_B bound to: 32 - type: integer + Parameter C_READ_WIDTH_B bound to: 32 - type: integer + Parameter C_WRITE_DEPTH_B bound to: 2048 - type: integer + Parameter C_READ_DEPTH_B bound to: 2048 - type: integer + Parameter C_ADDRB_WIDTH bound to: 11 - type: integer + Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 0 - type: integer + Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 0 - type: integer + Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 0 - type: integer + Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer + Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer + Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer + Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer + Parameter C_USE_SOFTECC bound to: 0 - type: integer + Parameter C_USE_ECC bound to: 0 - type: integer + Parameter C_EN_ECC_PIPE bound to: 0 - type: integer + Parameter C_READ_LATENCY_A bound to: 1 - type: integer + Parameter C_READ_LATENCY_B bound to: 1 - type: integer + Parameter C_HAS_INJECTERR bound to: 0 - type: integer + Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string + Parameter C_COMMON_CLK bound to: 0 - type: integer + Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer + Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer + Parameter C_USE_URAM bound to: 0 - type: integer + Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer + Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer + Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer + Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer + Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer + Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer + Parameter C_COUNT_36K_BRAM bound to: 2 - type: string + Parameter C_COUNT_18K_BRAM bound to: 0 - type: string + Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 4.8711 mW - type: string +INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_4' declared at 'f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_4' [f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/synth/inst_rom.vhd:232] +INFO: [Synth 8-256] done synthesizing module 'inst_rom' (9#1) [f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/synth/inst_rom.vhd:68] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port CLKB +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[31] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[30] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[29] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[28] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[27] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[26] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[25] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[24] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[23] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[22] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[21] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[20] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[19] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[18] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[17] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[16] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[15] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[14] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[13] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[12] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[11] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[10] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[9] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[8] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[7] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[6] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[5] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[4] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[3] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[2] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[1] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[0] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port SBITERR_I +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DBITERR_I +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[10] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[9] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[8] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[7] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[6] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[5] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[4] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[3] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[2] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[1] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[0] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port SSRA +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port CLKB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port SSRB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ENB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port REGCEB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port WEB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[10] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[9] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[8] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[7] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[6] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[5] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[4] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[3] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[2] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[17] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[16] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[15] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[14] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[13] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[12] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[11] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[10] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[9] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[8] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[7] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[6] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[5] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[4] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[3] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[2] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port SLEEP +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port INJECTSBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port INJECTDBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ECCPIPECE +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ram_rstram_b +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ram_rstreg_b +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRA +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port CLKB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ENB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port REGCEB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port WEB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[10] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[9] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[8] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[7] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[6] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[5] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[4] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1167.242 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_ooc.xdc] for cell 'U0' +Finished Parsing XDC File [f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_ooc.xdc] for cell 'U0' +Parsing XDC File [F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc] +Finished Parsing XDC File [F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.242 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1167.242 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k325tffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for U0. (constraint file F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 840 (col length:140) +BRAMs: 890 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----------+------+ +| |Cell |Count | ++------+-----------+------+ +|1 |RAMB36E1 | 1| +|2 |RAMB36E1_1 | 1| ++------+-----------+------+ + +Report Instance Areas: ++------+---------------------------------------------+----------------------------------------------+------+ +| |Instance |Module |Cells | ++------+---------------------------------------------+----------------------------------------------+------+ +|1 |top | | 2| +|2 | U0 |blk_mem_gen_v8_4_4 | 2| +|3 | inst_blk_mem_gen |blk_mem_gen_v8_4_4_synth | 2| +|4 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top | 2| +|5 | \valid.cstr |blk_mem_gen_generic_cstr | 2| +|6 | \ramloop[0].ram.r |blk_mem_gen_prim_width | 1| +|7 | \prim_init.ram |blk_mem_gen_prim_wrapper_init | 1| +|8 | \ramloop[1].ram.r |blk_mem_gen_prim_width__parameterized0 | 1| +|9 | \prim_init.ram |blk_mem_gen_prim_wrapper_init__parameterized0 | 1| ++------+---------------------------------------------+----------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 230 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:51 . Memory (MB): peak = 1167.242 ; gain = 535.883 +Synthesis Optimization Complete : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 1167.242 ; gain = 535.883 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1167.242 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.242 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +17 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:00:59 . Memory (MB): peak = 1167.242 ; gain = 865.621 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.242 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +WARNING: [Coretcl 2-1488] Problem adding IP cache entry: Directory already exists: f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/ip/2019.2/9888347cfb290ede +INFO: [Coretcl 2-1174] Renamed 8 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.242 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file inst_rom_utilization_synth.rpt -pb inst_rom_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Thu Nov 11 21:46:31 2021... diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_sim_netlist.v b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_sim_netlist.v new file mode 100644 index 0000000000000000000000000000000000000000..4740483e034b5f0a8814c947de4e815a10667760 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_sim_netlist.v @@ -0,0 +1,1136 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +// Date : Thu Nov 11 21:46:31 2021 +// Host : DESKTOP-B2469GJ running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ inst_rom_sim_netlist.v +// Design : inst_rom +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7k325tffg900-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "inst_rom,blk_mem_gen_v8_4_4,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2019.2" *) +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (clka, + ena, + addra, + douta); + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clka; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [10:0]addra; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [31:0]douta; + + wire [10:0]addra; + wire clka; + wire [31:0]douta; + wire ena; + wire NLW_U0_dbiterr_UNCONNECTED; + wire NLW_U0_rsta_busy_UNCONNECTED; + wire NLW_U0_rstb_busy_UNCONNECTED; + wire NLW_U0_s_axi_arready_UNCONNECTED; + wire NLW_U0_s_axi_awready_UNCONNECTED; + wire NLW_U0_s_axi_bvalid_UNCONNECTED; + wire NLW_U0_s_axi_dbiterr_UNCONNECTED; + wire NLW_U0_s_axi_rlast_UNCONNECTED; + wire NLW_U0_s_axi_rvalid_UNCONNECTED; + wire NLW_U0_s_axi_sbiterr_UNCONNECTED; + wire NLW_U0_s_axi_wready_UNCONNECTED; + wire NLW_U0_sbiterr_UNCONNECTED; + wire [31:0]NLW_U0_doutb_UNCONNECTED; + wire [10:0]NLW_U0_rdaddrecc_UNCONNECTED; + wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED; + wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; + wire [10:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED; + wire [31:0]NLW_U0_s_axi_rdata_UNCONNECTED; + wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED; + wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; + + (* C_ADDRA_WIDTH = "11" *) + (* C_ADDRB_WIDTH = "11" *) + (* C_ALGORITHM = "1" *) + (* C_AXI_ID_WIDTH = "4" *) + (* C_AXI_SLAVE_TYPE = "0" *) + (* C_AXI_TYPE = "1" *) + (* C_BYTE_SIZE = "9" *) + (* C_COMMON_CLK = "0" *) + (* C_COUNT_18K_BRAM = "0" *) + (* C_COUNT_36K_BRAM = "2" *) + (* C_CTRL_ECC_ALGO = "NONE" *) + (* C_DEFAULT_DATA = "0" *) + (* C_DISABLE_WARN_BHV_COLL = "0" *) + (* C_DISABLE_WARN_BHV_RANGE = "0" *) + (* C_ELABORATION_DIR = "./" *) + (* C_ENABLE_32BIT_ADDRESS = "0" *) + (* C_EN_DEEPSLEEP_PIN = "0" *) + (* C_EN_ECC_PIPE = "0" *) + (* C_EN_RDADDRA_CHG = "0" *) + (* C_EN_RDADDRB_CHG = "0" *) + (* C_EN_SAFETY_CKT = "0" *) + (* C_EN_SHUTDOWN_PIN = "0" *) + (* C_EN_SLEEP_PIN = "0" *) + (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 4.8711 mW" *) + (* C_FAMILY = "kintex7" *) + (* C_HAS_AXI_ID = "0" *) + (* C_HAS_ENA = "1" *) + (* C_HAS_ENB = "0" *) + (* C_HAS_INJECTERR = "0" *) + (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) + (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) + (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) + (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) + (* C_HAS_REGCEA = "0" *) + (* C_HAS_REGCEB = "0" *) + (* C_HAS_RSTA = "0" *) + (* C_HAS_RSTB = "0" *) + (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) + (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) + (* C_INITA_VAL = "0" *) + (* C_INITB_VAL = "0" *) + (* C_INIT_FILE = "inst_rom.mem" *) + (* C_INIT_FILE_NAME = "inst_rom.mif" *) + (* C_INTERFACE_TYPE = "0" *) + (* C_LOAD_INIT_FILE = "1" *) + (* C_MEM_TYPE = "3" *) + (* C_MUX_PIPELINE_STAGES = "0" *) + (* C_PRIM_TYPE = "1" *) + (* C_READ_DEPTH_A = "2048" *) + (* C_READ_DEPTH_B = "2048" *) + (* C_READ_LATENCY_A = "1" *) + (* C_READ_LATENCY_B = "1" *) + (* C_READ_WIDTH_A = "32" *) + (* C_READ_WIDTH_B = "32" *) + (* C_RSTRAM_A = "0" *) + (* C_RSTRAM_B = "0" *) + (* C_RST_PRIORITY_A = "CE" *) + (* C_RST_PRIORITY_B = "CE" *) + (* C_SIM_COLLISION_CHECK = "ALL" *) + (* C_USE_BRAM_BLOCK = "0" *) + (* C_USE_BYTE_WEA = "0" *) + (* C_USE_BYTE_WEB = "0" *) + (* C_USE_DEFAULT_DATA = "0" *) + (* C_USE_ECC = "0" *) + (* C_USE_SOFTECC = "0" *) + (* C_USE_URAM = "0" *) + (* C_WEA_WIDTH = "1" *) + (* C_WEB_WIDTH = "1" *) + (* C_WRITE_DEPTH_A = "2048" *) + (* C_WRITE_DEPTH_B = "2048" *) + (* C_WRITE_MODE_A = "WRITE_FIRST" *) + (* C_WRITE_MODE_B = "WRITE_FIRST" *) + (* C_WRITE_WIDTH_A = "32" *) + (* C_WRITE_WIDTH_B = "32" *) + (* C_XDEVICEFAMILY = "kintex7" *) + (* downgradeipidentifiedwarnings = "yes" *) + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 U0 + (.addra(addra), + .addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .clka(clka), + .clkb(1'b0), + .dbiterr(NLW_U0_dbiterr_UNCONNECTED), + .deepsleep(1'b0), + .dina({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .douta(douta), + .doutb(NLW_U0_doutb_UNCONNECTED[31:0]), + .eccpipece(1'b0), + .ena(ena), + .enb(1'b0), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[10:0]), + .regcea(1'b0), + .regceb(1'b0), + .rsta(1'b0), + .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED), + .rstb(1'b0), + .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED), + .s_aclk(1'b0), + .s_aresetn(1'b0), + .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_arburst({1'b0,1'b0}), + .s_axi_arid({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), + .s_axi_arsize({1'b0,1'b0,1'b0}), + .s_axi_arvalid(1'b0), + .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awburst({1'b0,1'b0}), + .s_axi_awid({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), + .s_axi_awsize({1'b0,1'b0,1'b0}), + .s_axi_awvalid(1'b0), + .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]), + .s_axi_bready(1'b0), + .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), + .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), + .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED), + .s_axi_injectdbiterr(1'b0), + .s_axi_injectsbiterr(1'b0), + .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[10:0]), + .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[31:0]), + .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]), + .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), + .s_axi_rready(1'b0), + .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), + .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), + .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED), + .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_wlast(1'b0), + .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), + .s_axi_wstrb(1'b0), + .s_axi_wvalid(1'b0), + .sbiterr(NLW_U0_sbiterr_UNCONNECTED), + .shutdown(1'b0), + .sleep(1'b0), + .wea(1'b0), + .web(1'b0)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr + (douta, + clka, + ena, + addra); + output [31:0]douta; + input clka; + input ena; + input [10:0]addra; + + wire [10:0]addra; + wire clka; + wire [31:0]douta; + wire ena; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r + (.addra(addra), + .clka(clka), + .douta(douta[17:0]), + .ena(ena)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r + (.addra(addra), + .clka(clka), + .douta(douta[31:18]), + .ena(ena)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width + (douta, + clka, + ena, + addra); + output [17:0]douta; + input clka; + input ena; + input [10:0]addra; + + wire [10:0]addra; + wire clka; + wire [17:0]douta; + wire ena; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init \prim_init.ram + (.addra(addra), + .clka(clka), + .douta(douta), + .ena(ena)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 + (douta, + clka, + ena, + addra); + output [13:0]douta; + input clka; + input ena; + input [10:0]addra; + + wire [10:0]addra; + wire clka; + wire [13:0]douta; + wire ena; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram + (.addra(addra), + .clka(clka), + .douta(douta), + .ena(ena)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init + (douta, + clka, + ena, + addra); + output [17:0]douta; + input clka; + input ena; + input [10:0]addra; + + wire [10:0]addra; + wire clka; + wire [17:0]douta; + wire ena; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h00000000000000000000000000000000000000005029580074809780A54801D8), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'hA936093C04019435043C8435043C00000916A936893C04011435043C8435043C), + .INIT_01(256'h04019435843C8435843C000009162936893C04019435043C8435043C00000916), + .INIT_02(256'h04010424042400000916A936093C04019435843C0435043C00000916A936893C), + .INIT_03(256'h000000000000000000000000000000000000000000000000004A000009160924), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), + .READ_WIDTH_A(18), + .READ_WIDTH_B(18), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(18), + .WRITE_WIDTH_B(18)) + \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(clka), + .CLKBWRCLK(clka), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,1'b0}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:16],douta[16:9],douta[7:0]}), + .DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]), + .DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:2],douta[17],douta[8]}), + .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena), + .ENBWREN(1'b0), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({1'b0,1'b0,1'b0,1'b0}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0 + (douta, + clka, + ena, + addra); + output [13:0]douta; + input clka; + input ena; + input [10:0]addra; + + wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_20 ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_28 ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_70 ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71 ; + wire [10:0]addra; + wire clka; + wire [13:0]douta; + wire ena; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h101349741020701C3C6A20370C4A00001600040C0A111020020C4950023F4001), + .INIT_01(256'h10207237373E7109761600000D003E4B077010200E7E5650300C306000001140), + .INIT_02(256'h10200000000000000400003A3C12102000125F7600285C5C0000084063012D55), + .INIT_03(256'h000000000000000000000000000000000000000000001F400000000001000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), + .READ_WIDTH_A(18), + .READ_WIDTH_B(18), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(18), + .WRITE_WIDTH_B(18)) + \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(clka), + .CLKBWRCLK(clka), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,1'b0}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:16],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_20 ,douta[13:7],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_28 ,douta[6:0]}), + .DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]), + .DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:2],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_70 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71 }), + .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena), + .ENBWREN(1'b0), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({1'b0,1'b0,1'b0,1'b0}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top + (douta, + clka, + ena, + addra); + output [31:0]douta; + input clka; + input ena; + input [10:0]addra; + + wire [10:0]addra; + wire clka; + wire [31:0]douta; + wire ena; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr + (.addra(addra), + .clka(clka), + .douta(douta), + .ena(ena)); +endmodule + +(* C_ADDRA_WIDTH = "11" *) (* C_ADDRB_WIDTH = "11" *) (* C_ALGORITHM = "1" *) +(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) +(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *) +(* C_COUNT_36K_BRAM = "2" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *) +(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *) +(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *) +(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) +(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 4.8711 mW" *) +(* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *) +(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) +(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) +(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) +(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) +(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "inst_rom.mem" *) +(* C_INIT_FILE_NAME = "inst_rom.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *) +(* C_MEM_TYPE = "3" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) +(* C_READ_DEPTH_A = "2048" *) (* C_READ_DEPTH_B = "2048" *) (* C_READ_LATENCY_A = "1" *) +(* C_READ_LATENCY_B = "1" *) (* C_READ_WIDTH_A = "32" *) (* C_READ_WIDTH_B = "32" *) +(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *) +(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *) +(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *) +(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *) +(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "2048" *) +(* C_WRITE_DEPTH_B = "2048" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) +(* C_WRITE_WIDTH_A = "32" *) (* C_WRITE_WIDTH_B = "32" *) (* C_XDEVICEFAMILY = "kintex7" *) +(* downgradeipidentifiedwarnings = "yes" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 + (clka, + rsta, + ena, + regcea, + wea, + addra, + dina, + douta, + clkb, + rstb, + enb, + regceb, + web, + addrb, + dinb, + doutb, + injectsbiterr, + injectdbiterr, + eccpipece, + sbiterr, + dbiterr, + rdaddrecc, + sleep, + deepsleep, + shutdown, + rsta_busy, + rstb_busy, + s_aclk, + s_aresetn, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_arid, + s_axi_araddr, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_rvalid, + s_axi_rready, + s_axi_injectsbiterr, + s_axi_injectdbiterr, + s_axi_sbiterr, + s_axi_dbiterr, + s_axi_rdaddrecc); + input clka; + input rsta; + input ena; + input regcea; + input [0:0]wea; + input [10:0]addra; + input [31:0]dina; + output [31:0]douta; + input clkb; + input rstb; + input enb; + input regceb; + input [0:0]web; + input [10:0]addrb; + input [31:0]dinb; + output [31:0]doutb; + input injectsbiterr; + input injectdbiterr; + input eccpipece; + output sbiterr; + output dbiterr; + output [10:0]rdaddrecc; + input sleep; + input deepsleep; + input shutdown; + output rsta_busy; + output rstb_busy; + input s_aclk; + input s_aresetn; + input [3:0]s_axi_awid; + input [31:0]s_axi_awaddr; + input [7:0]s_axi_awlen; + input [2:0]s_axi_awsize; + input [1:0]s_axi_awburst; + input s_axi_awvalid; + output s_axi_awready; + input [31:0]s_axi_wdata; + input [0:0]s_axi_wstrb; + input s_axi_wlast; + input s_axi_wvalid; + output s_axi_wready; + output [3:0]s_axi_bid; + output [1:0]s_axi_bresp; + output s_axi_bvalid; + input s_axi_bready; + input [3:0]s_axi_arid; + input [31:0]s_axi_araddr; + input [7:0]s_axi_arlen; + input [2:0]s_axi_arsize; + input [1:0]s_axi_arburst; + input s_axi_arvalid; + output s_axi_arready; + output [3:0]s_axi_rid; + output [31:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rlast; + output s_axi_rvalid; + input s_axi_rready; + input s_axi_injectsbiterr; + input s_axi_injectdbiterr; + output s_axi_sbiterr; + output s_axi_dbiterr; + output [10:0]s_axi_rdaddrecc; + + wire \ ; + wire [10:0]addra; + wire clka; + wire [31:0]douta; + wire ena; + + assign dbiterr = \ ; + assign doutb[31] = \ ; + assign doutb[30] = \ ; + assign doutb[29] = \ ; + assign doutb[28] = \ ; + assign doutb[27] = \ ; + assign doutb[26] = \ ; + assign doutb[25] = \ ; + assign doutb[24] = \ ; + assign doutb[23] = \ ; + assign doutb[22] = \ ; + assign doutb[21] = \ ; + assign doutb[20] = \ ; + assign doutb[19] = \ ; + assign doutb[18] = \ ; + assign doutb[17] = \ ; + assign doutb[16] = \ ; + assign doutb[15] = \ ; + assign doutb[14] = \ ; + assign doutb[13] = \ ; + assign doutb[12] = \ ; + assign doutb[11] = \ ; + assign doutb[10] = \ ; + assign doutb[9] = \ ; + assign doutb[8] = \ ; + assign doutb[7] = \ ; + assign doutb[6] = \ ; + assign doutb[5] = \ ; + assign doutb[4] = \ ; + assign doutb[3] = \ ; + assign doutb[2] = \ ; + assign doutb[1] = \ ; + assign doutb[0] = \ ; + assign rdaddrecc[10] = \ ; + assign rdaddrecc[9] = \ ; + assign rdaddrecc[8] = \ ; + assign rdaddrecc[7] = \ ; + assign rdaddrecc[6] = \ ; + assign rdaddrecc[5] = \ ; + assign rdaddrecc[4] = \ ; + assign rdaddrecc[3] = \ ; + assign rdaddrecc[2] = \ ; + assign rdaddrecc[1] = \ ; + assign rdaddrecc[0] = \ ; + assign rsta_busy = \ ; + assign rstb_busy = \ ; + assign s_axi_arready = \ ; + assign s_axi_awready = \ ; + assign s_axi_bid[3] = \ ; + assign s_axi_bid[2] = \ ; + assign s_axi_bid[1] = \ ; + assign s_axi_bid[0] = \ ; + assign s_axi_bresp[1] = \ ; + assign s_axi_bresp[0] = \ ; + assign s_axi_bvalid = \ ; + assign s_axi_dbiterr = \ ; + assign s_axi_rdaddrecc[10] = \ ; + assign s_axi_rdaddrecc[9] = \ ; + assign s_axi_rdaddrecc[8] = \ ; + assign s_axi_rdaddrecc[7] = \ ; + assign s_axi_rdaddrecc[6] = \ ; + assign s_axi_rdaddrecc[5] = \ ; + assign s_axi_rdaddrecc[4] = \ ; + assign s_axi_rdaddrecc[3] = \ ; + assign s_axi_rdaddrecc[2] = \ ; + assign s_axi_rdaddrecc[1] = \ ; + assign s_axi_rdaddrecc[0] = \ ; + assign s_axi_rdata[31] = \ ; + assign s_axi_rdata[30] = \ ; + assign s_axi_rdata[29] = \ ; + assign s_axi_rdata[28] = \ ; + assign s_axi_rdata[27] = \ ; + assign s_axi_rdata[26] = \ ; + assign s_axi_rdata[25] = \ ; + assign s_axi_rdata[24] = \ ; + assign s_axi_rdata[23] = \ ; + assign s_axi_rdata[22] = \ ; + assign s_axi_rdata[21] = \ ; + assign s_axi_rdata[20] = \ ; + assign s_axi_rdata[19] = \ ; + assign s_axi_rdata[18] = \ ; + assign s_axi_rdata[17] = \ ; + assign s_axi_rdata[16] = \ ; + assign s_axi_rdata[15] = \ ; + assign s_axi_rdata[14] = \ ; + assign s_axi_rdata[13] = \ ; + assign s_axi_rdata[12] = \ ; + assign s_axi_rdata[11] = \ ; + assign s_axi_rdata[10] = \ ; + assign s_axi_rdata[9] = \ ; + assign s_axi_rdata[8] = \ ; + assign s_axi_rdata[7] = \ ; + assign s_axi_rdata[6] = \ ; + assign s_axi_rdata[5] = \ ; + assign s_axi_rdata[4] = \ ; + assign s_axi_rdata[3] = \ ; + assign s_axi_rdata[2] = \ ; + assign s_axi_rdata[1] = \ ; + assign s_axi_rdata[0] = \ ; + assign s_axi_rid[3] = \ ; + assign s_axi_rid[2] = \ ; + assign s_axi_rid[1] = \ ; + assign s_axi_rid[0] = \ ; + assign s_axi_rlast = \ ; + assign s_axi_rresp[1] = \ ; + assign s_axi_rresp[0] = \ ; + assign s_axi_rvalid = \ ; + assign s_axi_sbiterr = \ ; + assign s_axi_wready = \ ; + assign sbiterr = \ ; + GND GND + (.G(\ )); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4_synth inst_blk_mem_gen + (.addra(addra), + .clka(clka), + .douta(douta), + .ena(ena)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4_synth + (douta, + clka, + ena, + addra); + output [31:0]douta; + input clka; + input ena; + input [10:0]addra; + + wire [10:0]addra; + wire clka; + wire [31:0]douta; + wire ena; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen + (.addra(addra), + .clka(clka), + .douta(douta), + .ena(ena)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_sim_netlist.vhdl b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_sim_netlist.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..48fa5b1d8816333ca54b77f5cfa650d0efe754ce --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_sim_netlist.vhdl @@ -0,0 +1,1253 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +-- Date : Thu Nov 11 21:46:31 2021 +-- Host : DESKTOP-B2469GJ running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ inst_rom_sim_netlist.vhdl +-- Design : inst_rom +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7k325tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is + port ( + douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); + clka : in STD_LOGIC; + ena : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute box_type : string; + attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; +begin +\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 0, + DOB_REG => 0, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"00000000000000000000000000000000000000005029580074809780A54801D8", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_00 => X"A936093C04019435043C8435043C00000916A936893C04011435043C8435043C", + INIT_01 => X"04019435843C8435843C000009162936893C04019435043C8435043C00000916", + INIT_02 => X"04010424042400000916A936093C04019435843C0435043C00000916A936893C", + INIT_03 => X"000000000000000000000000000000000000000000000000004A000009160924", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", + READ_WIDTH_A => 18, + READ_WIDTH_B => 18, + RSTREG_PRIORITY_A => "REGCE", + RSTREG_PRIORITY_B => "REGCE", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "WRITE_FIRST", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 18, + WRITE_WIDTH_B => 18 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 4) => addra(10 downto 0), + ADDRARDADDR(3 downto 0) => B"1111", + ADDRBWRADDR(15 downto 0) => B"0000000000000000", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => clka, + CLKBWRCLK => clka, + DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, + DIADI(31 downto 0) => B"00000000000000000000000000000000", + DIBDI(31 downto 0) => B"00000000000000000000000000000000", + DIPADIP(3 downto 0) => B"0000", + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 16), + DOADO(15 downto 8) => douta(16 downto 9), + DOADO(7 downto 0) => douta(7 downto 0), + DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0), + DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 2), + DOPADOP(1) => douta(17), + DOPADOP(0) => douta(8), + DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), + ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => ena, + ENBWREN => '0', + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '0', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"0000", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ is + port ( + douta : out STD_LOGIC_VECTOR ( 13 downto 0 ); + clka : in STD_LOGIC; + ena : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init"; +end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\; + +architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ is + signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_20\ : STD_LOGIC; + signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_28\ : STD_LOGIC; + signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_70\ : STD_LOGIC; + signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute box_type : string; + attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; +begin +\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 0, + DOB_REG => 0, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_00 => X"101349741020701C3C6A20370C4A00001600040C0A111020020C4950023F4001", + INIT_01 => X"10207237373E7109761600000D003E4B077010200E7E5650300C306000001140", + INIT_02 => X"10200000000000000400003A3C12102000125F7600285C5C0000084063012D55", + INIT_03 => X"000000000000000000000000000000000000000000001F400000000001000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", + READ_WIDTH_A => 18, + READ_WIDTH_B => 18, + RSTREG_PRIORITY_A => "REGCE", + RSTREG_PRIORITY_B => "REGCE", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "WRITE_FIRST", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 18, + WRITE_WIDTH_B => 18 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 4) => addra(10 downto 0), + ADDRARDADDR(3 downto 0) => B"1111", + ADDRBWRADDR(15 downto 0) => B"0000000000000000", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => clka, + CLKBWRCLK => clka, + DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, + DIADI(31 downto 0) => B"00000000000000000000000000000000", + DIBDI(31 downto 0) => B"00000000000000000000000000000000", + DIPADIP(3 downto 0) => B"0000", + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 16), + DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_20\, + DOADO(14 downto 8) => douta(13 downto 7), + DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_28\, + DOADO(6 downto 0) => douta(6 downto 0), + DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0), + DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 2), + DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_70\, + DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\, + DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), + ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => ena, + ENBWREN => '0', + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => '0', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => '0', + SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"0000", + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is + port ( + douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); + clka : in STD_LOGIC; + ena : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is +begin +\prim_init.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init + port map ( + addra(10 downto 0) => addra(10 downto 0), + clka => clka, + douta(17 downto 0) => douta(17 downto 0), + ena => ena + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is + port ( + douta : out STD_LOGIC_VECTOR ( 13 downto 0 ); + clka : in STD_LOGIC; + ena : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width"; +end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\; + +architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is +begin +\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ + port map ( + addra(10 downto 0) => addra(10 downto 0), + clka => clka, + douta(13 downto 0) => douta(13 downto 0), + ena => ena + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is + port ( + douta : out STD_LOGIC_VECTOR ( 31 downto 0 ); + clka : in STD_LOGIC; + ena : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is +begin +\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width + port map ( + addra(10 downto 0) => addra(10 downto 0), + clka => clka, + douta(17 downto 0) => douta(17 downto 0), + ena => ena + ); +\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ + port map ( + addra(10 downto 0) => addra(10 downto 0), + clka => clka, + douta(13 downto 0) => douta(31 downto 18), + ena => ena + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is + port ( + douta : out STD_LOGIC_VECTOR ( 31 downto 0 ); + clka : in STD_LOGIC; + ena : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is +begin +\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr + port map ( + addra(10 downto 0) => addra(10 downto 0), + clka => clka, + douta(31 downto 0) => douta(31 downto 0), + ena => ena + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4_synth is + port ( + douta : out STD_LOGIC_VECTOR ( 31 downto 0 ); + clka : in STD_LOGIC; + ena : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4_synth; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4_synth is +begin +\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top + port map ( + addra(10 downto 0) => addra(10 downto 0), + clka => clka, + douta(31 downto 0) => douta(31 downto 0), + ena => ena + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 is + port ( + clka : in STD_LOGIC; + rsta : in STD_LOGIC; + ena : in STD_LOGIC; + regcea : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 31 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 31 downto 0 ); + clkb : in STD_LOGIC; + rstb : in STD_LOGIC; + enb : in STD_LOGIC; + regceb : in STD_LOGIC; + web : in STD_LOGIC_VECTOR ( 0 to 0 ); + addrb : in STD_LOGIC_VECTOR ( 10 downto 0 ); + dinb : in STD_LOGIC_VECTOR ( 31 downto 0 ); + doutb : out STD_LOGIC_VECTOR ( 31 downto 0 ); + injectsbiterr : in STD_LOGIC; + injectdbiterr : in STD_LOGIC; + eccpipece : in STD_LOGIC; + sbiterr : out STD_LOGIC; + dbiterr : out STD_LOGIC; + rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 ); + sleep : in STD_LOGIC; + deepsleep : in STD_LOGIC; + shutdown : in STD_LOGIC; + rsta_busy : out STD_LOGIC; + rstb_busy : out STD_LOGIC; + s_aclk : in STD_LOGIC; + s_aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rlast : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + s_axi_injectsbiterr : in STD_LOGIC; + s_axi_injectdbiterr : in STD_LOGIC; + s_axi_sbiterr : out STD_LOGIC; + s_axi_dbiterr : out STD_LOGIC; + s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 ) + ); + attribute C_ADDRA_WIDTH : integer; + attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 11; + attribute C_ADDRB_WIDTH : integer; + attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 11; + attribute C_ALGORITHM : integer; + attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 1; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 4; + attribute C_AXI_SLAVE_TYPE : integer; + attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_AXI_TYPE : integer; + attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 1; + attribute C_BYTE_SIZE : integer; + attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 9; + attribute C_COMMON_CLK : integer; + attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_COUNT_18K_BRAM : string; + attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "0"; + attribute C_COUNT_36K_BRAM : string; + attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "2"; + attribute C_CTRL_ECC_ALGO : string; + attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "NONE"; + attribute C_DEFAULT_DATA : string; + attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "0"; + attribute C_DISABLE_WARN_BHV_COLL : integer; + attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_DISABLE_WARN_BHV_RANGE : integer; + attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_ELABORATION_DIR : string; + attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "./"; + attribute C_ENABLE_32BIT_ADDRESS : integer; + attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_EN_DEEPSLEEP_PIN : integer; + attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_EN_ECC_PIPE : integer; + attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_EN_RDADDRA_CHG : integer; + attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_EN_RDADDRB_CHG : integer; + attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_EN_SAFETY_CKT : integer; + attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_EN_SHUTDOWN_PIN : integer; + attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_EN_SLEEP_PIN : integer; + attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_EST_POWER_SUMMARY : string; + attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "Estimated Power for IP : 4.8711 mW"; + attribute C_FAMILY : string; + attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "kintex7"; + attribute C_HAS_AXI_ID : integer; + attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_HAS_ENA : integer; + attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 1; + attribute C_HAS_ENB : integer; + attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_HAS_INJECTERR : integer; + attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_HAS_MEM_OUTPUT_REGS_A : integer; + attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_HAS_MEM_OUTPUT_REGS_B : integer; + attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_HAS_MUX_OUTPUT_REGS_A : integer; + attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_HAS_MUX_OUTPUT_REGS_B : integer; + attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_HAS_REGCEA : integer; + attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_HAS_REGCEB : integer; + attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_HAS_RSTA : integer; + attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_HAS_RSTB : integer; + attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; + attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; + attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_INITA_VAL : string; + attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "0"; + attribute C_INITB_VAL : string; + attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "0"; + attribute C_INIT_FILE : string; + attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "inst_rom.mem"; + attribute C_INIT_FILE_NAME : string; + attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "inst_rom.mif"; + attribute C_INTERFACE_TYPE : integer; + attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_LOAD_INIT_FILE : integer; + attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 1; + attribute C_MEM_TYPE : integer; + attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 3; + attribute C_MUX_PIPELINE_STAGES : integer; + attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_PRIM_TYPE : integer; + attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 1; + attribute C_READ_DEPTH_A : integer; + attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 2048; + attribute C_READ_DEPTH_B : integer; + attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 2048; + attribute C_READ_LATENCY_A : integer; + attribute C_READ_LATENCY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 1; + attribute C_READ_LATENCY_B : integer; + attribute C_READ_LATENCY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 1; + attribute C_READ_WIDTH_A : integer; + attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 32; + attribute C_READ_WIDTH_B : integer; + attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 32; + attribute C_RSTRAM_A : integer; + attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_RSTRAM_B : integer; + attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_RST_PRIORITY_A : string; + attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "CE"; + attribute C_RST_PRIORITY_B : string; + attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "CE"; + attribute C_SIM_COLLISION_CHECK : string; + attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "ALL"; + attribute C_USE_BRAM_BLOCK : integer; + attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_USE_BYTE_WEA : integer; + attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_USE_BYTE_WEB : integer; + attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_USE_DEFAULT_DATA : integer; + attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_USE_ECC : integer; + attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_USE_SOFTECC : integer; + attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_USE_URAM : integer; + attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 0; + attribute C_WEA_WIDTH : integer; + attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 1; + attribute C_WEB_WIDTH : integer; + attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 1; + attribute C_WRITE_DEPTH_A : integer; + attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 2048; + attribute C_WRITE_DEPTH_B : integer; + attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 2048; + attribute C_WRITE_MODE_A : string; + attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "WRITE_FIRST"; + attribute C_WRITE_MODE_B : string; + attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "WRITE_FIRST"; + attribute C_WRITE_WIDTH_A : integer; + attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 32; + attribute C_WRITE_WIDTH_B : integer; + attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is 32; + attribute C_XDEVICEFAMILY : string; + attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "kintex7"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 : entity is "yes"; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 is + signal \\ : STD_LOGIC; +begin + dbiterr <= \\; + doutb(31) <= \\; + doutb(30) <= \\; + doutb(29) <= \\; + doutb(28) <= \\; + doutb(27) <= \\; + doutb(26) <= \\; + doutb(25) <= \\; + doutb(24) <= \\; + doutb(23) <= \\; + doutb(22) <= \\; + doutb(21) <= \\; + doutb(20) <= \\; + doutb(19) <= \\; + doutb(18) <= \\; + doutb(17) <= \\; + doutb(16) <= \\; + doutb(15) <= \\; + doutb(14) <= \\; + doutb(13) <= \\; + doutb(12) <= \\; + doutb(11) <= \\; + doutb(10) <= \\; + doutb(9) <= \\; + doutb(8) <= \\; + doutb(7) <= \\; + doutb(6) <= \\; + doutb(5) <= \\; + doutb(4) <= \\; + doutb(3) <= \\; + doutb(2) <= \\; + doutb(1) <= \\; + doutb(0) <= \\; + rdaddrecc(10) <= \\; + rdaddrecc(9) <= \\; + rdaddrecc(8) <= \\; + rdaddrecc(7) <= \\; + rdaddrecc(6) <= \\; + rdaddrecc(5) <= \\; + rdaddrecc(4) <= \\; + rdaddrecc(3) <= \\; + rdaddrecc(2) <= \\; + rdaddrecc(1) <= \\; + rdaddrecc(0) <= \\; + rsta_busy <= \\; + rstb_busy <= \\; + s_axi_arready <= \\; + s_axi_awready <= \\; + s_axi_bid(3) <= \\; + s_axi_bid(2) <= \\; + s_axi_bid(1) <= \\; + s_axi_bid(0) <= \\; + s_axi_bresp(1) <= \\; + s_axi_bresp(0) <= \\; + s_axi_bvalid <= \\; + s_axi_dbiterr <= \\; + s_axi_rdaddrecc(10) <= \\; + s_axi_rdaddrecc(9) <= \\; + s_axi_rdaddrecc(8) <= \\; + s_axi_rdaddrecc(7) <= \\; + s_axi_rdaddrecc(6) <= \\; + s_axi_rdaddrecc(5) <= \\; + s_axi_rdaddrecc(4) <= \\; + s_axi_rdaddrecc(3) <= \\; + s_axi_rdaddrecc(2) <= \\; + s_axi_rdaddrecc(1) <= \\; + s_axi_rdaddrecc(0) <= \\; + s_axi_rdata(31) <= \\; + s_axi_rdata(30) <= \\; + s_axi_rdata(29) <= \\; + s_axi_rdata(28) <= \\; + s_axi_rdata(27) <= \\; + s_axi_rdata(26) <= \\; + s_axi_rdata(25) <= \\; + s_axi_rdata(24) <= \\; + s_axi_rdata(23) <= \\; + s_axi_rdata(22) <= \\; + s_axi_rdata(21) <= \\; + s_axi_rdata(20) <= \\; + s_axi_rdata(19) <= \\; + s_axi_rdata(18) <= \\; + s_axi_rdata(17) <= \\; + s_axi_rdata(16) <= \\; + s_axi_rdata(15) <= \\; + s_axi_rdata(14) <= \\; + s_axi_rdata(13) <= \\; + s_axi_rdata(12) <= \\; + s_axi_rdata(11) <= \\; + s_axi_rdata(10) <= \\; + s_axi_rdata(9) <= \\; + s_axi_rdata(8) <= \\; + s_axi_rdata(7) <= \\; + s_axi_rdata(6) <= \\; + s_axi_rdata(5) <= \\; + s_axi_rdata(4) <= \\; + s_axi_rdata(3) <= \\; + s_axi_rdata(2) <= \\; + s_axi_rdata(1) <= \\; + s_axi_rdata(0) <= \\; + s_axi_rid(3) <= \\; + s_axi_rid(2) <= \\; + s_axi_rid(1) <= \\; + s_axi_rid(0) <= \\; + s_axi_rlast <= \\; + s_axi_rresp(1) <= \\; + s_axi_rresp(0) <= \\; + s_axi_rvalid <= \\; + s_axi_sbiterr <= \\; + s_axi_wready <= \\; + sbiterr <= \\; +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4_synth + port map ( + addra(10 downto 0) => addra(10 downto 0), + clka => clka, + douta(31 downto 0) => douta(31 downto 0), + ena => ena + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "inst_rom,blk_mem_gen_v8_4_4,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; + attribute x_core_info : string; + attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_4_4,Vivado 2019.2"; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; + signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute C_ADDRA_WIDTH : integer; + attribute C_ADDRA_WIDTH of U0 : label is 11; + attribute C_ADDRB_WIDTH : integer; + attribute C_ADDRB_WIDTH of U0 : label is 11; + attribute C_ALGORITHM : integer; + attribute C_ALGORITHM of U0 : label is 1; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of U0 : label is 4; + attribute C_AXI_SLAVE_TYPE : integer; + attribute C_AXI_SLAVE_TYPE of U0 : label is 0; + attribute C_AXI_TYPE : integer; + attribute C_AXI_TYPE of U0 : label is 1; + attribute C_BYTE_SIZE : integer; + attribute C_BYTE_SIZE of U0 : label is 9; + attribute C_COMMON_CLK : integer; + attribute C_COMMON_CLK of U0 : label is 0; + attribute C_COUNT_18K_BRAM : string; + attribute C_COUNT_18K_BRAM of U0 : label is "0"; + attribute C_COUNT_36K_BRAM : string; + attribute C_COUNT_36K_BRAM of U0 : label is "2"; + attribute C_CTRL_ECC_ALGO : string; + attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; + attribute C_DEFAULT_DATA : string; + attribute C_DEFAULT_DATA of U0 : label is "0"; + attribute C_DISABLE_WARN_BHV_COLL : integer; + attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; + attribute C_DISABLE_WARN_BHV_RANGE : integer; + attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; + attribute C_ELABORATION_DIR : string; + attribute C_ELABORATION_DIR of U0 : label is "./"; + attribute C_ENABLE_32BIT_ADDRESS : integer; + attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; + attribute C_EN_DEEPSLEEP_PIN : integer; + attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; + attribute C_EN_ECC_PIPE : integer; + attribute C_EN_ECC_PIPE of U0 : label is 0; + attribute C_EN_RDADDRA_CHG : integer; + attribute C_EN_RDADDRA_CHG of U0 : label is 0; + attribute C_EN_RDADDRB_CHG : integer; + attribute C_EN_RDADDRB_CHG of U0 : label is 0; + attribute C_EN_SAFETY_CKT : integer; + attribute C_EN_SAFETY_CKT of U0 : label is 0; + attribute C_EN_SHUTDOWN_PIN : integer; + attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; + attribute C_EN_SLEEP_PIN : integer; + attribute C_EN_SLEEP_PIN of U0 : label is 0; + attribute C_EST_POWER_SUMMARY : string; + attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 4.8711 mW"; + attribute C_FAMILY : string; + attribute C_FAMILY of U0 : label is "kintex7"; + attribute C_HAS_AXI_ID : integer; + attribute C_HAS_AXI_ID of U0 : label is 0; + attribute C_HAS_ENA : integer; + attribute C_HAS_ENA of U0 : label is 1; + attribute C_HAS_ENB : integer; + attribute C_HAS_ENB of U0 : label is 0; + attribute C_HAS_INJECTERR : integer; + attribute C_HAS_INJECTERR of U0 : label is 0; + attribute C_HAS_MEM_OUTPUT_REGS_A : integer; + attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0; + attribute C_HAS_MEM_OUTPUT_REGS_B : integer; + attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; + attribute C_HAS_MUX_OUTPUT_REGS_A : integer; + attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; + attribute C_HAS_MUX_OUTPUT_REGS_B : integer; + attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; + attribute C_HAS_REGCEA : integer; + attribute C_HAS_REGCEA of U0 : label is 0; + attribute C_HAS_REGCEB : integer; + attribute C_HAS_REGCEB of U0 : label is 0; + attribute C_HAS_RSTA : integer; + attribute C_HAS_RSTA of U0 : label is 0; + attribute C_HAS_RSTB : integer; + attribute C_HAS_RSTB of U0 : label is 0; + attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; + attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; + attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; + attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; + attribute C_INITA_VAL : string; + attribute C_INITA_VAL of U0 : label is "0"; + attribute C_INITB_VAL : string; + attribute C_INITB_VAL of U0 : label is "0"; + attribute C_INIT_FILE : string; + attribute C_INIT_FILE of U0 : label is "inst_rom.mem"; + attribute C_INIT_FILE_NAME : string; + attribute C_INIT_FILE_NAME of U0 : label is "inst_rom.mif"; + attribute C_INTERFACE_TYPE : integer; + attribute C_INTERFACE_TYPE of U0 : label is 0; + attribute C_LOAD_INIT_FILE : integer; + attribute C_LOAD_INIT_FILE of U0 : label is 1; + attribute C_MEM_TYPE : integer; + attribute C_MEM_TYPE of U0 : label is 3; + attribute C_MUX_PIPELINE_STAGES : integer; + attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; + attribute C_PRIM_TYPE : integer; + attribute C_PRIM_TYPE of U0 : label is 1; + attribute C_READ_DEPTH_A : integer; + attribute C_READ_DEPTH_A of U0 : label is 2048; + attribute C_READ_DEPTH_B : integer; + attribute C_READ_DEPTH_B of U0 : label is 2048; + attribute C_READ_LATENCY_A : integer; + attribute C_READ_LATENCY_A of U0 : label is 1; + attribute C_READ_LATENCY_B : integer; + attribute C_READ_LATENCY_B of U0 : label is 1; + attribute C_READ_WIDTH_A : integer; + attribute C_READ_WIDTH_A of U0 : label is 32; + attribute C_READ_WIDTH_B : integer; + attribute C_READ_WIDTH_B of U0 : label is 32; + attribute C_RSTRAM_A : integer; + attribute C_RSTRAM_A of U0 : label is 0; + attribute C_RSTRAM_B : integer; + attribute C_RSTRAM_B of U0 : label is 0; + attribute C_RST_PRIORITY_A : string; + attribute C_RST_PRIORITY_A of U0 : label is "CE"; + attribute C_RST_PRIORITY_B : string; + attribute C_RST_PRIORITY_B of U0 : label is "CE"; + attribute C_SIM_COLLISION_CHECK : string; + attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; + attribute C_USE_BRAM_BLOCK : integer; + attribute C_USE_BRAM_BLOCK of U0 : label is 0; + attribute C_USE_BYTE_WEA : integer; + attribute C_USE_BYTE_WEA of U0 : label is 0; + attribute C_USE_BYTE_WEB : integer; + attribute C_USE_BYTE_WEB of U0 : label is 0; + attribute C_USE_DEFAULT_DATA : integer; + attribute C_USE_DEFAULT_DATA of U0 : label is 0; + attribute C_USE_ECC : integer; + attribute C_USE_ECC of U0 : label is 0; + attribute C_USE_SOFTECC : integer; + attribute C_USE_SOFTECC of U0 : label is 0; + attribute C_USE_URAM : integer; + attribute C_USE_URAM of U0 : label is 0; + attribute C_WEA_WIDTH : integer; + attribute C_WEA_WIDTH of U0 : label is 1; + attribute C_WEB_WIDTH : integer; + attribute C_WEB_WIDTH of U0 : label is 1; + attribute C_WRITE_DEPTH_A : integer; + attribute C_WRITE_DEPTH_A of U0 : label is 2048; + attribute C_WRITE_DEPTH_B : integer; + attribute C_WRITE_DEPTH_B of U0 : label is 2048; + attribute C_WRITE_MODE_A : string; + attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; + attribute C_WRITE_MODE_B : string; + attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; + attribute C_WRITE_WIDTH_A : integer; + attribute C_WRITE_WIDTH_A of U0 : label is 32; + attribute C_WRITE_WIDTH_B : integer; + attribute C_WRITE_WIDTH_B of U0 : label is 32; + attribute C_XDEVICEFAMILY : string; + attribute C_XDEVICEFAMILY of U0 : label is "kintex7"; + attribute downgradeipidentifiedwarnings of U0 : label is "yes"; + attribute x_interface_info : string; + attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1"; + attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; + attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; + attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; +begin +U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4 + port map ( + addra(10 downto 0) => addra(10 downto 0), + addrb(10 downto 0) => B"00000000000", + clka => clka, + clkb => '0', + dbiterr => NLW_U0_dbiterr_UNCONNECTED, + deepsleep => '0', + dina(31 downto 0) => B"00000000000000000000000000000000", + dinb(31 downto 0) => B"00000000000000000000000000000000", + douta(31 downto 0) => douta(31 downto 0), + doutb(31 downto 0) => NLW_U0_doutb_UNCONNECTED(31 downto 0), + eccpipece => '0', + ena => ena, + enb => '0', + injectdbiterr => '0', + injectsbiterr => '0', + rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0), + regcea => '0', + regceb => '0', + rsta => '0', + rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, + rstb => '0', + rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, + s_aclk => '0', + s_aresetn => '0', + s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_arburst(1 downto 0) => B"00", + s_axi_arid(3 downto 0) => B"0000", + s_axi_arlen(7 downto 0) => B"00000000", + s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, + s_axi_arsize(2 downto 0) => B"000", + s_axi_arvalid => '0', + s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_awburst(1 downto 0) => B"00", + s_axi_awid(3 downto 0) => B"0000", + s_axi_awlen(7 downto 0) => B"00000000", + s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, + s_axi_awsize(2 downto 0) => B"000", + s_axi_awvalid => '0', + s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), + s_axi_bready => '0', + s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), + s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, + s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, + s_axi_injectdbiterr => '0', + s_axi_injectsbiterr => '0', + s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0), + s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0), + s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), + s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, + s_axi_rready => '0', + s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), + s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, + s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, + s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000", + s_axi_wlast => '0', + s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, + s_axi_wstrb(0) => '0', + s_axi_wvalid => '0', + sbiterr => NLW_U0_sbiterr_UNCONNECTED, + shutdown => '0', + sleep => '0', + wea(0) => '0', + web(0) => '0' + ); +end STRUCTURE; diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_stub.v b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_stub.v new file mode 100644 index 0000000000000000000000000000000000000000..d69831253d12a7e51a9176ada23fb31a7ac224d0 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_stub.v @@ -0,0 +1,23 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +// Date : Thu Nov 11 21:46:31 2021 +// Host : DESKTOP-B2469GJ running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ inst_rom_stub.v +// Design : inst_rom +// Purpose : Stub declaration of top-level module interface +// Device : xc7k325tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2019.2" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, ena, addra, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,addra[10:0],douta[31:0]" */; + input clka; + input ena; + input [10:0]addra; + output [31:0]douta; +endmodule diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_stub.vhdl b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..e37793aca1536b31192627b6b446e57debbb8078 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_stub.vhdl @@ -0,0 +1,33 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +-- Date : Thu Nov 11 21:46:31 2021 +-- Host : DESKTOP-B2469GJ running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ inst_rom_stub.vhdl +-- Design : inst_rom +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k325tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,addra[10:0],douta[31:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2019.2"; +begin +end; diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_utilization_synth.pb b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_utilization_synth.pb new file mode 100644 index 0000000000000000000000000000000000000000..6fab4e3897aef35a8388625017045ef7c7e26338 Binary files /dev/null and b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_utilization_synth.pb differ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_utilization_synth.rpt b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_utilization_synth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..c09fe1e73b4ad2f1bfa102273befb08270ddcc73 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_utilization_synth.rpt @@ -0,0 +1,174 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Thu Nov 11 21:46:31 2021 +| Host : DESKTOP-B2469GJ running 64-bit major release (build 9200) +| Command : report_utilization -file inst_rom_utilization_synth.rpt -pb inst_rom_utilization_synth.pb +| Design : inst_rom +| Device : 7k325tffg900-2 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 0 | 0 | 203800 | 0.00 | +| LUT as Logic | 0 | 0 | 203800 | 0.00 | +| LUT as Memory | 0 | 0 | 64000 | 0.00 | +| Slice Registers | 0 | 0 | 407600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 407600 | 0.00 | +| Register as Latch | 0 | 0 | 407600 | 0.00 | +| F7 Muxes | 0 | 0 | 101900 | 0.00 | +| F8 Muxes | 0 | 0 | 50950 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++-------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------+------+-------+-----------+-------+ +| Block RAM Tile | 2 | 0 | 445 | 0.45 | +| RAMB36/FIFO* | 2 | 0 | 445 | 0.45 | +| RAMB36E1 only | 2 | | | | +| RAMB18 | 0 | 0 | 890 | 0.00 | ++-------------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 840 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 500 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| PHY_CONTROL | 0 | 0 | 10 | 0.00 | +| PHASER_REF | 0 | 0 | 10 | 0.00 | +| OUT_FIFO | 0 | 0 | 40 | 0.00 | +| IN_FIFO | 0 | 0 | 40 | 0.00 | +| IDELAYCTRL | 0 | 0 | 10 | 0.00 | +| IBUFDS | 0 | 0 | 480 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 500 | 0.00 | +| OLOGIC | 0 | 0 | 500 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 40 | 0.00 | +| MMCME2_ADV | 0 | 0 | 10 | 0.00 | +| PLLE2_ADV | 0 | 0 | 10 | 0.00 | +| BUFMRCE | 0 | 0 | 20 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 40 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| RAMB36E1 | 2 | Block Memory | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/project.wdf b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/project.wdf new file mode 100644 index 0000000000000000000000000000000000000000..29b9d3625164fd18d119cf17486be4379612aeaa --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/project.wdf @@ -0,0 +1,34 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3139:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:34:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:34:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f345c636c6b646976:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f345c646174615f72616d:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f345c696e73745f726f6d:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:313430:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3136:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3136:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3136:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3136:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3136:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3136:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3136:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6262316439623662383537613436623238383633623139316435353136326561:506172656e742050412070726f6a656374204944:00 +eof:2569069136 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/rundef.js b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/rundef.js new file mode 100644 index 0000000000000000000000000000000000000000..2f0dc865e9fde8edee5e526ca21191fe651a76dd --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "E:/xlinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;E:/xlinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;E:/xlinx/Vivado/2019.2/bin;"; +} else { + PathVal = "E:/xlinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;E:/xlinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;E:/xlinx/Vivado/2019.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log inst_rom.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_rom.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.bat b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.bat new file mode 100644 index 0000000000000000000000000000000000000000..1760626bb4b0da1a578c635144b580e9c28b7c28 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.log b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.log new file mode 100644 index 0000000000000000000000000000000000000000..9214fc0a7658dfb7b5659b0134dfff0c3c45e887 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.log @@ -0,0 +1,455 @@ + +*** Running vivado + with args -log inst_rom.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_rom.tcl + + +****** Vivado v2019.2 (64-bit) + **** SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 + **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source inst_rom.tcl -notrace +Command: synth_design -top inst_rom -part xc7k325tffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' +INFO: [Device 21-403] Loading part xc7k325tffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 4240 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 866.430 ; gain = 235.070 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'inst_rom' [f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/synth/inst_rom.vhd:68] + Parameter C_FAMILY bound to: kintex7 - type: string + Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string + Parameter C_ELABORATION_DIR bound to: ./ - type: string + Parameter C_INTERFACE_TYPE bound to: 0 - type: integer + Parameter C_AXI_TYPE bound to: 1 - type: integer + Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer + Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer + Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer + Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string + Parameter C_HAS_AXI_ID bound to: 0 - type: integer + Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer + Parameter C_MEM_TYPE bound to: 3 - type: integer + Parameter C_BYTE_SIZE bound to: 9 - type: integer + Parameter C_ALGORITHM bound to: 1 - type: integer + Parameter C_PRIM_TYPE bound to: 1 - type: integer + Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer + Parameter C_INIT_FILE_NAME bound to: inst_rom.mif - type: string + Parameter C_INIT_FILE bound to: inst_rom.mem - type: string + Parameter C_USE_DEFAULT_DATA bound to: 0 - type: integer + Parameter C_DEFAULT_DATA bound to: 0 - type: string + Parameter C_HAS_RSTA bound to: 0 - type: integer + Parameter C_RST_PRIORITY_A bound to: CE - type: string + Parameter C_RSTRAM_A bound to: 0 - type: integer + Parameter C_INITA_VAL bound to: 0 - type: string + Parameter C_HAS_ENA bound to: 1 - type: integer + Parameter C_HAS_REGCEA bound to: 0 - type: integer + Parameter C_USE_BYTE_WEA bound to: 0 - type: integer + Parameter C_WEA_WIDTH bound to: 1 - type: integer + Parameter C_WRITE_MODE_A bound to: WRITE_FIRST - type: string + Parameter C_WRITE_WIDTH_A bound to: 32 - type: integer + Parameter C_READ_WIDTH_A bound to: 32 - type: integer + Parameter C_WRITE_DEPTH_A bound to: 2048 - type: integer + Parameter C_READ_DEPTH_A bound to: 2048 - type: integer + Parameter C_ADDRA_WIDTH bound to: 11 - type: integer + Parameter C_HAS_RSTB bound to: 0 - type: integer + Parameter C_RST_PRIORITY_B bound to: CE - type: string + Parameter C_RSTRAM_B bound to: 0 - type: integer + Parameter C_INITB_VAL bound to: 0 - type: string + Parameter C_HAS_ENB bound to: 0 - type: integer + Parameter C_HAS_REGCEB bound to: 0 - type: integer + Parameter C_USE_BYTE_WEB bound to: 0 - type: integer + Parameter C_WEB_WIDTH bound to: 1 - type: integer + Parameter C_WRITE_MODE_B bound to: WRITE_FIRST - type: string + Parameter C_WRITE_WIDTH_B bound to: 32 - type: integer + Parameter C_READ_WIDTH_B bound to: 32 - type: integer + Parameter C_WRITE_DEPTH_B bound to: 2048 - type: integer + Parameter C_READ_DEPTH_B bound to: 2048 - type: integer + Parameter C_ADDRB_WIDTH bound to: 11 - type: integer + Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 0 - type: integer + Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 0 - type: integer + Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 0 - type: integer + Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer + Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer + Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer + Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer + Parameter C_USE_SOFTECC bound to: 0 - type: integer + Parameter C_USE_ECC bound to: 0 - type: integer + Parameter C_EN_ECC_PIPE bound to: 0 - type: integer + Parameter C_READ_LATENCY_A bound to: 1 - type: integer + Parameter C_READ_LATENCY_B bound to: 1 - type: integer + Parameter C_HAS_INJECTERR bound to: 0 - type: integer + Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string + Parameter C_COMMON_CLK bound to: 0 - type: integer + Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer + Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer + Parameter C_USE_URAM bound to: 0 - type: integer + Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer + Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer + Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer + Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer + Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer + Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer + Parameter C_COUNT_36K_BRAM bound to: 2 - type: string + Parameter C_COUNT_18K_BRAM bound to: 0 - type: string + Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 4.8711 mW - type: string +INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_4' declared at 'f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_4' [f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/synth/inst_rom.vhd:232] +INFO: [Synth 8-256] done synthesizing module 'inst_rom' (9#1) [f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/synth/inst_rom.vhd:68] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port CLKB +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[31] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[30] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[29] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[28] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[27] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[26] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[25] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[24] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[23] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[22] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[21] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[20] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[19] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[18] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[17] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[16] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[15] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[14] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[13] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[12] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[11] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[10] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[9] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[8] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[7] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[6] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[5] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[4] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[3] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[2] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[1] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[0] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port SBITERR_I +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DBITERR_I +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[10] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[9] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[8] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[7] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[6] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[5] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[4] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[3] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[2] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[1] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[0] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port SSRA +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port CLKB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port SSRB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ENB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port REGCEB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port WEB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[10] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[9] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[8] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[7] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[6] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[5] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[4] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[3] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[2] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[17] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[16] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[15] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[14] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[13] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[12] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[11] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[10] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[9] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[8] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[7] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[6] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[5] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[4] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[3] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[2] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port SLEEP +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port INJECTSBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port INJECTDBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ECCPIPECE +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ram_rstram_b +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ram_rstreg_b +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRA +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port CLKB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ENB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port REGCEB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port WEB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[10] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[9] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[8] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[7] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[6] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[5] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[4] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1167.242 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_ooc.xdc] for cell 'U0' +Finished Parsing XDC File [f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_ooc.xdc] for cell 'U0' +Parsing XDC File [F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc] +Finished Parsing XDC File [F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.242 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1167.242 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k325tffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for U0. (constraint file F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 840 (col length:140) +BRAMs: 890 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----------+------+ +| |Cell |Count | ++------+-----------+------+ +|1 |RAMB36E1 | 1| +|2 |RAMB36E1_1 | 1| ++------+-----------+------+ + +Report Instance Areas: ++------+---------------------------------------------+----------------------------------------------+------+ +| |Instance |Module |Cells | ++------+---------------------------------------------+----------------------------------------------+------+ +|1 |top | | 2| +|2 | U0 |blk_mem_gen_v8_4_4 | 2| +|3 | inst_blk_mem_gen |blk_mem_gen_v8_4_4_synth | 2| +|4 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top | 2| +|5 | \valid.cstr |blk_mem_gen_generic_cstr | 2| +|6 | \ramloop[0].ram.r |blk_mem_gen_prim_width | 1| +|7 | \prim_init.ram |blk_mem_gen_prim_wrapper_init | 1| +|8 | \ramloop[1].ram.r |blk_mem_gen_prim_width__parameterized0 | 1| +|9 | \prim_init.ram |blk_mem_gen_prim_wrapper_init__parameterized0 | 1| ++------+---------------------------------------------+----------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 1167.242 ; gain = 535.883 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 230 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:51 . Memory (MB): peak = 1167.242 ; gain = 535.883 +Synthesis Optimization Complete : Time (s): cpu = 00:00:52 ; elapsed = 00:00:54 . Memory (MB): peak = 1167.242 ; gain = 535.883 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1167.242 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.242 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +17 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:00:59 . Memory (MB): peak = 1167.242 ; gain = 865.621 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.242 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +WARNING: [Coretcl 2-1488] Problem adding IP cache entry: Directory already exists: f:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/ip/2019.2/9888347cfb290ede +INFO: [Coretcl 2-1174] Renamed 8 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.242 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file inst_rom_utilization_synth.rpt -pb inst_rom_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Thu Nov 11 21:46:31 2021... diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.sh b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.sh new file mode 100644 index 0000000000000000000000000000000000000000..5319028cd6f22bcc67a82ea1b8b71cd0cbcf9d91 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=E:/xlinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;E:/xlinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:E:/xlinx/Vivado/2019.2/bin +else + PATH=E:/xlinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;E:/xlinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:E:/xlinx/Vivado/2019.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log inst_rom.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_rom.tcl diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/vivado.jou b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/vivado.jou new file mode 100644 index 0000000000000000000000000000000000000000..3111c7ac109eca4983d1cce063a51e9a79d004f5 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Thu Nov 11 21:45:28 2021 +# Process ID: 7060 +# Current directory: F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1 +# Command line: vivado.exe -log inst_rom.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_rom.tcl +# Log file: F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.vds +# Journal file: F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1\vivado.jou +#----------------------------------------------------------- +source inst_rom.tcl -notrace diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/vivado.pb b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/vivado.pb new file mode 100644 index 0000000000000000000000000000000000000000..9184096892ec1822bc11c1ff3fb0fe7097d7afd7 Binary files /dev/null and b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/vivado.pb differ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.dcp b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.dcp index 3096addc732423eaa055a108ffae5376590aba07..43daa17c25116bda22ed2f737476870fbd327c25 100644 Binary files a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.dcp and b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.dcp differ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xci b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xci index de07a1ed7a4d88d56fa3ef8d244d73cfd6672599..89de0ad0bc20505f43cabc22d42cbac2471da064 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xci +++ b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xci @@ -172,7 +172,7 @@ false 9 NONE - ../../../../../../TEMU/mips_sc/build/add_inst.coe + e:/add_inst.coe ALL inst_rom false diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xml b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xml index 9d8ac1eb2cea2cfaa5bbf7d008f3a71a51a27fa4..1be8f9ce00af7bceff8fdc7dac066b1ecdd4f7ef 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xml +++ b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xml @@ -1446,24 +1446,6 @@ - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Thu Nov 11 13:00:11 UTC 2021 - - - outputProductCRC - 9:d6f89bdb - - - xilinx_veriloginstantiationtemplate Verilog Instantiation Template @@ -1475,11 +1457,11 @@ GENtimestamp - Thu Nov 11 13:00:10 UTC 2021 + Thu Nov 11 13:45:24 UTC 2021 outputProductCRC - 9:0a6e9b18 + 9:79dc00dd @@ -1495,11 +1477,11 @@ GENtimestamp - Thu Nov 11 13:00:11 UTC 2021 + Thu Nov 11 13:45:24 UTC 2021 outputProductCRC - 9:0a6e9b18 + 9:79dc00dd @@ -1510,7 +1492,7 @@ outputProductCRC - 9:0a6e9b18 + 9:79dc00dd @@ -1526,11 +1508,11 @@ GENtimestamp - Thu Nov 11 13:00:11 UTC 2021 + Thu Nov 11 13:45:24 UTC 2021 outputProductCRC - 9:0a6e9b18 + 9:79dc00dd @@ -1545,11 +1527,11 @@ GENtimestamp - Thu Nov 11 13:00:11 UTC 2021 + Thu Nov 11 13:45:24 UTC 2021 outputProductCRC - 9:6627dbfb + 9:d77ec156 @@ -1565,11 +1547,11 @@ GENtimestamp - Thu Nov 11 13:00:11 UTC 2021 + Thu Nov 11 13:45:24 UTC 2021 outputProductCRC - 9:6627dbfb + 9:d77ec156 @@ -1583,11 +1565,11 @@ GENtimestamp - Thu Nov 11 13:00:11 UTC 2021 + Thu Nov 11 13:45:24 UTC 2021 outputProductCRC - 9:0a6e9b18 + 9:79dc00dd @@ -1601,11 +1583,29 @@ GENtimestamp - Thu Nov 11 13:00:11 UTC 2021 + Thu Nov 11 13:45:24 UTC 2021 + + + outputProductCRC + 9:79dc00dd + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Thu Nov 11 13:46:31 UTC 2021 outputProductCRC - 9:0a6e9b18 + 9:79dc00dd @@ -3542,42 +3542,6 @@ - - xilinx_externalfiles_view_fileset - - inst_rom.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - inst_rom_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - inst_rom_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - inst_rom_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - inst_rom_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - xilinx_veriloginstantiationtemplate_view_fileset @@ -3656,6 +3620,42 @@ text + + xilinx_externalfiles_view_fileset + + inst_rom.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + inst_rom_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + inst_rom_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + inst_rom_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + inst_rom_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. @@ -4145,7 +4145,7 @@ Coe_File - ../../../../../../TEMU/mips_sc/build/add_inst.coe + e:/add_inst.coe diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.v b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.v index f32b8fdde3965d843e9fd1dc9d6b9058b298702a..162fec42f74c408568890c159d5f589ecfda3a8f 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.v +++ b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 -// Date : Fri Oct 29 14:30:24 2021 -// Host : LAPTOP-M01GHSS7 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top inst_rom -prefix -// inst_rom_ inst_rom_sim_netlist.v +// Date : Thu Nov 11 21:46:31 2021 +// Host : DESKTOP-B2469GJ running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.v // Design : inst_rom // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -191,6 +191,7 @@ module inst_rom .web(1'b0)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) module inst_rom_blk_mem_gen_generic_cstr (douta, clka, @@ -218,6 +219,7 @@ module inst_rom_blk_mem_gen_generic_cstr .ena(ena)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module inst_rom_blk_mem_gen_prim_width (douta, clka, @@ -263,6 +265,7 @@ module inst_rom_blk_mem_gen_prim_width__parameterized0 .ena(ena)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) module inst_rom_blk_mem_gen_prim_wrapper_init (douta, clka, @@ -742,6 +745,7 @@ module inst_rom_blk_mem_gen_prim_wrapper_init__parameterized0 .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_top" *) module inst_rom_blk_mem_gen_top (douta, clka, @@ -789,7 +793,7 @@ endmodule (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "2048" *) (* C_WRITE_DEPTH_B = "2048" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "32" *) (* C_WRITE_WIDTH_B = "32" *) (* C_XDEVICEFAMILY = "kintex7" *) -(* downgradeipidentifiedwarnings = "yes" *) +(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *) module inst_rom_blk_mem_gen_v8_4_4 (clka, rsta, @@ -1043,6 +1047,7 @@ module inst_rom_blk_mem_gen_v8_4_4 .ena(ena)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *) module inst_rom_blk_mem_gen_v8_4_4_synth (douta, clka, diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.vhdl b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.vhdl index f58b74f8d4863cec8657d497ca745609b357f482..492a6445f4512ce02f86fc8bdbc4abaed20cb433 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.vhdl +++ b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 --- Date : Fri Oct 29 14:30:24 2021 --- Host : LAPTOP-M01GHSS7 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top inst_rom -prefix --- inst_rom_ inst_rom_sim_netlist.vhdl +-- Date : Thu Nov 11 21:46:31 2021 +-- Host : DESKTOP-B2469GJ running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.vhdl -- Design : inst_rom -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -21,6 +21,8 @@ entity inst_rom_blk_mem_gen_prim_wrapper_init is ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of inst_rom_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end inst_rom_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of inst_rom_blk_mem_gen_prim_wrapper_init is @@ -521,6 +523,8 @@ entity inst_rom_blk_mem_gen_prim_width is ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of inst_rom_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end inst_rom_blk_mem_gen_prim_width; architecture STRUCTURE of inst_rom_blk_mem_gen_prim_width is @@ -569,6 +573,8 @@ entity inst_rom_blk_mem_gen_generic_cstr is ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of inst_rom_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end inst_rom_blk_mem_gen_generic_cstr; architecture STRUCTURE of inst_rom_blk_mem_gen_generic_cstr is @@ -599,6 +605,8 @@ entity inst_rom_blk_mem_gen_top is ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of inst_rom_blk_mem_gen_top : entity is "blk_mem_gen_top"; end inst_rom_blk_mem_gen_top; architecture STRUCTURE of inst_rom_blk_mem_gen_top is @@ -622,6 +630,8 @@ entity inst_rom_blk_mem_gen_v8_4_4_synth is ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of inst_rom_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth"; end inst_rom_blk_mem_gen_v8_4_4_synth; architecture STRUCTURE of inst_rom_blk_mem_gen_v8_4_4_synth is @@ -854,6 +864,8 @@ entity inst_rom_blk_mem_gen_v8_4_4 is attribute C_WRITE_WIDTH_B of inst_rom_blk_mem_gen_v8_4_4 : entity is 32; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of inst_rom_blk_mem_gen_v8_4_4 : entity is "kintex7"; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of inst_rom_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of inst_rom_blk_mem_gen_v8_4_4 : entity is "yes"; end inst_rom_blk_mem_gen_v8_4_4; diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v index 60c2ed360aa0ec11b2339f81a579f641f9d485af..9f3d3e24dc01139eb73287061a395e1bc40c1d24 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v +++ b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 -// Date : Fri Oct 29 14:30:24 2021 -// Host : LAPTOP-M01GHSS7 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top inst_rom -prefix -// inst_rom_ inst_rom_stub.v +// Date : Thu Nov 11 21:46:31 2021 +// Host : DESKTOP-B2469GJ running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v // Design : inst_rom // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl index 279e0b79c4542e4e924a7ce63509d2eefc5a21e9..7d1db92f3cde788c798f0c856ba49ced8a2c25b4 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl +++ b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 --- Date : Fri Oct 29 14:30:24 2021 --- Host : LAPTOP-M01GHSS7 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top inst_rom -prefix --- inst_rom_ inst_rom_stub.vhdl +-- Date : Thu Nov 11 21:46:31 2021 +-- Host : DESKTOP-B2469GJ running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub +-- F:/gitee/Architecture_work/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl -- Design : inst_rom -- Purpose : Stub declaration of top-level module interface -- Device : xc7k325tffg900-2 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/alu.sv b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/alu.sv index d160f3e44c004ab799bb78b6c70bf9d5b48ea1ef..333f4c0f9624de383d5b9ed990359aaec09887d3 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/alu.sv +++ b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/alu.sv @@ -27,19 +27,68 @@ module alu( input logic[31: 0] src2, output logic[31: 0] arithres, output logic[63: 0] mulres, + output logic[31:0] logicres, output logic stallreq_exe ); always_comb begin case(aluop) 8'b00011000: arithres = src1 + src2; //add - 8'b00011011: arithres = src1 - src2; - 8'b00011100: arithres = src1 & src2; - 8'b00011101: arithres = src1 | src2; //ori - 8'b00010100: mulres = $signed(src1) * $signed(src2); //mult - 8'b00000000: mulres[63: 32] = src1; //mthi - 8'b00000001: mulres[31: 0] = src1; //mtlo - 8'b10010000: arithres = src1 + src2; + 8'b00010000: arithres = src1 + src2; //addi + 8'b00010010: arithres = src1 + src2; //addu + 8'b00011001: arithres = src1 + src2; //addiu + 8'b00010011: arithres = src1 - src2; //sub + 8'b00011011: arithres = src1 - src2; //subu + 8'b00100110: begin + if(src1 < src2)begin + logicres = 1; + end + else begin + logicres = 0; + end + end //slt + + 8'b00100000:begin + if(src1 < src2)begin + logicres = 1; + end + else begin + logicres = 0; + end + end //slti + 8'b00100001:begin + if(src1 < src2)begin + logicres = 1; + end + else begin + logicres = 0; + end + end //sltu + 8'b00100111:begin + if(src1 < src2)begin + logicres = 1; + end + else begin + logicres = 0; + end + end //sltiu + 8'b00010100: mulres = src1 * src2; //muit + 8'b00010101: mulres = src1 * src2; //multu + 8'b00011100: arithres = src1 & src2; //and + 8'b00010110: arithres = src1 & src2; //andi + 8'b01000001: arithres = !(src1 | src2); //nor + 8'b01000001: arithres = src1 | src2 ; //or + 8'b00011101: arithres = src1 | src2; //ori + 8'b00011010: arithres = src1 ^ src2; //xor + 8'b01000010: arithres = src1 ^ src2; //xori + 8'b00010001: logicres = src1 << src2; //sll; + 8'b01000100: logicres = src1 << src2; //sllv + 8'b01001000: logicres = src1 >> src2; //sra + 8'b01000011: logicres = src1 >> src2; //srav + 8'b01000110: logicres = src1 >> src2; //srl + 8'b01001100: logicres = src1 >> src2; //srlv + 8'b10010000: arithres = src1 + src2; // + 8'b00000101: arithres = src2; //lui 8'b10010001: arithres = src1 + src2; 8'b10010100: arithres = src1 + src2; 8'b10010011: arithres = src1 + src2; @@ -47,7 +96,7 @@ always_comb begin 8'b10011000: arithres = src1 + src2; 8'b10010101: arithres = src1 + src2; 8'b10011010: arithres = src1 + src2; - 8'b00011101: arithres = src1 | src2; + 8'b00000101: arithres[31:16] = src2; default: begin diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.xpr b/CPU_core/MiniMIPS32/MiniMIPS32.xpr index 88eaf178735eb4988572a3e9a47a2a12a4340a18..ea77c7bccb3267ced0dbb879720ebc10253321f9 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.xpr +++ b/CPU_core/MiniMIPS32/MiniMIPS32.xpr @@ -3,7 +3,7 @@ - +