From 29ff7abe224b1349a7a7e75ddfe5f9411d259b81 Mon Sep 17 00:00:00 2001 From: hua-yi-123 <1342881632@qq.com> Date: Tue, 2 Nov 2021 22:26:09 +0800 Subject: [PATCH 1/3] hit good trip on j.s --- TEMU/mips_sc/src/include/asm/context.h | 200 ++++++++++++++++++ ...13\350\257\225\346\214\207\344\273\244.md" | 2 +- 2 files changed, 201 insertions(+), 1 deletion(-) create mode 100644 TEMU/mips_sc/src/include/asm/context.h diff --git a/TEMU/mips_sc/src/include/asm/context.h b/TEMU/mips_sc/src/include/asm/context.h new file mode 100644 index 0000000..58199f7 --- /dev/null +++ b/TEMU/mips_sc/src/include/asm/context.h @@ -0,0 +1,200 @@ +/************************************************************************** +* * +* PROJECT : MIPS port for uC/OS-II * +* * +* MODULE : CONTEXT.h * +* * +* AUTHOR : Michael Anburaj * +* URL : http://geocities.com/michaelanburaj/ * +* EMAIL: michaelanburaj@hotmail.com * +* * +* PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board * +* * +* TOOL-CHAIN : SDE & Cygnus * +* * +* DESCRIPTION : * +* Context switch macros. * +* * +**************************************************************************/ + + +#ifndef __CONTEXT_H__ +#define __CONTEXT_H__ + + +/* ********************************************************************* */ +/* Module configuration */ + + +/* ********************************************************************* */ +/* Interface macro & data definition */ + +#ifdef __ASSEMBLER__ + + +// push context: at, v0-v1,a0-a3,t0-t9,s0-s7,gp,fp,ra, & pc +#define STORE_REG_RET(Retaddr) \ + .set noat; \ + .set noreorder; \ + subu sp,120; \ + sw ra,0(sp); \ + sw fp,4(sp); \ + sw gp,8(sp); \ + sw t9,12(sp); \ + sw t8,16(sp); \ + sw s7,20(sp); \ + sw s6,24(sp); \ + sw s5,28(sp); \ + sw s4,32(sp); \ + sw s3,36(sp); \ + sw s2,40(sp); \ + sw s1,44(sp); \ + sw s0,48(sp); \ + sw t7,52(sp); \ + sw t6,56(sp); \ + sw t5,60(sp); \ + sw t4,64(sp); \ + sw t3,68(sp); \ + sw t2,72(sp); \ + sw t1,76(sp); \ + sw t0,80(sp); \ + sw a3,84(sp); \ + sw a2,88(sp); \ + sw a1,92(sp); \ + sw a0,96(sp); \ + sw v1,100(sp); \ + sw v0,104(sp); \ + sw AT,108(sp); \ + mfc0 t0,c0_status; \ + sw t0,112(sp); \ + sw Retaddr,116(sp); \ + .set at + +// pop context (normal execution): at, v0-v1,a0-a3,t0-t9,s0-s7,gp,fp,ra, & pc +#define RESTORE_REG_RET() \ + .set noat; \ + .set noreorder; \ + lw ra,0(sp); \ + lw fp,4(sp); \ + lw gp,8(sp); \ + lw t9,12(sp); \ + lw t8,16(sp); \ + lw s7,20(sp); \ + lw s6,24(sp); \ + lw s5,28(sp); \ + lw s4,32(sp); \ + lw s3,36(sp); \ + lw s2,40(sp); \ + lw s1,44(sp); \ + lw s0,48(sp); \ + lw t7,52(sp); \ + lw t6,56(sp); \ + lw t5,60(sp); \ + lw t4,64(sp); \ + lw t3,68(sp); \ + lw t2,72(sp); \ + lw t1,76(sp); \ + lw t0,80(sp); \ + lw a3,84(sp); \ + lw a2,88(sp); \ + lw a1,92(sp); \ + lw a0,96(sp); \ + lw v1,100(sp); \ + lw v0,104(sp); \ + lw AT,108(sp); \ + lw k0,112(sp); \ + mtc0 k0,c0_status; \ + lw k0,116(sp); \ + addu sp,120; \ + jr k0; \ + nop; \ + .set at + +// pop context: at, v0-v1,a0-a3,t0-t9,s0-s7,gp,fp,ra, & pc +#define RESTORE_REG_ERET() \ + .set noat; \ + .set noreorder; \ + lw ra,0(sp); \ + lw fp,4(sp); \ + lw gp,8(sp); \ + lw t9,12(sp); \ + lw t8,16(sp); \ + lw s7,20(sp); \ + lw s6,24(sp); \ + lw s5,28(sp); \ + lw s4,32(sp); \ + lw s3,36(sp); \ + lw s2,40(sp); \ + lw s1,44(sp); \ + lw s0,48(sp); \ + lw t7,52(sp); \ + lw t6,56(sp); \ + lw t5,60(sp); \ + lw t4,64(sp); \ + lw t3,68(sp); \ + lw t2,72(sp); \ + lw t1,76(sp); \ + lw t0,80(sp); \ + lw a3,84(sp); \ + lw a2,88(sp); \ + lw a1,92(sp); \ + lw a0,96(sp); \ + lw v1,100(sp); \ + lw v0,104(sp); \ + lw AT,108(sp); \ + lw k0,112(sp); \ + mtc0 k0,c0_status; \ + lw k0,116(sp); \ + mtc0 k0,c0_epc; \ + addu sp,120; \ + eret; \ + nop; \ + .set at + +#else +struct pt_regs { + int ra; + int fp; + int gp; + int t9; + int t8; + int s7; + int s6; + int s5; + int s4; + int s3; + int s2; + int s1; + int s0; + int t7; + int t6; + int t5; + int t4; + int t3; + int t2; + int t1; + int t0; + int a3; + int a2; + int a1; + int a0; + int v1; + int v0; + int AT; + int status; + int epc; +}; +#endif /* _ASSEMBLER_ */ + + +/* ********************************************************************* */ +/* Interface function definition */ + + +/* ********************************************************************* */ + +#ifdef __cplusplus +} +#endif + +#endif /*__CONTEXT_H__*/ \ No newline at end of file diff --git "a/TEMU/mips_sc/src/\346\265\213\350\257\225\346\214\207\344\273\244.md" "b/TEMU/mips_sc/src/\346\265\213\350\257\225\346\214\207\344\273\244.md" index 662e3d2..7562c57 100644 --- "a/TEMU/mips_sc/src/\346\265\213\350\257\225\346\214\207\344\273\244.md" +++ "b/TEMU/mips_sc/src/\346\265\213\350\257\225\346\214\207\344\273\244.md" @@ -36,7 +36,7 @@ | bltz | | | | bgezal | | | | bltzal | | | -| j | | | +| j | | 1 | | jal | for | 1 | | jr | for | 1 | | jalr | | | -- Gitee From 1db59041b986d0202714f1b909dbb8ac7e46cb13 Mon Sep 17 00:00:00 2001 From: hua-yi-123 <1342881632@qq.com> Date: Tue, 2 Nov 2021 23:09:08 +0800 Subject: [PATCH 2/3] bgezal.s --- .gitignore | 49 -- .../MiniMIPS32_SYS_tb_behav.wcfg | 379 ++++++++++ .../sim_1/behav/xsim/MiniMIPS32_SYS_tb.tcl | 11 + .../behav/xsim/MiniMIPS32_SYS_tb_behav.wdb | Bin 0 -> 214102 bytes .../behav/xsim/MiniMIPS32_SYS_tb_vlog.prj | 31 + .../sim_1/behav/xsim/add_inst.coe | 55 ++ .../sim_1/behav/xsim/and_inst.coe | 4 + .../sim_1/behav/xsim/compile.bat | 25 + .../sim_1/behav/xsim/compile.log | 10 + .../sim_1/behav/xsim/elaborate.bat | 24 + .../sim_1/behav/xsim/elaborate.log | 50 ++ .../MiniMIPS32.sim/sim_1/behav/xsim/glbl.v | 71 ++ .../sim_1/behav/xsim/inst_rom.mif | 53 ++ .../sim_1/behav/xsim/simulate.bat | 24 + .../sim_1/behav/xsim/simulate.log | 7 + .../sim_1/behav/xsim/webtalk.jou | 12 + .../sim_1/behav/xsim/webtalk.log | 13 + .../sim_1/behav/xsim/webtalk_12844.backup.jou | 12 + .../sim_1/behav/xsim/webtalk_12844.backup.log | 13 + .../MiniMIPS32.sim/sim_1/behav/xsim/xelab.pb | Bin 0 -> 7383 bytes .../Compile_Options.txt | 1 + .../TempBreakPointFile.txt | 1 + .../obj/xsim_0.win64.obj | Bin 0 -> 956334 bytes .../MiniMIPS32_SYS_tb_behav/obj/xsim_1.c | 680 ++++++++++++++++++ .../obj/xsim_1.win64.obj | Bin 0 -> 29943 bytes .../webtalk/.xsim_webtallk.info | 5 + .../webtalk/usage_statistics_ext_xsim.wdm | 38 + .../webtalk/xsim_webtalk.tcl | 32 + .../xsim.dir/MiniMIPS32_SYS_tb_behav/xsim.dbg | Bin 0 -> 183744 bytes .../xsim.dir/MiniMIPS32_SYS_tb_behav/xsim.mem | Bin 0 -> 62346 bytes .../MiniMIPS32_SYS_tb_behav/xsim.reloc | Bin 0 -> 52162 bytes .../xsim.dir/MiniMIPS32_SYS_tb_behav/xsim.rlx | 12 + .../MiniMIPS32_SYS_tb_behav/xsim.rtti | Bin 0 -> 547 bytes .../MiniMIPS32_SYS_tb_behav/xsim.svtype | Bin 0 -> 147 bytes .../MiniMIPS32_SYS_tb_behav/xsim.type | Bin 0 -> 24 bytes .../MiniMIPS32_SYS_tb_behav/xsim.xdbg | Bin 0 -> 144096 bytes .../MiniMIPS32_SYS_tb_behav/xsimSettings.ini | 50 ++ .../MiniMIPS32_SYS_tb_behav/xsimcrash.log | 0 .../MiniMIPS32_SYS_tb_behav/xsimk.exe | Bin 0 -> 908644 bytes .../MiniMIPS32_SYS_tb_behav/xsimkernel.log | 7 + .../xil_defaultlib/@mini@m@i@p@s32.sdb | Bin 0 -> 15627 bytes .../xil_defaultlib/@mini@m@i@p@s32_@s@y@s.sdb | Bin 0 -> 2322 bytes .../@mini@m@i@p@s32_@s@y@s_tb.sdb | Bin 0 -> 1369 bytes .../xsim/xsim.dir/xil_defaultlib/alu.sdb | Bin 0 -> 1678 bytes .../xsim/xsim.dir/xil_defaultlib/clkdiv.sdb | Bin 0 -> 1229 bytes .../xil_defaultlib/clkdiv_clk_wiz.sdb | Bin 0 -> 4913 bytes .../xsim/xsim.dir/xil_defaultlib/data_ram.sdb | Bin 0 -> 6908 bytes .../xsim/xsim.dir/xil_defaultlib/dcu.sdb | Bin 0 -> 30429 bytes .../xsim.dir/xil_defaultlib/exemem_reg.sdb | Bin 0 -> 3104 bytes .../xsim/xsim.dir/xil_defaultlib/glbl.sdb | Bin 0 -> 3779 bytes .../xsim/xsim.dir/xil_defaultlib/hilo.sdb | Bin 0 -> 1536 bytes .../xsim.dir/xil_defaultlib/idexe_reg.sdb | Bin 0 -> 3724 bytes .../xsim/xsim.dir/xil_defaultlib/ifid_reg.sdb | Bin 0 -> 1518 bytes .../xsim/xsim.dir/xil_defaultlib/inst_rom.sdb | Bin 0 -> 6628 bytes .../xsim/xsim.dir/xil_defaultlib/mcu.sdb | Bin 0 -> 8011 bytes .../xsim.dir/xil_defaultlib/memwb_reg.sdb | Bin 0 -> 2647 bytes .../xsim/xsim.dir/xil_defaultlib/mux2.sdb | Bin 0 -> 959 bytes .../xsim/xsim.dir/xil_defaultlib/mux3.sdb | Bin 0 -> 1380 bytes .../xsim/xsim.dir/xil_defaultlib/mux4.sdb | Bin 0 -> 1479 bytes .../xsim/xsim.dir/xil_defaultlib/mux5.sdb | Bin 0 -> 1614 bytes .../xsim/xsim.dir/xil_defaultlib/pc_reg.sdb | Bin 0 -> 1523 bytes .../xsim/xsim.dir/xil_defaultlib/register.sdb | Bin 0 -> 4869 bytes .../xsim/xsim.dir/xil_defaultlib/scu.sdb | Bin 0 -> 1066 bytes .../xil_defaultlib/xil_defaultlib.rlx | 25 + .../MiniMIPS32.sim/sim_1/behav/xsim/xsim.ini | 445 ++++++++++++ .../sim_1/behav/xsim/xsim.ini.bak | 445 ++++++++++++ .../MiniMIPS32.sim/sim_1/behav/xsim/xvlog.log | 10 + .../MiniMIPS32.sim/sim_1/behav/xsim/xvlog.pb | Bin 0 -> 1822 bytes TEMU/build/temu | Bin 112704 -> 111272 bytes TEMU/inst.bin | Bin 844 -> 212 bytes TEMU/log.txt | 138 ++-- TEMU/mips_sc/build/add.o | Bin 0 -> 853 bytes TEMU/mips_sc/build/bltzal.o | Bin 0 -> 1080 bytes TEMU/mips_sc/build/convert | Bin 8824 -> 8920 bytes TEMU/mips_sc/build/jal.o | Bin 0 -> 1612 bytes TEMU/mips_sc/src/Makefile.testcase | 1 - TEMU/mips_sc/src/include/inst_def.h | 9 + TEMU/mips_sc/src/include/inst_test.h | 4 +- TEMU/mips_sc/src/inst/bgezal.S | 217 ++++++ TEMU/mips_sc/src/inst/bltzal.S | 202 +++++- TEMU/mips_sc/src/inst/jal.S | 201 +----- ...13\350\257\225\346\214\207\344\273\244.md" | 2 +- 82 files changed, 3030 insertions(+), 338 deletions(-) delete mode 100644 .gitignore create mode 100644 CPU_core/MiniMIPS32/MiniMIPS32.sim/MiniMIPS32_SYS_tb_behav.wcfg create mode 100644 CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/MiniMIPS32_SYS_tb.tcl create mode 100644 CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/MiniMIPS32_SYS_tb_behav.wdb create mode 100644 CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/MiniMIPS32_SYS_tb_vlog.prj create mode 100644 CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/add_inst.coe create mode 100644 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CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pc_reg.sdb create mode 100644 CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/register.sdb create mode 100644 CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/scu.sdb create mode 100644 CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx create mode 100644 CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.ini create mode 100644 CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.ini.bak create mode 100644 CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xvlog.log create mode 100644 CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xvlog.pb create mode 100644 TEMU/mips_sc/build/add.o create mode 100644 TEMU/mips_sc/build/bltzal.o create mode 100644 TEMU/mips_sc/build/jal.o create mode 100644 TEMU/mips_sc/src/inst/bgezal.S diff --git a/.gitignore b/.gitignore deleted file mode 100644 index 43aa0b6..0000000 --- a/.gitignore +++ /dev/null @@ -1,49 +0,0 @@ -# Prerequisites -*.d - -# Compiled Object files -*.slo -*.lo -*.o -*.obj - -# Precompiled Headers -*.gch -*.pch - -# Compiled Dynamic libraries -*.so -*.dylib -*.dll - -# Fortran module files -*.mod -*.smod - -# Compiled Static libraries -*.lai -*.la -*.a -*.lib - -# Executables -*.exe -*.out -*.app -workspace.code-workspace -CPU_core/MiniMIPS32/MiniMIPS32.xpr -CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/gui_handlers.wdf -CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/java_command_handlers.wdf -CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/project.wpc -CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/webtalk_pa.xml -CPU_core/MiniMIPS32/MiniMIPS32.hw/MiniMIPS32.lpr -CPU_core/MiniMIPS32/MiniMIPS32.sim/* -# CPU_core/MiniMIPS32/MiniMIPS32.runs/* -# CPU_core/MiniMIPS32/MiniMIPS32.cache/* -TEMU/mips_sc/build -TEMU/build -TEMU/data.bin -TEMU/inst.bin -TEMU/mips_sc/src/Makefile.testcase/ -# CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/ -# CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/ \ No newline at end of file diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/MiniMIPS32_SYS_tb_behav.wcfg b/CPU_core/MiniMIPS32/MiniMIPS32.sim/MiniMIPS32_SYS_tb_behav.wcfg new file mode 100644 index 0000000..4b9b0b5 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/MiniMIPS32_SYS_tb_behav.wcfg @@ -0,0 +1,379 @@ + + + + + + + + + + + + + + + + + + + + + + + + cpu_clk + cpu_clk + + + cpu_rst_n + cpu_rst_n + + + iaddr[31:0] + iaddr[31:0] + + + ice + ice + + + inst[31:0] + inst[31:0] + + + dout[31:0] + dout[31:0] + + + dce + dce + + + daddr[31:0] + daddr[31:0] + + + we[3:0] + we[3:0] + + + din[31:0] + din[31:0] + + + out_ice + out_ice + + + stall[3:0] + stall[3:0] + + + normal_addr[31:0] + normal_addr[31:0] + + + pc_addr[31:0] + pc_addr[31:0] + + + out_iaddr[31:0] + out_iaddr[31:0] + + + out_addr_4[31:0] + out_addr_4[31:0] + + + far_addr[31:0] + far_addr[31:0] + + + short_addr[31:0] + short_addr[31:0] + + + absolute_addr[31:0] + absolute_addr[31:0] + + + id_inst[31:0] + id_inst[31:0] + + + id_inst_i[31:0] + id_inst_i[31:0] + + + id_pc_4[31:0] + id_pc_4[31:0] + + + id_src1[31:0] + id_src1[31:0] + + + rs[4:0] + rs[4:0] + + + rt[4:0] + rt[4:0] + + + id_rd_before[4:0] + id_rd_before[4:0] + + + id_rd[4:0] + id_rd[4:0] + + + rd1[31:0] + rd1[31:0] + + + rd2[31:0] + rd2[31:0] + + + id_rd1[31:0] + id_rd1[31:0] + + + id_rd2[31:0] + id_rd2[31:0] + + + id_res[31:0] + id_res[31:0] + + + id_alutype[1:0] + id_alutype[1:0] + + + exe_alutype[1:0] + exe_alutype[1:0] + + + id_aluop[7:0] + id_aluop[7:0] + + + exe_aluop[7:0] + exe_aluop[7:0] + + + id_wreg + id_wreg + + + id_whilo + id_whilo + + + id_shift + id_shift + + + rtsel + rtsel + + + sext + sext + + + upper + upper + + + immsel + immsel + + + id_mreg + id_mreg + + + fwrd1 + fwrd1 + + + fwrd2 + fwrd2 + + + equ + equ + + + stallreq_id + stallreq_id + + + jal + jal + + + unsigned_imm[31:0] + unsigned_imm[31:0] + + + signed_imm[31:0] + signed_imm[31:0] + + + out_imm[31:0] + out_imm[31:0] + + + ans_imm[31:0] + ans_imm[31:0] + + + imm[15:0] + imm[15:0] + + + jtsel[1:0] + jtsel[1:0] + + + arithres[31:0] + arithres[31:0] + + + moveres[31:0] + moveres[31:0] + + + exe_res[31:0] + exe_res[31:0] + + + exe_src1[31:0] + exe_src1[31:0] + + + exe_src2[31:0] + exe_src2[31:0] + + + hi_o[31:0] + hi_o[31:0] + + + lo_o[31:0] + lo_o[31:0] + + + exe_rd2[31:0] + exe_rd2[31:0] + + + exe_pc_8[31:0] + exe_pc_8[31:0] + + + exe_mulres[63:0] + exe_mulres[63:0] + + + wb_mulres[63:0] + wb_mulres[63:0] + + + mulres[63:0] + mulres[63:0] + + + exe_divres[63:0] + exe_divres[63:0] + + + exe_rd[4:0] + exe_rd[4:0] + + + exe_whilo + exe_whilo + + + exe_wreg + exe_wreg + + + wb_whilo + wb_whilo + + + exe_mreg + exe_mreg + + + stallreq_exe + stallreq_exe + + + mem_whilo + mem_whilo + + + mem_wreg + mem_wreg + + + mem_mreg + mem_mreg + + + mem_rd[4:0] + mem_rd[4:0] + + + mem_res[31:0] + mem_res[31:0] + + + mem_rd2[31:0] + mem_rd2[31:0] + + + mem_mulres[63:0] + mem_mulres[63:0] + + + mem_aluop[7:0] + mem_aluop[7:0] + + + mem_dre[3:0] + mem_dre[3:0] + + + wb_mreg + wb_mreg + + + wb_wreg + wb_wreg + + + wb_rd[4:0] + wb_rd[4:0] + + + wb_dout[31:0] + wb_dout[31:0] + + + wb_res[31:0] + wb_res[31:0] + + + wd[31:0] + wd[31:0] + + diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/MiniMIPS32_SYS_tb.tcl b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/MiniMIPS32_SYS_tb.tcl new file mode 100644 index 0000000..4719c2d --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/MiniMIPS32_SYS_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1ms diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/MiniMIPS32_SYS_tb_behav.wdb b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/MiniMIPS32_SYS_tb_behav.wdb new file mode 100644 index 0000000000000000000000000000000000000000..c1e7506db7999694319a8730958ec1e8feccf405 GIT binary patch literal 214102 zcmeF42YgjU_QxMq?AWnCz=Bvvc_~;)1EK+9LbW~8fM}X26f1VDAU1R@*wMASDt6Y2 z9eY>o*jCoHu)CK3?|1J^a^B?4NwOPvb^nJ9>x4n%`I_I9L*% zw*GH#O}-y!=AnU+NF}u6^K*AEm{wKS+)9QAmS1S@V@4RgxeqGDjZk#V#NvYJu)-qT zAmI+_#*Xsjx$vDPe;;Ai8E zmJw^!l&Z#nO%}m+<|^0@BG}tp7o=bnq=>UTQ$h)6d>p_rMd49+%+zHdfRQ#=*H%T= z!%4Cj_cd497!%5XF|r(OjLFKN-32tLU4Rx5xDw;H82?)1KX3dsO>FtbpK1IXjBlDq z$(S*P=8DiW>PVDXh8tkYNj9nc+~H_Uu?U;ex5)Y;aJQn8mb}s{vJ~xg_TIfBOHOSs zv#;zGnf+j|$igQ>ng0~dpY9czkLxIBBl0pxI$Fiyt4AVzO)m%%V*Yz@OB`$+iEJD8 zpvbm3rJQKe85B5d^ym~EhAdiPTpmIu=`9%70GM{RL2 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zGq&?39|a$8)6c{*2kL18HidHVVW=enmC>FmdjX7Rr-I97bK?h?53Bg=Get0UXTI%0 zF;OHwt*?g||QF z+uBd_abm<`TmnM(Vu*G;WP#>NI?cE6`%6EF25wFkbb~95PSZ%mmW6lW?2hz9@;F^r z(;|haKO^op3^9Wx(h)SwC|qU{k{#a=m>Ku45U!{zisAgqiiBq(Mq82C_UmeQ*Mf(A zq0hB1St-c+&WXZ#5Lfd&B(X6vDZwYwk6fE^r71U&&(rV6;LlTPF23fl1>*_rtl8#>UKf8^?mGdS1PXyb`w9 z{&@MTzoE|^-ef+m4>Ugrx2q)&OPF}G6cxMVd{tfk<=&<!jy5>lbsSDerspd5P1_bt#YS_p`6y%M#G_oaw^At|`>I<| zdB-`dtQfcciW%-NalYmSo$jc)Uc$>6ailer7j~v$>JN11cEV9rN$5n6so7d8gtIr0 zQ;w{yf?eTdViDxDSR_EUUtk*8o!huLEW*K~%7)tvy^sX-vj8Y})VbDE*Cx{F3|=#p zBPy2mvK)`iXl$k>doZMPwxJBoc7Ky``0P8YbY{W=E;E*Eh$C1g*rwaDZB|LEIhr+{ zi&L*4TBMb9%X>dud6c1Ox^V6-->0%Kumt};%1VxF>Sb9+vB}-}Ok4pwo;3H$r2kKr M&2WFTj*!9mHx|*1pa1{> literal 0 HcmV?d00001 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/MiniMIPS32_SYS_tb_vlog.prj b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/MiniMIPS32_SYS_tb_vlog.prj new file mode 100644 index 0000000..0ced920 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/MiniMIPS32_SYS_tb_vlog.prj @@ -0,0 +1,31 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib --include "../../../../MiniMIPS32.srcs/sources_1/ip/clkdiv" \ +"../../../../MiniMIPS32.srcs/sources_1/ip/data_ram/sim/data_ram.v" \ +"../../../../MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v" \ +"../../../../MiniMIPS32.srcs/sources_1/ip/clkdiv/clkdiv_clk_wiz.v" \ +"../../../../MiniMIPS32.srcs/sources_1/ip/clkdiv/clkdiv.v" \ +"../../../../MiniMIPS32.srcs/sources_1/new/MiniMIPS32_SYS.v" \ + +sv xil_defaultlib --include "../../../../MiniMIPS32.srcs/sources_1/ip/clkdiv" \ +"../../../../MiniMIPS32.srcs/sources_1/new/MiniMIPS32.sv" \ +"../../../../MiniMIPS32.srcs/sources_1/new/alu.sv" \ +"../../../../MiniMIPS32.srcs/sources_1/new/dcu.sv" \ +"../../../../MiniMIPS32.srcs/sources_1/new/exemem_reg.sv" \ +"../../../../MiniMIPS32.srcs/sources_1/new/hilo.sv" \ +"../../../../MiniMIPS32.srcs/sources_1/new/idexe_reg.sv" \ +"../../../../MiniMIPS32.srcs/sources_1/new/ifid_reg.sv" \ +"../../../../MiniMIPS32.srcs/sources_1/new/mcu.sv" \ +"../../../../MiniMIPS32.srcs/sources_1/new/memwb_reg.sv" \ +"../../../../MiniMIPS32.srcs/sources_1/new/mux.sv" \ +"../../../../MiniMIPS32.srcs/sources_1/new/pc_reg.sv" \ +"../../../../MiniMIPS32.srcs/sources_1/new/register.sv" \ +"../../../../MiniMIPS32.srcs/sources_1/new/scu.sv" \ + +verilog xil_defaultlib --include "../../../../MiniMIPS32.srcs/sources_1/ip/clkdiv" \ +"../../../../MiniMIPS32.srcs/sim_1/new/MiniMIPS32_SYS_tb.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/add_inst.coe b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/add_inst.coe new file mode 100644 index 0000000..c75f627 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/add_inst.coe @@ -0,0 +1,55 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +8004083c +04ff0835 +9340093c +04322935 +20800901 +1445123c +08315236 +2c001216 +00000000 +192a083c +40dd0835 +79a8093c +e0712935 +20800901 +93d2123c +204f5236 +23001216 +00000000 +6180083c +60330835 +ad42093c +1df92935 +20800901 +0fc3123c +7d2c5236 +1a001216 +00000000 +ec5b083c +e2250835 +6ef9093c +e4df2935 +20800901 +5b55123c +c6055236 +11001216 +00000000 +b970083c +00a20835 +bfd9093c +00492935 +20800901 +784a123c +00eb5236 +08001216 +00000000 +00000824 +00000924 +20800901 +00001224 +02001216 +00000000 +0000004a +3f000000 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/and_inst.coe b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/and_inst.coe new file mode 100644 index 0000000..80a48b2 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/and_inst.coe @@ -0,0 +1,4 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +24182200 +24182200 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/compile.bat b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/compile.bat new file mode 100644 index 0000000..d63851f --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/compile.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Fri Oct 29 12:20:13 +0800 2021 +REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvlog --incr --relax -prj MiniMIPS32_SYS_tb_vlog.prj" +call xvlog --incr --relax -prj MiniMIPS32_SYS_tb_vlog.prj -log xvlog.log +call type xvlog.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/compile.log b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/compile.log new file mode 100644 index 0000000..370669e --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/compile.log @@ -0,0 +1,10 @@ +INFO: [VRFC 10-2263] Analyzing Verilog file "F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/data_ram/sim/data_ram.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module data_ram +INFO: [VRFC 10-2263] Analyzing Verilog file "F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module inst_rom +INFO: [VRFC 10-2263] Analyzing Verilog file "F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/clkdiv/clkdiv_clk_wiz.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module clkdiv_clk_wiz +INFO: [VRFC 10-2263] Analyzing Verilog file "F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/clkdiv/clkdiv.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module clkdiv +INFO: [VRFC 10-2263] Analyzing Verilog file "F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32_SYS.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module MiniMIPS32_SYS diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/elaborate.bat b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/elaborate.bat new file mode 100644 index 0000000..c258528 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/elaborate.bat @@ -0,0 +1,24 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Fri Oct 29 12:20:15 +0800 2021 +REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +echo "xelab -wto bb1d9b6b857a46b28863b191d55162ea --incr --debug typical --relax --mt 2 -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot MiniMIPS32_SYS_tb_behav xil_defaultlib.MiniMIPS32_SYS_tb xil_defaultlib.glbl -log elaborate.log" +call xelab -wto bb1d9b6b857a46b28863b191d55162ea --incr --debug typical --relax --mt 2 -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot MiniMIPS32_SYS_tb_behav xil_defaultlib.MiniMIPS32_SYS_tb xil_defaultlib.glbl -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/elaborate.log b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/elaborate.log new file mode 100644 index 0000000..073aa28 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/elaborate.log @@ -0,0 +1,50 @@ +Vivado Simulator 2019.2 +Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved. +Running: E:/xlinx/Vivado/2019.2/bin/unwrapped/win64.o/xelab.exe -wto bb1d9b6b857a46b28863b191d55162ea --incr --debug typical --relax --mt 2 -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot MiniMIPS32_SYS_tb_behav xil_defaultlib.MiniMIPS32_SYS_tb xil_defaultlib.glbl -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Pass Through NonSizing Optimizer +WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 11 for port 'addra' [F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32_SYS.v:37] +WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 32 for port 'D1' [F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32.sv:138] +WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 32 for port 'D0' [F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32.sv:139] +WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'D1' [F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32.sv:152] +WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 32 for port 'D0' [F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32.sv:154] +WARNING: [VRFC 10-3091] actual bit length 64 differs from formal bit length 32 for port 'D0' [F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32.sv:222] +WARNING: [VRFC 10-5021] port 're1' is not connected on this instance [F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32.sv:123] +WARNING: [VRFC 10-3823] variable 'sll' might have multiple concurrent drivers [F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/dcu.sv:108] +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling module unisims_ver.IBUFDS +Compiling module unisims_ver.MMCME2_ADV(CLKIN1_PERIOD=5.0,CLK... +Compiling module unisims_ver.BUFG +Compiling module xil_defaultlib.clkdiv_clk_wiz +Compiling module xil_defaultlib.clkdiv +Compiling module blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_output_stage(... +Compiling module blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_softecc_outpu... +Compiling module blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_mem_module(C_... +Compiling module blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4(C_FAMILY="kin... +Compiling module xil_defaultlib.inst_rom +Compiling module blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_mem_module(C_... +Compiling module blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4(C_FAMILY="kin... +Compiling module xil_defaultlib.data_ram +Compiling module xil_defaultlib.pc_reg +Compiling module xil_defaultlib.mux4(width=32) +Compiling module xil_defaultlib.mux2(width=32) +Compiling module xil_defaultlib.ifid_reg +Compiling module xil_defaultlib.dcu +Compiling module xil_defaultlib.register +Compiling module xil_defaultlib.idexe_reg +Compiling module xil_defaultlib.alu +Compiling module xil_defaultlib.hilo +Compiling module xil_defaultlib.scu +Compiling module xil_defaultlib.mux3(width=32) +Compiling module xil_defaultlib.exemem_reg +Compiling module xil_defaultlib.mcu +Compiling module xil_defaultlib.memwb_reg +Compiling module xil_defaultlib.MiniMIPS32 +Compiling module xil_defaultlib.MiniMIPS32_SYS +Compiling module xil_defaultlib.MiniMIPS32_SYS_tb +Compiling module xil_defaultlib.glbl +Built simulation snapshot MiniMIPS32_SYS_tb_behav diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/glbl.v b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/inst_rom.mif b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/inst_rom.mif new file mode 100644 index 0000000..a4938bd --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/inst_rom.mif @@ -0,0 +1,53 @@ +10000000000001000000100000111100 +00000100111111110000100000110101 +10010011010000000000100100111100 +00000100001100100010100100110101 +00100000100000000000100100000001 +00010100010001010001001000111100 +00001000001100010101001000110110 +00101100000000000001001000010110 +00000000000000000000000000000000 +00011001001010100000100000111100 +01000000110111010000100000110101 +01111001101010000000100100111100 +11100000011100010010100100110101 +00100000100000000000100100000001 +10010011110100100001001000111100 +00100000010011110101001000110110 +00100011000000000001001000010110 +00000000000000000000000000000000 +01100001100000000000100000111100 +01100000001100110000100000110101 +10101101010000100000100100111100 +00011101111110010010100100110101 +00100000100000000000100100000001 +00001111110000110001001000111100 +01111101001011000101001000110110 +00011010000000000001001000010110 +00000000000000000000000000000000 +11101100010110110000100000111100 +11100010001001010000100000110101 +01101110111110010000100100111100 +11100100110111110010100100110101 +00100000100000000000100100000001 +01011011010101010001001000111100 +11000110000001010101001000110110 +00010001000000000001001000010110 +00000000000000000000000000000000 +10111001011100000000100000111100 +00000000101000100000100000110101 +10111111110110010000100100111100 +00000000010010010010100100110101 +00100000100000000000100100000001 +01111000010010100001001000111100 +00000000111010110101001000110110 +00001000000000000001001000010110 +00000000000000000000000000000000 +00000000000000000000100000100100 +00000000000000000000100100100100 +00100000100000000000100100000001 +00000000000000000001001000100100 +00000010000000000001001000010110 +00000000000000000000000000000000 +00000000000000000000000001001010 +00111111000000000000000000000000 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/simulate.bat b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/simulate.bat new file mode 100644 index 0000000..c3a6376 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/simulate.bat @@ -0,0 +1,24 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Fri Oct 29 12:20:21 +0800 2021 +REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +echo "xsim MiniMIPS32_SYS_tb_behav -key {Behavioral:sim_1:Functional:MiniMIPS32_SYS_tb} -tclbatch MiniMIPS32_SYS_tb.tcl -view F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/MiniMIPS32_SYS_tb_behav.wcfg -log simulate.log" +call xsim MiniMIPS32_SYS_tb_behav -key {Behavioral:sim_1:Functional:MiniMIPS32_SYS_tb} -tclbatch MiniMIPS32_SYS_tb.tcl -view F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/MiniMIPS32_SYS_tb_behav.wcfg -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/simulate.log b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/simulate.log new file mode 100644 index 0000000..6de08fa --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/simulate.log @@ -0,0 +1,7 @@ +Vivado Simulator 2019.2 +Time resolution is 1 ps + Block Memory Generator module loading initial data... + Block Memory Generator data initialization complete. +Block Memory Generator module MiniMIPS32_SYS_tb.SoC.inst_rom0.inst.native_mem_module.blk_mem_gen_v8_4_4_inst is using a behavioral model for simulation which will not precisely model memory collision behavior. +Block Memory Generator module MiniMIPS32_SYS_tb.SoC.data_ram_0.inst.native_mem_module.blk_mem_gen_v8_4_4_inst is using a behavioral model for simulation which will not precisely model memory collision behavior. +$stop called at time : 700 ns : File "F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sim_1/new/MiniMIPS32_SYS_tb.v" Line 26 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.jou b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..9065b5d --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Fri Oct 29 12:18:47 2021 +# Process ID: 23084 +# Current directory: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log new file mode 100644 index 0000000..6e1a36c --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Fri Oct 29 12:18:47 2021 +# Process ID: 23084 +# Current directory: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Fri Oct 29 12:18:47 2021... diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_12844.backup.jou b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_12844.backup.jou new file mode 100644 index 0000000..454eb38 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_12844.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Fri Oct 29 12:18:02 2021 +# Process ID: 12844 +# Current directory: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_12844.backup.log b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_12844.backup.log new file mode 100644 index 0000000..5d069e5 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_12844.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Fri Oct 29 12:18:02 2021 +# Process ID: 12844 +# Current directory: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source 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b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/obj/xsim_1.c @@ -0,0 +1,680 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_244(char*, char *); +extern void execute_245(char*, char *); +extern void execute_246(char*, char *); +extern void execute_855(char*, char *); +extern void execute_856(char*, char *); +extern void execute_857(char*, char *); +extern void execute_849(char*, char *); +extern void execute_850(char*, char *); +extern void execute_851(char*, char *); +extern void execute_852(char*, char *); +extern void execute_853(char*, char *); +extern void execute_854(char*, char *); +extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +extern void execute_332(char*, char *); +extern void execute_335(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_28(char*, char *); +extern void execute_29(char*, char *); +extern void execute_30(char*, char *); +extern void execute_31(char*, char *); +extern void execute_32(char*, char *); +extern void execute_33(char*, char *); +extern void execute_34(char*, char *); +extern void execute_35(char*, char *); +extern void execute_36(char*, char *); +extern void execute_37(char*, char *); +extern void execute_38(char*, char *); +extern void execute_39(char*, char *); +extern void execute_40(char*, char *); +extern void execute_41(char*, char *); +extern void execute_42(char*, char *); +extern void execute_43(char*, char *); +extern void execute_44(char*, char *); +extern void execute_45(char*, char *); +extern void execute_46(char*, char *); +extern void execute_47(char*, char *); +extern void execute_48(char*, char *); +extern void execute_49(char*, char *); +extern void execute_50(char*, char *); +extern void execute_51(char*, char *); +extern void execute_52(char*, char *); +extern void execute_53(char*, char *); +extern void execute_54(char*, char *); +extern void execute_55(char*, char *); +extern void execute_56(char*, char *); +extern void execute_57(char*, char *); +extern void execute_58(char*, char *); +extern void execute_59(char*, char *); +extern void execute_60(char*, char *); +extern void execute_61(char*, char *); +extern void execute_62(char*, char *); +extern void execute_63(char*, char *); +extern void execute_64(char*, char *); +extern void execute_65(char*, char *); +extern void execute_66(char*, char *); +extern void execute_67(char*, char *); +extern void execute_68(char*, char *); +extern void execute_69(char*, char *); +extern void execute_70(char*, char *); +extern void execute_71(char*, char *); +extern void execute_72(char*, char *); +extern void execute_73(char*, char *); +extern void execute_74(char*, char *); +extern void execute_75(char*, char *); +extern void execute_76(char*, char *); +extern void execute_77(char*, char *); +extern void execute_78(char*, char *); +extern void execute_79(char*, char *); +extern void execute_80(char*, char *); +extern void execute_81(char*, char *); +extern void execute_82(char*, char *); +extern void execute_83(char*, char *); +extern void execute_84(char*, char *); +extern void execute_85(char*, char *); +extern void execute_86(char*, char *); +extern void execute_87(char*, char *); +extern void execute_88(char*, char *); +extern void execute_89(char*, char *); +extern void execute_90(char*, char *); +extern void execute_91(char*, char *); +extern void execute_92(char*, char *); +extern void execute_93(char*, char *); +extern void execute_94(char*, char *); +extern void execute_95(char*, char *); +extern void execute_96(char*, char *); +extern void execute_97(char*, char *); +extern void execute_98(char*, char *); +extern void execute_99(char*, char *); +extern void execute_100(char*, char *); +extern void execute_101(char*, char *); +extern void execute_102(char*, char *); +extern void execute_103(char*, char *); +extern void execute_104(char*, char *); +extern void execute_105(char*, char *); +extern void execute_106(char*, char *); +extern void execute_107(char*, char *); +extern void execute_108(char*, char *); +extern void execute_109(char*, char *); +extern void execute_110(char*, char *); +extern void execute_111(char*, char *); +extern void execute_112(char*, char *); +extern void execute_113(char*, char *); +extern void execute_114(char*, char *); +extern void execute_115(char*, char *); +extern void execute_116(char*, char *); +extern void execute_117(char*, char *); +extern void execute_118(char*, char *); +extern void execute_119(char*, char *); +extern void execute_135(char*, char *); +extern void execute_254(char*, char *); +extern void execute_255(char*, char *); +extern void execute_258(char*, char *); +extern void execute_259(char*, char *); +extern void execute_271(char*, char *); +extern void execute_272(char*, char *); +extern void execute_273(char*, char *); +extern void execute_274(char*, char *); +extern void execute_275(char*, char *); +extern void execute_276(char*, char *); +extern void execute_277(char*, char *); +extern void execute_278(char*, char *); +extern void execute_279(char*, char *); +extern void execute_280(char*, char *); +extern void execute_281(char*, char *); +extern void execute_282(char*, char *); +extern void execute_283(char*, char *); +extern void execute_284(char*, char *); +extern void execute_285(char*, char *); +extern void execute_286(char*, char *); +extern void execute_287(char*, char *); +extern void execute_288(char*, char *); +extern void execute_289(char*, char *); +extern void execute_290(char*, char *); +extern void execute_291(char*, char *); +extern void execute_292(char*, char *); +extern void execute_293(char*, char *); +extern void execute_294(char*, char *); +extern void execute_295(char*, char *); +extern void execute_296(char*, char *); +extern void execute_297(char*, char *); +extern void execute_298(char*, char *); +extern void execute_299(char*, char *); +extern void execute_300(char*, char *); +extern void execute_301(char*, char *); +extern void execute_302(char*, char *); +extern void execute_303(char*, char *); +extern void execute_304(char*, char *); +extern void execute_305(char*, char *); +extern void execute_306(char*, char *); +extern void execute_307(char*, char *); +extern void execute_308(char*, char *); +extern void execute_309(char*, char *); +extern void execute_310(char*, char *); +extern void execute_311(char*, char *); +extern void execute_312(char*, char *); +extern void execute_313(char*, char *); +extern void execute_314(char*, char *); +extern void execute_315(char*, char *); +extern void execute_316(char*, char *); +extern void execute_317(char*, char *); +extern void execute_318(char*, char *); +extern void execute_319(char*, char *); +extern void execute_320(char*, char *); +extern void execute_321(char*, char *); +extern void execute_322(char*, char *); +extern void execute_323(char*, char *); +extern void execute_324(char*, char *); +extern void execute_325(char*, char *); +extern void execute_326(char*, char *); +extern void execute_327(char*, char *); +extern void execute_328(char*, char *); +extern void execute_468(char*, char *); +extern void execute_474(char*, char *); +extern void execute_475(char*, char *); +extern void execute_484(char*, char *); +extern void execute_485(char*, char *); +extern void execute_486(char*, char *); +extern void execute_487(char*, char *); +extern void execute_488(char*, char *); +extern void execute_490(char*, char *); +extern void execute_495(char*, char *); +extern void execute_496(char*, char *); +extern void execute_497(char*, char *); +extern void execute_498(char*, char *); +extern void execute_499(char*, char *); +extern void execute_140(char*, char *); +extern void execute_168(char*, char *); +extern void execute_458(char*, char *); +extern void execute_459(char*, char *); +extern void execute_460(char*, char *); +extern void execute_461(char*, char *); +extern void execute_462(char*, char *); +extern void execute_463(char*, char *); +extern void execute_464(char*, char *); +extern void execute_149(char*, char *); +extern void execute_150(char*, char *); +extern void execute_151(char*, char *); +extern void execute_165(char*, char *); +extern void execute_166(char*, char *); +extern void execute_167(char*, char *); +extern void execute_390(char*, char *); +extern void execute_391(char*, char *); +extern void execute_392(char*, char *); +extern void execute_393(char*, char *); +extern void execute_394(char*, char *); +extern void execute_395(char*, char *); +extern void execute_396(char*, char *); +extern void execute_398(char*, char *); +extern void execute_399(char*, char *); +extern void execute_400(char*, char *); +extern void execute_401(char*, char *); +extern void execute_405(char*, char *); +extern void execute_409(char*, char *); +extern void execute_410(char*, char *); +extern void execute_411(char*, char *); +extern void execute_412(char*, char *); +extern void execute_413(char*, char *); +extern void execute_414(char*, char *); +extern void execute_417(char*, char *); +extern void execute_419(char*, char *); +extern void execute_420(char*, char *); +extern void execute_421(char*, char *); +extern void execute_422(char*, char *); +extern void execute_423(char*, char *); +extern void execute_424(char*, char *); +extern void execute_425(char*, char *); +extern void execute_426(char*, char *); +extern void execute_427(char*, char *); +extern void execute_428(char*, char *); +extern void execute_429(char*, char *); +extern void execute_430(char*, char *); +extern void execute_431(char*, char *); +extern void execute_432(char*, char *); +extern void execute_153(char*, char *); +extern void execute_154(char*, char *); +extern void execute_155(char*, char *); +extern void execute_156(char*, char *); +extern void execute_402(char*, char *); +extern void execute_403(char*, char *); +extern void execute_404(char*, char *); +extern void execute_163(char*, char *); +extern void execute_164(char*, char *); +extern void execute_633(char*, char *); +extern void execute_634(char*, char *); +extern void execute_635(char*, char *); +extern void execute_644(char*, char *); +extern void execute_645(char*, char *); +extern void execute_646(char*, char *); +extern void execute_647(char*, char *); +extern void execute_648(char*, char *); +extern void execute_650(char*, char *); +extern void execute_651(char*, char *); +extern void execute_655(char*, char *); +extern void execute_656(char*, char *); +extern void execute_657(char*, char *); +extern void execute_658(char*, char *); +extern void execute_659(char*, char *); +extern void execute_171(char*, char *); +extern void execute_199(char*, char *); +extern void execute_620(char*, char *); +extern void execute_621(char*, char *); +extern void execute_622(char*, char *); +extern void execute_623(char*, char *); +extern void execute_624(char*, char *); +extern void execute_625(char*, char *); +extern void execute_626(char*, char *); +extern void execute_180(char*, char *); +extern void execute_181(char*, char *); +extern void execute_182(char*, char *); +extern void execute_196(char*, char *); +extern void execute_197(char*, char *); +extern void execute_198(char*, char *); +extern void execute_552(char*, char *); +extern void execute_553(char*, char *); +extern void execute_554(char*, char *); +extern void execute_555(char*, char *); +extern void execute_556(char*, char *); +extern void execute_557(char*, char *); +extern void execute_558(char*, char *); +extern void execute_560(char*, char *); +extern void execute_561(char*, char *); +extern void execute_562(char*, char *); +extern void execute_563(char*, char *); +extern void execute_567(char*, char *); +extern void execute_571(char*, char *); +extern void execute_572(char*, char *); +extern void execute_573(char*, char *); +extern void execute_574(char*, char *); +extern void execute_575(char*, char *); +extern void execute_576(char*, char *); +extern void execute_579(char*, char *); +extern void execute_581(char*, char *); +extern void execute_582(char*, char *); +extern void execute_583(char*, char *); +extern void execute_584(char*, char *); +extern void execute_585(char*, char *); +extern void execute_586(char*, char *); +extern void execute_587(char*, char *); +extern void execute_588(char*, char *); +extern void execute_589(char*, char *); +extern void execute_590(char*, char *); +extern void execute_591(char*, char *); +extern void execute_592(char*, char *); +extern void execute_593(char*, char *); +extern void execute_594(char*, char *); +extern void execute_217(char*, char *); +extern void execute_223(char*, char *); +extern void execute_664(char*, char *); +extern void vlog_simple_process_execute_0_fast_for_reg(char*, char*, char*); +extern void execute_666(char*, char *); +extern void execute_667(char*, char *); +extern void execute_670(char*, char *); +extern void execute_671(char*, char *); +extern void execute_672(char*, char *); +extern void execute_673(char*, char *); +extern void execute_720(char*, char *); +extern void execute_721(char*, char *); +extern void execute_723(char*, char *); +extern void execute_724(char*, char *); +extern void execute_729(char*, char *); +extern void execute_742(char*, char *); +extern void execute_743(char*, char *); +extern void execute_744(char*, char *); +extern void execute_745(char*, char *); +extern void execute_746(char*, char *); +extern void execute_747(char*, char *); +extern void execute_748(char*, char *); +extern void execute_749(char*, char *); +extern void execute_750(char*, char *); +extern void execute_751(char*, char *); +extern void execute_752(char*, char *); +extern void execute_753(char*, char *); +extern void execute_754(char*, char *); +extern void execute_755(char*, char *); +extern void execute_756(char*, char *); +extern void execute_757(char*, char *); +extern void execute_758(char*, char *); +extern void execute_759(char*, char *); +extern void execute_760(char*, char *); +extern void execute_761(char*, char *); +extern void execute_762(char*, char *); +extern void execute_763(char*, char *); +extern void execute_764(char*, char *); +extern void execute_765(char*, char *); +extern void execute_766(char*, char *); +extern void execute_767(char*, char *); +extern void execute_768(char*, char *); +extern void execute_769(char*, char *); +extern void execute_770(char*, char *); +extern void execute_771(char*, char *); +extern void execute_772(char*, char *); +extern void execute_773(char*, char *); +extern void execute_774(char*, char *); +extern void execute_775(char*, char *); +extern void execute_776(char*, char *); +extern void execute_777(char*, char *); +extern void execute_778(char*, char *); +extern void execute_779(char*, char *); +extern void execute_780(char*, char *); +extern void execute_781(char*, char *); +extern void execute_782(char*, char *); +extern void execute_783(char*, char *); +extern void execute_784(char*, char *); +extern void execute_785(char*, char *); +extern void execute_786(char*, char *); +extern void execute_787(char*, char *); +extern void execute_788(char*, char *); +extern void execute_789(char*, char *); +extern void execute_790(char*, char *); +extern void execute_791(char*, char *); +extern void execute_792(char*, char *); +extern void execute_793(char*, char *); +extern void execute_794(char*, char *); +extern void execute_795(char*, char *); +extern void execute_796(char*, char *); +extern void execute_797(char*, char *); +extern void execute_798(char*, char *); +extern void execute_799(char*, char *); +extern void execute_800(char*, char *); +extern void execute_801(char*, char *); +extern void execute_802(char*, char *); +extern void execute_803(char*, char *); +extern void execute_804(char*, char *); +extern void execute_805(char*, char *); +extern void execute_806(char*, char *); +extern void execute_807(char*, char *); +extern void execute_808(char*, char *); +extern void execute_809(char*, char *); +extern void execute_810(char*, char *); +extern void execute_811(char*, char *); +extern void execute_812(char*, char *); +extern void execute_813(char*, char *); +extern void execute_814(char*, char *); +extern void execute_815(char*, char *); +extern void execute_816(char*, char *); +extern void execute_817(char*, char *); +extern void execute_818(char*, char *); +extern void execute_819(char*, char *); +extern void execute_820(char*, char *); +extern void execute_821(char*, char *); +extern void execute_822(char*, char *); +extern void execute_823(char*, char *); +extern void execute_824(char*, char *); +extern void execute_825(char*, char *); +extern void execute_826(char*, char *); +extern void execute_827(char*, char *); +extern void execute_828(char*, char *); +extern void execute_829(char*, char *); +extern void execute_830(char*, char *); +extern void execute_831(char*, char *); +extern void execute_832(char*, char *); +extern void execute_833(char*, char *); +extern void execute_834(char*, char *); +extern void execute_835(char*, char *); +extern void execute_836(char*, char *); +extern void execute_837(char*, char *); +extern void execute_838(char*, char *); +extern void execute_839(char*, char *); +extern void execute_840(char*, char *); +extern void execute_841(char*, char *); +extern void execute_842(char*, char *); +extern void execute_843(char*, char *); +extern void execute_844(char*, char *); +extern void execute_845(char*, char *); +extern void execute_846(char*, char *); +extern void execute_847(char*, char *); +extern void execute_848(char*, char *); +extern void execute_202(char*, char *); +extern void execute_204(char*, char *); +extern void execute_669(char*, char *); +extern void execute_207(char*, char *); +extern void execute_209(char*, char *); +extern void execute_674(char*, char *); +extern void execute_675(char*, char *); +extern void execute_676(char*, char *); +extern void execute_677(char*, char *); +extern void execute_678(char*, char *); +extern void execute_679(char*, char *); +extern void execute_680(char*, char *); +extern void execute_681(char*, char *); +extern void execute_682(char*, char *); +extern void execute_683(char*, char *); +extern void execute_684(char*, char *); +extern void execute_685(char*, char *); +extern void execute_686(char*, char *); +extern void execute_687(char*, char *); +extern void execute_688(char*, char *); +extern void execute_689(char*, char *); +extern void execute_690(char*, char *); +extern void execute_691(char*, char *); +extern void execute_692(char*, char *); +extern void execute_693(char*, char *); +extern void execute_694(char*, char *); +extern void execute_695(char*, char *); +extern void execute_696(char*, char *); +extern void execute_697(char*, char *); +extern void execute_698(char*, char *); +extern void execute_699(char*, char *); +extern void execute_700(char*, char *); +extern void execute_701(char*, char *); +extern void execute_702(char*, char *); +extern void execute_703(char*, char *); +extern void execute_704(char*, char *); +extern void execute_705(char*, char *); +extern void execute_706(char*, char *); +extern void execute_707(char*, char *); +extern void execute_708(char*, char *); +extern void execute_709(char*, char *); +extern void execute_710(char*, char *); +extern void execute_711(char*, char *); +extern void execute_712(char*, char *); +extern void execute_713(char*, char *); +extern void execute_714(char*, char *); +extern void execute_715(char*, char *); +extern void execute_716(char*, char *); +extern void execute_717(char*, char *); +extern void execute_718(char*, char *); +extern void execute_719(char*, char *); +extern void execute_211(char*, char *); +extern void execute_212(char*, char *); +extern void execute_213(char*, char *); +extern void execute_225(char*, char *); +extern void execute_227(char*, char *); +extern void execute_229(char*, char *); +extern void execute_231(char*, char *); +extern void execute_233(char*, char *); +extern void execute_238(char*, char *); +extern void execute_240(char*, char *); +extern void execute_731(char*, char *); +extern void execute_732(char*, char *); +extern void execute_733(char*, char *); +extern void execute_734(char*, char *); +extern void execute_735(char*, char *); +extern void execute_736(char*, char *); +extern void execute_737(char*, char *); +extern void execute_738(char*, char *); +extern void execute_739(char*, char *); +extern void execute_740(char*, char *); +extern void execute_242(char*, char *); +extern void execute_248(char*, char *); +extern void execute_249(char*, char *); +extern void execute_250(char*, char *); +extern void execute_858(char*, char *); +extern void execute_859(char*, char *); +extern void execute_860(char*, char *); +extern void execute_861(char*, char *); +extern void execute_862(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +extern void transaction_15(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_17(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_24(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_25(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_26(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_27(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_28(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_30(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_31(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_32(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_33(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_34(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_35(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_36(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_37(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_38(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_39(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_40(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_41(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_42(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_43(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_47(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_51(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_54(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1467(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1471(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1557(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1558(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1561(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1573(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1574(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1577(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1600(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1601(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_211(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_212(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_288(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_289(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_290(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_291(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_321(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1400(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1401(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[571] = {(funcp)execute_244, (funcp)execute_245, (funcp)execute_246, (funcp)execute_855, (funcp)execute_856, (funcp)execute_857, (funcp)execute_849, (funcp)execute_850, (funcp)execute_851, (funcp)execute_852, (funcp)execute_853, (funcp)execute_854, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_332, (funcp)execute_335, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)execute_54, (funcp)execute_55, (funcp)execute_56, (funcp)execute_57, (funcp)execute_58, (funcp)execute_59, (funcp)execute_60, (funcp)execute_61, (funcp)execute_62, (funcp)execute_63, (funcp)execute_64, (funcp)execute_65, (funcp)execute_66, (funcp)execute_67, (funcp)execute_68, (funcp)execute_69, (funcp)execute_70, (funcp)execute_71, (funcp)execute_72, (funcp)execute_73, (funcp)execute_74, (funcp)execute_75, (funcp)execute_76, (funcp)execute_77, (funcp)execute_78, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_84, (funcp)execute_85, (funcp)execute_86, (funcp)execute_87, (funcp)execute_88, (funcp)execute_89, (funcp)execute_90, (funcp)execute_91, (funcp)execute_92, (funcp)execute_93, (funcp)execute_94, (funcp)execute_95, (funcp)execute_96, (funcp)execute_97, (funcp)execute_98, (funcp)execute_99, (funcp)execute_100, (funcp)execute_101, (funcp)execute_102, (funcp)execute_103, (funcp)execute_104, (funcp)execute_105, (funcp)execute_106, (funcp)execute_107, (funcp)execute_108, (funcp)execute_109, (funcp)execute_110, (funcp)execute_111, (funcp)execute_112, (funcp)execute_113, (funcp)execute_114, (funcp)execute_115, (funcp)execute_116, (funcp)execute_117, (funcp)execute_118, (funcp)execute_119, (funcp)execute_135, (funcp)execute_254, (funcp)execute_255, (funcp)execute_258, (funcp)execute_259, (funcp)execute_271, (funcp)execute_272, (funcp)execute_273, (funcp)execute_274, (funcp)execute_275, (funcp)execute_276, (funcp)execute_277, (funcp)execute_278, (funcp)execute_279, (funcp)execute_280, (funcp)execute_281, (funcp)execute_282, (funcp)execute_283, (funcp)execute_284, (funcp)execute_285, (funcp)execute_286, (funcp)execute_287, (funcp)execute_288, (funcp)execute_289, (funcp)execute_290, (funcp)execute_291, (funcp)execute_292, (funcp)execute_293, (funcp)execute_294, (funcp)execute_295, (funcp)execute_296, (funcp)execute_297, (funcp)execute_298, (funcp)execute_299, (funcp)execute_300, (funcp)execute_301, (funcp)execute_302, (funcp)execute_303, (funcp)execute_304, (funcp)execute_305, (funcp)execute_306, (funcp)execute_307, (funcp)execute_308, (funcp)execute_309, (funcp)execute_310, (funcp)execute_311, (funcp)execute_312, (funcp)execute_313, (funcp)execute_314, (funcp)execute_315, (funcp)execute_316, (funcp)execute_317, (funcp)execute_318, (funcp)execute_319, (funcp)execute_320, (funcp)execute_321, (funcp)execute_322, (funcp)execute_323, (funcp)execute_324, (funcp)execute_325, (funcp)execute_326, (funcp)execute_327, (funcp)execute_328, (funcp)execute_468, (funcp)execute_474, (funcp)execute_475, (funcp)execute_484, (funcp)execute_485, (funcp)execute_486, (funcp)execute_487, (funcp)execute_488, (funcp)execute_490, (funcp)execute_495, (funcp)execute_496, (funcp)execute_497, (funcp)execute_498, (funcp)execute_499, (funcp)execute_140, (funcp)execute_168, (funcp)execute_458, (funcp)execute_459, (funcp)execute_460, (funcp)execute_461, (funcp)execute_462, (funcp)execute_463, (funcp)execute_464, (funcp)execute_149, (funcp)execute_150, (funcp)execute_151, (funcp)execute_165, (funcp)execute_166, (funcp)execute_167, (funcp)execute_390, (funcp)execute_391, (funcp)execute_392, (funcp)execute_393, (funcp)execute_394, (funcp)execute_395, (funcp)execute_396, (funcp)execute_398, (funcp)execute_399, (funcp)execute_400, (funcp)execute_401, (funcp)execute_405, (funcp)execute_409, (funcp)execute_410, (funcp)execute_411, (funcp)execute_412, (funcp)execute_413, (funcp)execute_414, (funcp)execute_417, (funcp)execute_419, (funcp)execute_420, (funcp)execute_421, (funcp)execute_422, (funcp)execute_423, (funcp)execute_424, (funcp)execute_425, (funcp)execute_426, (funcp)execute_427, (funcp)execute_428, (funcp)execute_429, (funcp)execute_430, (funcp)execute_431, (funcp)execute_432, (funcp)execute_153, (funcp)execute_154, (funcp)execute_155, (funcp)execute_156, (funcp)execute_402, (funcp)execute_403, (funcp)execute_404, (funcp)execute_163, (funcp)execute_164, (funcp)execute_633, (funcp)execute_634, (funcp)execute_635, (funcp)execute_644, (funcp)execute_645, (funcp)execute_646, (funcp)execute_647, (funcp)execute_648, (funcp)execute_650, (funcp)execute_651, (funcp)execute_655, (funcp)execute_656, (funcp)execute_657, (funcp)execute_658, (funcp)execute_659, (funcp)execute_171, (funcp)execute_199, (funcp)execute_620, (funcp)execute_621, (funcp)execute_622, (funcp)execute_623, (funcp)execute_624, (funcp)execute_625, (funcp)execute_626, (funcp)execute_180, (funcp)execute_181, (funcp)execute_182, (funcp)execute_196, (funcp)execute_197, (funcp)execute_198, (funcp)execute_552, (funcp)execute_553, (funcp)execute_554, (funcp)execute_555, (funcp)execute_556, (funcp)execute_557, (funcp)execute_558, (funcp)execute_560, (funcp)execute_561, (funcp)execute_562, (funcp)execute_563, (funcp)execute_567, (funcp)execute_571, (funcp)execute_572, (funcp)execute_573, (funcp)execute_574, (funcp)execute_575, (funcp)execute_576, (funcp)execute_579, (funcp)execute_581, (funcp)execute_582, (funcp)execute_583, (funcp)execute_584, (funcp)execute_585, (funcp)execute_586, (funcp)execute_587, (funcp)execute_588, (funcp)execute_589, (funcp)execute_590, (funcp)execute_591, (funcp)execute_592, (funcp)execute_593, (funcp)execute_594, (funcp)execute_217, (funcp)execute_223, (funcp)execute_664, (funcp)vlog_simple_process_execute_0_fast_for_reg, (funcp)execute_666, (funcp)execute_667, (funcp)execute_670, (funcp)execute_671, (funcp)execute_672, (funcp)execute_673, (funcp)execute_720, (funcp)execute_721, (funcp)execute_723, (funcp)execute_724, (funcp)execute_729, (funcp)execute_742, (funcp)execute_743, (funcp)execute_744, (funcp)execute_745, (funcp)execute_746, (funcp)execute_747, (funcp)execute_748, (funcp)execute_749, (funcp)execute_750, (funcp)execute_751, (funcp)execute_752, (funcp)execute_753, (funcp)execute_754, (funcp)execute_755, (funcp)execute_756, (funcp)execute_757, (funcp)execute_758, (funcp)execute_759, (funcp)execute_760, (funcp)execute_761, (funcp)execute_762, (funcp)execute_763, (funcp)execute_764, (funcp)execute_765, (funcp)execute_766, (funcp)execute_767, (funcp)execute_768, (funcp)execute_769, (funcp)execute_770, (funcp)execute_771, (funcp)execute_772, (funcp)execute_773, (funcp)execute_774, (funcp)execute_775, (funcp)execute_776, (funcp)execute_777, (funcp)execute_778, (funcp)execute_779, (funcp)execute_780, (funcp)execute_781, (funcp)execute_782, (funcp)execute_783, (funcp)execute_784, (funcp)execute_785, (funcp)execute_786, (funcp)execute_787, (funcp)execute_788, (funcp)execute_789, (funcp)execute_790, (funcp)execute_791, (funcp)execute_792, (funcp)execute_793, (funcp)execute_794, (funcp)execute_795, (funcp)execute_796, (funcp)execute_797, (funcp)execute_798, (funcp)execute_799, (funcp)execute_800, (funcp)execute_801, (funcp)execute_802, (funcp)execute_803, (funcp)execute_804, (funcp)execute_805, (funcp)execute_806, (funcp)execute_807, (funcp)execute_808, (funcp)execute_809, (funcp)execute_810, (funcp)execute_811, (funcp)execute_812, (funcp)execute_813, (funcp)execute_814, (funcp)execute_815, (funcp)execute_816, (funcp)execute_817, (funcp)execute_818, (funcp)execute_819, (funcp)execute_820, (funcp)execute_821, (funcp)execute_822, (funcp)execute_823, (funcp)execute_824, (funcp)execute_825, (funcp)execute_826, (funcp)execute_827, (funcp)execute_828, (funcp)execute_829, (funcp)execute_830, (funcp)execute_831, (funcp)execute_832, (funcp)execute_833, (funcp)execute_834, (funcp)execute_835, (funcp)execute_836, (funcp)execute_837, (funcp)execute_838, (funcp)execute_839, (funcp)execute_840, (funcp)execute_841, (funcp)execute_842, (funcp)execute_843, (funcp)execute_844, (funcp)execute_845, (funcp)execute_846, (funcp)execute_847, (funcp)execute_848, (funcp)execute_202, (funcp)execute_204, (funcp)execute_669, (funcp)execute_207, (funcp)execute_209, (funcp)execute_674, (funcp)execute_675, (funcp)execute_676, (funcp)execute_677, (funcp)execute_678, (funcp)execute_679, (funcp)execute_680, (funcp)execute_681, (funcp)execute_682, (funcp)execute_683, (funcp)execute_684, (funcp)execute_685, (funcp)execute_686, (funcp)execute_687, (funcp)execute_688, (funcp)execute_689, (funcp)execute_690, (funcp)execute_691, (funcp)execute_692, (funcp)execute_693, (funcp)execute_694, (funcp)execute_695, (funcp)execute_696, (funcp)execute_697, (funcp)execute_698, (funcp)execute_699, (funcp)execute_700, (funcp)execute_701, (funcp)execute_702, (funcp)execute_703, (funcp)execute_704, (funcp)execute_705, (funcp)execute_706, (funcp)execute_707, (funcp)execute_708, (funcp)execute_709, (funcp)execute_710, (funcp)execute_711, (funcp)execute_712, (funcp)execute_713, (funcp)execute_714, (funcp)execute_715, (funcp)execute_716, (funcp)execute_717, (funcp)execute_718, (funcp)execute_719, (funcp)execute_211, (funcp)execute_212, (funcp)execute_213, (funcp)execute_225, (funcp)execute_227, (funcp)execute_229, (funcp)execute_231, (funcp)execute_233, (funcp)execute_238, (funcp)execute_240, (funcp)execute_731, (funcp)execute_732, (funcp)execute_733, (funcp)execute_734, (funcp)execute_735, (funcp)execute_736, (funcp)execute_737, (funcp)execute_738, (funcp)execute_739, (funcp)execute_740, (funcp)execute_242, (funcp)execute_248, (funcp)execute_249, (funcp)execute_250, (funcp)execute_858, (funcp)execute_859, (funcp)execute_860, (funcp)execute_861, (funcp)execute_862, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_15, (funcp)transaction_17, (funcp)transaction_24, (funcp)transaction_25, (funcp)transaction_26, (funcp)transaction_27, (funcp)transaction_28, (funcp)transaction_30, (funcp)transaction_31, (funcp)transaction_32, (funcp)transaction_33, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_37, (funcp)transaction_38, (funcp)transaction_39, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43, (funcp)transaction_47, (funcp)transaction_51, (funcp)transaction_54, (funcp)transaction_1467, (funcp)transaction_1471, (funcp)transaction_1557, (funcp)transaction_1558, (funcp)transaction_1561, (funcp)transaction_1573, (funcp)transaction_1574, (funcp)transaction_1577, (funcp)transaction_1600, (funcp)transaction_1601, (funcp)transaction_211, (funcp)transaction_212, (funcp)transaction_288, (funcp)transaction_289, (funcp)transaction_290, (funcp)transaction_291, (funcp)transaction_321, (funcp)transaction_1400, (funcp)transaction_1401}; +const int NumRelocateId= 571; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/MiniMIPS32_SYS_tb_behav/xsim.reloc", (void **)funcTab, 571); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/MiniMIPS32_SYS_tb_behav/xsim.reloc"); +} + + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + +void wrapper_func_0(char *dp) + +{ + +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/MiniMIPS32_SYS_tb_behav/xsim.reloc"); + wrapper_func_0(dp); + + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstantiate(); + +extern void implicit_HDL_SCcleanup(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/MiniMIPS32_SYS_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/MiniMIPS32_SYS_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/MiniMIPS32_SYS_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git 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+v_smpte_uhdsdi_v1_0_7=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_7 +ddr4_pl_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_0 +xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6 +fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10 +tmr_manager_v1_0_5=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_5 +displayport_v9_0_2=$RDI_DATADIR/xsim/ip/displayport_v9_0_2 +lte_pucch_receiver_v2_0_17=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_17 +axi_tft_v2_0_23=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_23 +axis_dbg_sync_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_0 +axis_mem_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_0 +noc_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_v1_0_0 +duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15 +dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13 +blk_mem_gen_v8_4_4=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_4 +interlaken_v2_4_4=$RDI_DATADIR/xsim/ip/interlaken_v2_4_4 +mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0 +pcie_dma_versal_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_dma_versal_v1_0_0 +pcie_axi4lite_tap_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_0 +rs_encoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_16 +axi_firewall_v1_0_8=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_8 +g709_fec_v2_4_2=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_2 +sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1 +ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13 +v_hscaler_v1_0_14=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_14 +hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 +hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0 +usxgmii_v1_1_1=$RDI_DATADIR/xsim/ip/usxgmii_v1_1_1 +mem_tg_v1_0_1=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_1 +rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1 +axi_crossbar_v2_1_21=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_21 +lib_fifo_v1_0_14=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_14 +proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13 +axi_pcie_v2_9_2=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_2 +v_osd_v6_0_16=$RDI_DATADIR/xsim/ip/v_osd_v6_0_16 +pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12 +axi_vdma_v6_3_8=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_8 +xdma_v4_1_4=$RDI_DATADIR/xsim/ip/xdma_v4_1_4 +xfft_v7_2_10=$RDI_DATADIR/xsim/ip/xfft_v7_2_10 +icap_arb_v1_0_0=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_0 +vid_phy_controller_v2_1_6=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_6 +zynq_ultra_ps_e_v3_2_4=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_4 +tri_mode_ethernet_mac_v9_0_15=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_15 +axi_memory_init_v1_0_1=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_1 +audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 +axi_mmu_v2_1_18=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_18 +v_enhance_v8_0_15=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_15 +cic_compiler_v4_0_15=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_15 +xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 +emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 +axi_interconnect_v1_7_17=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_17 +axi_cdma_v4_1_20=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_20 +processing_system7_vip_v1_0_8=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_8 +xxv_ethernet_v3_1_0=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_1_0 +axi_traffic_gen_v3_0_6=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_6 +pr_decoupler_v1_0_8=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_8 +pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0 +v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8 +g709_rs_encoder_v2_2_7=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_7 +viterbi_v9_1_12=$RDI_DATADIR/xsim/ip/viterbi_v9_1_12 +axi_emc_v3_0_20=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_20 +axi_perf_mon_v5_0_22=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_22 +xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2 +ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig +axis_combiner_v1_1_18=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_18 +lib_bmg_v1_0_13=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_13 +remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 +pr_axi_shutdown_manager_v1_0_1=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_1 +axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 +smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 +lmb_v10_v3_0_10=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_10 +axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib +v_letterbox_v1_0_14=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_14 +xlconstant_v1_1_6=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_6 +hdmi_gt_controller_v1_0_1=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_1 +tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 +xhmc_v1_0_10=$RDI_DATADIR/xsim/ip/xhmc_v1_0_10 +amm_axi_bridge_v1_0_6=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_6 +ten_gig_eth_pcs_pma_v6_0_16=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_16 +axi_msg_v1_0_6=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_6 +mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 +v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1 +emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0 +cmac_usplus_v3_0_0=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_0_0 +v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 +dsp_macro_v1_0_0=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_0 +pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2 +high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 +lte_3gpp_mimo_encoder_v4_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_15 +oddr_v1_0_1=$RDI_DATADIR/xsim/ip/oddr_v1_0_1 +etrnic_v1_0_4=$RDI_DATADIR/xsim/ip/etrnic_v1_0_4 +advanced_io_wizard_v1_0_1=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_1 +tcc_encoder_3gpp_v5_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_16 +sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 +axi_fifo_mm_s_v4_2_2=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_2 +lte_3gpp_channel_estimator_v2_0_17=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_17 +gtwizard_ultrascale_v1_6_10=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_10 +v_scenechange_v1_0_2=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_2 +gmii_to_rgmii_v4_0_7=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_7 +xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 +v_rgb2ycrcb_v7_1_13=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_13 +axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0 +advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0 +ieee802d3_rs_fec_v2_0_6=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_6 +axi_protocol_checker_v2_0_6=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_6 +axi_data_fifo_v2_1_19=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_19 +tmr_voter_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_3 +interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 +axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub +c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6 +v_frmbuf_wr_v2_1_3=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_3 +v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 +ieee802d3_400g_rs_fec_v1_0_8=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_8 +stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0 +rld3_pl_v1_0_1=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_1 +v_demosaic_v1_0_6=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_6 +ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 +v_tpg_v7_0_14=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_14 +lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 +axi_protocol_converter_v2_1_20=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_20 +blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 +fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 +rama_v1_1_3_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_3_lib +xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip +ernic_v1_0_2=$RDI_DATADIR/xsim/ip/ernic_v1_0_2 +axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 +noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0 +pc_cfr_v6_3_1=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_1 +sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1 +lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 +axi_register_slice_v2_1_20=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_20 +shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0 +videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 +audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0 +lte_fft_v2_0_19=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_19 +i2s_receiver_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_3 +v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 +sid_v8_0_15=$RDI_DATADIR/xsim/ip/sid_v8_0_15 +axis_data_fifo_v2_0_2=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_2 +remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 +axis_cap_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_0 +microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 +axi_pcie3_v3_0_10=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_10 +hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3 +axis_accelerator_adapter_v2_1_16=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_16 +xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6 +v_axi4s_remap_v1_0_12=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_12 +jesd204c_v4_2_0=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_0 +axi_sideband_util_v1_0_4=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_4 +debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1 +mult_gen_v12_0_16=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_16 +v_tpg_v8_0_2=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_2 +ats_switch_v1_0_3=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_3 +v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9 +axis_clock_converter_v1_1_21=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_21 +can_v5_0_23=$RDI_DATADIR/xsim/ip/can_v5_0_23 +mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 +axis_broadcaster_v1_1_19=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_19 +v_tc_v6_2_0=$RDI_DATADIR/xsim/ip/v_tc_v6_2_0 +g975_efec_i4_v1_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_18 +xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0 +v_mix_v4_0_1=$RDI_DATADIR/xsim/ip/v_mix_v4_0_1 +clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0 +axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0 +roe_framer_v2_1_0=$RDI_DATADIR/xsim/ip/roe_framer_v2_1_0 +microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 +axi_intc_v4_1_14=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_14 +emb_mem_gen_v1_0_2=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_2 +tmr_comparator_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_3 +v_gamma_lut_v1_0_6=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_6 +dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16 +mpegtsmux_v1_0_0=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_0_0 +g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18 +uhdsdi_gt_v2_0_1=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_1 +axi_gpio_v2_0_22=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_22 +axi_quad_spi_v3_2_19=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_19 +v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 +c_shift_ram_v12_0_14=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_14 +v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12 +sem_v4_1_12=$RDI_DATADIR/xsim/ip/sem_v4_1_12 +ten_gig_eth_mac_v15_1_7=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_7 +spdif_v2_0_22=$RDI_DATADIR/xsim/ip/spdif_v2_0_22 +v_multi_scaler_v1_0_2=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_2 +v_ccm_v6_0_15=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_15 +axi_timer_v2_0_22=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_22 +quadsgmii_v3_4_7=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_7 +versal_cips_v1_0_0=$RDI_DATADIR/xsim/ip/versal_cips_v1_0_0 +zynq_ultra_ps_e_v3_3_1=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_1 +tcc_decoder_3gppmm_v2_0_19=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_19 +c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6 +axi_mcdma_v1_0_6=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_6 +axi_clock_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_19 +timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 +ieee802d3_200g_rs_fec_v1_0_8=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_8 +gtwizard_ultrascale_v1_7_7=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_7 +sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0 +bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 +div_gen_v5_1_16=$RDI_DATADIR/xsim/ip/div_gen_v5_1_16 +axi_ethernetlite_v3_0_18=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_18 +pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 +axi4stream_vip_v1_1_6=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_6 +floating_point_v7_0_17=$RDI_DATADIR/xsim/ip/floating_point_v7_0_17 +high_speed_selectio_wiz_v3_5_2=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_2 +xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6 +srio_gen2_v4_1_7=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_7 +ieee802d3_clause74_fec_v1_0_5=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_5 +v_gamma_v7_0_15=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_15 +high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 +dp_videoaxi4s_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_1 +ethernet_1_10_25g_v2_4_0=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_4_0 +in_system_ibert_v1_0_10=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_10 +ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0 +trace_s2mm_v1_0_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v1_0_0 +mdm_v3_2_17=$RDI_DATADIR/xsim/ip/mdm_v3_2_17 +dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1 +axis_ila_pp_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_0 +axis_ila_intf_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_0 +rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0 +axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6 +v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 +axi_traffic_gen_v2_0_21=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_21 +stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0 +lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 +uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3 +pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4 +cordic_v6_0_16=$RDI_DATADIR/xsim/ip/cordic_v6_0_16 +ieee802d3_50g_rs_fec_v2_0_2=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_2 +axi_ahblite_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_17 +axi_mcdma_v1_1_1=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_1 +ieee802d3_50g_rs_fec_v1_0_12=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_12 +axi_amm_bridge_v1_0_10=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_10 +xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6 +xbip_multadd_v3_0_15=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_15 +axi_timebase_wdt_v3_0_12=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_12 +v_mix_v3_0_4=$RDI_DATADIR/xsim/ip/v_mix_v3_0_4 +axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 +tmr_sem_v1_0_10=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_10 +axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 +mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7 +aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0 +sem_ultra_v3_1_12=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_12 +xtlm=$RDI_DATADIR/xsim/ip/xtlm +axi_ethernet_buffer_v2_0_21=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_21 +iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 +vfb_v1_0_14=$RDI_DATADIR/xsim/ip/vfb_v1_0_14 +xlconcat_v2_1_3=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_3 +v_ycrcb2rgb_v7_1_13=$RDI_DATADIR/xsim/ip/v_ycrcb2rgb_v7_1_13 +emb_fifo_gen_v1_0_2=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_2 +lte_rach_detector_v3_1_6=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_6 +processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6 +lte_ul_channel_decoder_v4_0_16=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_16 +soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0 +ieee802d3_rs_fec_v1_0_16=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_16 +pr_bitstream_monitor_v1_0_1=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_1 +sync_ip=$RDI_DATADIR/xsim/ip/sync_ip +v_vscaler_v1_0_14=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_14 +c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6 +ibert_lib_v1_0_7=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_7 +c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6 +v_hcresampler_v1_0_14=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_14 +axis_itct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_0 +lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 +axi_uart16550_v2_0_22=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_22 +ai_pl=$RDI_DATADIR/xsim/ip/ai_pl +g709_fec_v2_3_6=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_6 +av_pat_gen_v1_0_1=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_1 +fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 +v_vcresampler_v1_0_14=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_14 +v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0 +microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 +axi_iic_v2_0_23=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_23 +axis_protocol_checker_v2_0_4=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_4 +v_uhdsdi_audio_v2_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_1 +xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6 +axis_dbg_stub_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_0 +c_counter_binary_v12_0_14=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_14 +xpm=$RDI_DATADIR/xsim/ip/xpm +axi_chip2chip_v5_0_7=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_7 +displayport_v7_0_12=$RDI_DATADIR/xsim/ip/displayport_v7_0_12 +switch_core_top_v1_0_8=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_8 +displayport_v8_1_2=$RDI_DATADIR/xsim/ip/displayport_v8_1_2 +xfft_v9_0_18=$RDI_DATADIR/xsim/ip/xfft_v9_0_18 +lte_3gpp_mimo_decoder_v3_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_16 +noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0 +mrmac_v1_1_0=$RDI_DATADIR/xsim/ip/mrmac_v1_1_0 +axi_datamover_v5_1_22=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_22 +xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10 +tcc_encoder_3gpplte_v4_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_16 +rs_decoder_v9_0_17=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_17 +jesd204_v7_2_7=$RDI_DATADIR/xsim/ip/jesd204_v7_2_7 +dds_compiler_v6_0_19=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_19 +generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 +fc32_rs_fec_v1_0_12=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_12 +fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1 +axi_epc_v2_0_23=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_23 +lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 +video_frame_crc_v1_0_2=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_2 +axi_apb_bridge_v3_0_16=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_16 +axi_usb2_device_v5_0_21=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_21 +axis_ila_ct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_0 +multi_channel_25g_rs_fec_v1_0_6=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_6 +util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 +sim_trig_top_v1_0=$RDI_DATADIR/xsim/ip/sim_trig_top_v1_0 +v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0 +xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6 +lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 +util_idelay_ctrl_v1_0_2=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_2 +v_csc_v1_0_14=$RDI_DATADIR/xsim/ip/v_csc_v1_0_14 +axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 +gig_ethernet_pcs_pma_v16_1_7=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_7 +mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 +audio_formatter_v1_0_2=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_2 +xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 +axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0 +tsn_endpoint_ethernet_mac_block_v1_0_5=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_5 +mem_pl_v1_0_0=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_0 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.ini.bak b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.ini.bak new file mode 100644 index 0000000..6ddb512 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.ini.bak @@ -0,0 +1,445 @@ +std=$RDI_DATADIR/xsim/vhdl/std +ieee=$RDI_DATADIR/xsim/vhdl/ieee +ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed +vl=$RDI_DATADIR/xsim/vhdl/vl +synopsys=$RDI_DATADIR/xsim/vhdl/synopsys +uvm=$RDI_DATADIR/xsim/system_verilog/uvm +secureip=$RDI_DATADIR/xsim/verilog/secureip +unisim=$RDI_DATADIR/xsim/vhdl/unisim +unimacro=$RDI_DATADIR/xsim/vhdl/unimacro +unifast=$RDI_DATADIR/xsim/vhdl/unifast +unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver +unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver +unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver +simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver +system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6 +bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 +xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0 +axis_interconnect_v1_1_18=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_18 +floating_point_v7_1_9=$RDI_DATADIR/xsim/ip/floating_point_v7_1_9 +prc_v1_3_3=$RDI_DATADIR/xsim/ip/prc_v1_3_3 +axi_hbicap_v1_0_0=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_0 +common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0 +fir_compiler_v7_2_13=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_13 +axi_fifo_mm_s_v4_1_17=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_17 +rs_toolbox_v9_0_8=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_8 +gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 +v_cfa_v7_0_14=$RDI_DATADIR/xsim/ip/v_cfa_v7_0_14 +axi4svideo_bridge_v1_0_10=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_10 +axi_sg_v4_1_13=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_13 +perf_axi_tg_v1_0_9=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_9 +pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11 +xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6 +gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux +fifo_generator_v13_2_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_5 +lte_dl_channel_encoder_v4_0_1=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_1 +cmpy_v6_0_18=$RDI_DATADIR/xsim/ip/cmpy_v6_0_18 +qdma_v3_0_3=$RDI_DATADIR/xsim/ip/qdma_v3_0_3 +v_cresample_v4_0_14=$RDI_DATADIR/xsim/ip/v_cresample_v4_0_14 +v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9 +hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0 +convolution_v9_0_15=$RDI_DATADIR/xsim/ip/convolution_v9_0_15 +xfft_v9_1_3=$RDI_DATADIR/xsim/ip/xfft_v9_1_3 +noc_mc_ddr4_phy_v1_0_0=$RDI_DATADIR/xsim/ip/noc_mc_ddr4_phy_v1_0_0 +axi_vfifo_ctrl_v2_0_22=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_22 +axi_bram_ctrl_v4_1_2=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_2 +ldpc_v2_0_4=$RDI_DATADIR/xsim/ip/ldpc_v2_0_4 +sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2 +lte_dl_channel_encoder_v3_0_16=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_16 +mipi_dphy_v4_1_5=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_1_5 +ba317=$RDI_DATADIR/xsim/ip/ba317 +xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4 +qdriv_pl_v1_0_0=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_0 +axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14 +polar_v1_0_4=$RDI_DATADIR/xsim/ip/polar_v1_0_4 +vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0 +axis_dwidth_converter_v1_1_19=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_19 +ahblite_axi_bridge_v3_0_15=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_15 +xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6 +common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1 +util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 +cmac_v2_5_2=$RDI_DATADIR/xsim/ip/cmac_v2_5_2 +sd_fec_v1_0_2=$RDI_DATADIR/xsim/ip/sd_fec_v1_0_2 +axis_register_slice_v1_1_20=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_20 +sd_fec_v1_1_4=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_4 +canfd_v2_0_2=$RDI_DATADIR/xsim/ip/canfd_v2_0_2 +ai_noc=$RDI_DATADIR/xsim/ip/ai_noc +qdriv_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_0 +flexo_100g_rs_fec_v1_0_12=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_12 +v_uhdsdi_audio_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_0 +etrnic_v1_1_3=$RDI_DATADIR/xsim/ip/etrnic_v1_1_3 +jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi +mrmac_v1_0_1=$RDI_DATADIR/xsim/ip/mrmac_v1_0_1 +system_cache_v5_0_0=$RDI_DATADIR/xsim/ip/system_cache_v5_0_0 +v_dp_axi4s_vid_out_v1_0_0=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_0 +v_axi4s_vid_out_v4_0_10=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_10 +ta_dma_v1_0_4=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_4 +axis_mu_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_0 +axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 +rst_vip_v1_0_3=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_3 +ieee802d3_25g_rs_fec_v1_0_14=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_14 +mailbox_v2_1_12=$RDI_DATADIR/xsim/ip/mailbox_v2_1_12 +v_deinterlacer_v5_0_14=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_14 +v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13 +xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6 +cpri_v8_11_0=$RDI_DATADIR/xsim/ip/cpri_v8_11_0 +c_accum_v12_0_14=$RDI_DATADIR/xsim/ip/c_accum_v12_0_14 +microblaze_v11_0_2=$RDI_DATADIR/xsim/ip/microblaze_v11_0_2 +uram_rd_back_v1_0_0=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_0 +clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2 +hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 +tmr_inject_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_4 +picxo=$RDI_DATADIR/xsim/ip/picxo +axis_subset_converter_v1_1_20=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_20 +nvmeha_v1_0_1=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_1 +bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 +axi_uartlite_v2_0_24=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_24 +l_ethernet_v3_0_0=$RDI_DATADIR/xsim/ip/l_ethernet_v3_0_0 +lte_fft_v2_1_1=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_1 +axis_vio_v1_0_0=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_0 +noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0 +axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0 +xbip_dsp48_macro_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_17 +noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0 +i2s_transmitter_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_3 +iomodule_v3_1_5=$RDI_DATADIR/xsim/ip/iomodule_v3_1_5 +axi_hwicap_v3_0_24=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_24 +pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8 +axi_dma_v7_1_21=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_21 +axis_data_fifo_v1_1_21=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_21 +axis_switch_v1_1_20=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_20 +c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6 +fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6 +compact_gt_v1_0_6=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_6 +tsn_temac_v1_0_5=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_5 +axi_dwidth_converter_v2_1_20=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_20 +lmb_bram_if_cntlr_v4_0_17=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_17 +v_frmbuf_rd_v2_1_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_3 +v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 +v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 +vid_phy_controller_v2_2_4=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_4 +lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 +mutex_v2_1_11=$RDI_DATADIR/xsim/ip/mutex_v2_1_11 +high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1 +xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6 +fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1 +g709_rs_decoder_v2_2_9=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_9 +zynq_ultra_ps_e_vip_v1_0_6=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_6 +axi_mm2s_mapper_v1_1_19=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_19 +axi_vip_v1_1_6=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_6 +c_addsub_v12_0_14=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_14 +v_smpte_uhdsdi_v1_0_7=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_7 +ddr4_pl_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_0 +xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6 +fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10 +tmr_manager_v1_0_5=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_5 +displayport_v9_0_2=$RDI_DATADIR/xsim/ip/displayport_v9_0_2 +lte_pucch_receiver_v2_0_17=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_17 +axi_tft_v2_0_23=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_23 +axis_dbg_sync_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_0 +axis_mem_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_0 +noc_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_v1_0_0 +duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15 +dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13 +blk_mem_gen_v8_4_4=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_4 +interlaken_v2_4_4=$RDI_DATADIR/xsim/ip/interlaken_v2_4_4 +mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0 +pcie_dma_versal_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_dma_versal_v1_0_0 +pcie_axi4lite_tap_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_0 +rs_encoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_16 +axi_firewall_v1_0_8=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_8 +g709_fec_v2_4_2=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_2 +sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1 +ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13 +v_hscaler_v1_0_14=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_14 +hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 +hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0 +usxgmii_v1_1_1=$RDI_DATADIR/xsim/ip/usxgmii_v1_1_1 +mem_tg_v1_0_1=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_1 +rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1 +axi_crossbar_v2_1_21=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_21 +lib_fifo_v1_0_14=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_14 +proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13 +axi_pcie_v2_9_2=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_2 +v_osd_v6_0_16=$RDI_DATADIR/xsim/ip/v_osd_v6_0_16 +pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12 +axi_vdma_v6_3_8=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_8 +xdma_v4_1_4=$RDI_DATADIR/xsim/ip/xdma_v4_1_4 +xfft_v7_2_10=$RDI_DATADIR/xsim/ip/xfft_v7_2_10 +icap_arb_v1_0_0=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_0 +vid_phy_controller_v2_1_6=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_6 +zynq_ultra_ps_e_v3_2_4=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_4 +tri_mode_ethernet_mac_v9_0_15=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_15 +axi_memory_init_v1_0_1=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_1 +audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 +axi_mmu_v2_1_18=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_18 +v_enhance_v8_0_15=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_15 +cic_compiler_v4_0_15=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_15 +xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 +emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 +axi_interconnect_v1_7_17=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_17 +axi_cdma_v4_1_20=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_20 +processing_system7_vip_v1_0_8=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_8 +xxv_ethernet_v3_1_0=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_1_0 +axi_traffic_gen_v3_0_6=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_6 +pr_decoupler_v1_0_8=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_8 +pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0 +v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8 +g709_rs_encoder_v2_2_7=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_7 +viterbi_v9_1_12=$RDI_DATADIR/xsim/ip/viterbi_v9_1_12 +axi_emc_v3_0_20=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_20 +axi_perf_mon_v5_0_22=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_22 +xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2 +ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig +axis_combiner_v1_1_18=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_18 +lib_bmg_v1_0_13=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_13 +remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 +pr_axi_shutdown_manager_v1_0_1=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_1 +axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 +smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 +lmb_v10_v3_0_10=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_10 +axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib +v_letterbox_v1_0_14=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_14 +xlconstant_v1_1_6=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_6 +hdmi_gt_controller_v1_0_1=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_1 +tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 +xhmc_v1_0_10=$RDI_DATADIR/xsim/ip/xhmc_v1_0_10 +amm_axi_bridge_v1_0_6=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_6 +ten_gig_eth_pcs_pma_v6_0_16=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_16 +axi_msg_v1_0_6=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_6 +mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 +v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1 +emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0 +cmac_usplus_v3_0_0=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_0_0 +v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 +dsp_macro_v1_0_0=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_0 +pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2 +high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 +lte_3gpp_mimo_encoder_v4_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_15 +oddr_v1_0_1=$RDI_DATADIR/xsim/ip/oddr_v1_0_1 +etrnic_v1_0_4=$RDI_DATADIR/xsim/ip/etrnic_v1_0_4 +advanced_io_wizard_v1_0_1=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_1 +tcc_encoder_3gpp_v5_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_16 +sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 +axi_fifo_mm_s_v4_2_2=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_2 +lte_3gpp_channel_estimator_v2_0_17=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_17 +gtwizard_ultrascale_v1_6_10=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_10 +v_scenechange_v1_0_2=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_2 +gmii_to_rgmii_v4_0_7=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_7 +xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 +v_rgb2ycrcb_v7_1_13=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_13 +axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0 +advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0 +ieee802d3_rs_fec_v2_0_6=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_6 +axi_protocol_checker_v2_0_6=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_6 +axi_data_fifo_v2_1_19=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_19 +tmr_voter_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_3 +interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 +axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub +c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6 +v_frmbuf_wr_v2_1_3=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_3 +v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 +ieee802d3_400g_rs_fec_v1_0_8=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_8 +stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0 +rld3_pl_v1_0_1=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_1 +v_demosaic_v1_0_6=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_6 +ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 +v_tpg_v7_0_14=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_14 +lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 +axi_protocol_converter_v2_1_20=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_20 +blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 +fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 +rama_v1_1_3_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_3_lib +xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip +ernic_v1_0_2=$RDI_DATADIR/xsim/ip/ernic_v1_0_2 +axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 +noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0 +pc_cfr_v6_3_1=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_1 +sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1 +lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 +axi_register_slice_v2_1_20=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_20 +shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0 +videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 +audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0 +lte_fft_v2_0_19=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_19 +i2s_receiver_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_3 +v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 +sid_v8_0_15=$RDI_DATADIR/xsim/ip/sid_v8_0_15 +axis_data_fifo_v2_0_2=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_2 +remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 +axis_cap_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_0 +microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 +axi_pcie3_v3_0_10=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_10 +hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3 +axis_accelerator_adapter_v2_1_16=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_16 +xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6 +v_axi4s_remap_v1_0_12=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_12 +jesd204c_v4_2_0=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_0 +axi_sideband_util_v1_0_4=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_4 +debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1 +mult_gen_v12_0_16=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_16 +v_tpg_v8_0_2=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_2 +ats_switch_v1_0_3=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_3 +v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9 +axis_clock_converter_v1_1_21=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_21 +can_v5_0_23=$RDI_DATADIR/xsim/ip/can_v5_0_23 +mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 +axis_broadcaster_v1_1_19=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_19 +v_tc_v6_2_0=$RDI_DATADIR/xsim/ip/v_tc_v6_2_0 +g975_efec_i4_v1_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_18 +xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0 +v_mix_v4_0_1=$RDI_DATADIR/xsim/ip/v_mix_v4_0_1 +clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0 +axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0 +roe_framer_v2_1_0=$RDI_DATADIR/xsim/ip/roe_framer_v2_1_0 +microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 +axi_intc_v4_1_14=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_14 +emb_mem_gen_v1_0_2=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_2 +tmr_comparator_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_3 +v_gamma_lut_v1_0_6=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_6 +dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16 +mpegtsmux_v1_0_0=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_0_0 +g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18 +uhdsdi_gt_v2_0_1=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_1 +axi_gpio_v2_0_22=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_22 +axi_quad_spi_v3_2_19=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_19 +v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 +c_shift_ram_v12_0_14=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_14 +v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12 +sem_v4_1_12=$RDI_DATADIR/xsim/ip/sem_v4_1_12 +ten_gig_eth_mac_v15_1_7=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_7 +spdif_v2_0_22=$RDI_DATADIR/xsim/ip/spdif_v2_0_22 +v_multi_scaler_v1_0_2=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_2 +v_ccm_v6_0_15=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_15 +axi_timer_v2_0_22=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_22 +quadsgmii_v3_4_7=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_7 +versal_cips_v1_0_0=$RDI_DATADIR/xsim/ip/versal_cips_v1_0_0 +zynq_ultra_ps_e_v3_3_1=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_1 +tcc_decoder_3gppmm_v2_0_19=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_19 +c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6 +axi_mcdma_v1_0_6=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_6 +axi_clock_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_19 +timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 +ieee802d3_200g_rs_fec_v1_0_8=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_8 +gtwizard_ultrascale_v1_7_7=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_7 +sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0 +bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 +div_gen_v5_1_16=$RDI_DATADIR/xsim/ip/div_gen_v5_1_16 +axi_ethernetlite_v3_0_18=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_18 +pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 +axi4stream_vip_v1_1_6=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_6 +floating_point_v7_0_17=$RDI_DATADIR/xsim/ip/floating_point_v7_0_17 +high_speed_selectio_wiz_v3_5_2=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_2 +xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6 +srio_gen2_v4_1_7=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_7 +ieee802d3_clause74_fec_v1_0_5=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_5 +v_gamma_v7_0_15=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_15 +high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 +dp_videoaxi4s_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_1 +ethernet_1_10_25g_v2_4_0=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_4_0 +in_system_ibert_v1_0_10=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_10 +ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0 +trace_s2mm_v1_0_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v1_0_0 +mdm_v3_2_17=$RDI_DATADIR/xsim/ip/mdm_v3_2_17 +dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1 +axis_ila_pp_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_0 +axis_ila_intf_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_0 +rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0 +axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6 +v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 +axi_traffic_gen_v2_0_21=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_21 +stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0 +lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 +uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3 +pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4 +cordic_v6_0_16=$RDI_DATADIR/xsim/ip/cordic_v6_0_16 +ieee802d3_50g_rs_fec_v2_0_2=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_2 +axi_ahblite_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_17 +axi_mcdma_v1_1_1=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_1 +ieee802d3_50g_rs_fec_v1_0_12=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_12 +axi_amm_bridge_v1_0_10=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_10 +xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6 +xbip_multadd_v3_0_15=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_15 +axi_timebase_wdt_v3_0_12=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_12 +v_mix_v3_0_4=$RDI_DATADIR/xsim/ip/v_mix_v3_0_4 +axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 +tmr_sem_v1_0_10=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_10 +axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 +mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7 +aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0 +sem_ultra_v3_1_12=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_12 +xtlm=$RDI_DATADIR/xsim/ip/xtlm +axi_ethernet_buffer_v2_0_21=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_21 +iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 +vfb_v1_0_14=$RDI_DATADIR/xsim/ip/vfb_v1_0_14 +xlconcat_v2_1_3=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_3 +v_ycrcb2rgb_v7_1_13=$RDI_DATADIR/xsim/ip/v_ycrcb2rgb_v7_1_13 +emb_fifo_gen_v1_0_2=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_2 +lte_rach_detector_v3_1_6=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_6 +processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6 +lte_ul_channel_decoder_v4_0_16=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_16 +soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0 +ieee802d3_rs_fec_v1_0_16=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_16 +pr_bitstream_monitor_v1_0_1=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_1 +sync_ip=$RDI_DATADIR/xsim/ip/sync_ip +v_vscaler_v1_0_14=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_14 +c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6 +ibert_lib_v1_0_7=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_7 +c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6 +v_hcresampler_v1_0_14=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_14 +axis_itct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_0 +lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 +axi_uart16550_v2_0_22=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_22 +ai_pl=$RDI_DATADIR/xsim/ip/ai_pl +g709_fec_v2_3_6=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_6 +av_pat_gen_v1_0_1=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_1 +fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 +v_vcresampler_v1_0_14=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_14 +v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0 +microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 +axi_iic_v2_0_23=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_23 +axis_protocol_checker_v2_0_4=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_4 +v_uhdsdi_audio_v2_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_1 +xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6 +axis_dbg_stub_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_0 +c_counter_binary_v12_0_14=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_14 +xpm=$RDI_DATADIR/xsim/ip/xpm +axi_chip2chip_v5_0_7=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_7 +displayport_v7_0_12=$RDI_DATADIR/xsim/ip/displayport_v7_0_12 +switch_core_top_v1_0_8=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_8 +displayport_v8_1_2=$RDI_DATADIR/xsim/ip/displayport_v8_1_2 +xfft_v9_0_18=$RDI_DATADIR/xsim/ip/xfft_v9_0_18 +lte_3gpp_mimo_decoder_v3_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_16 +noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0 +mrmac_v1_1_0=$RDI_DATADIR/xsim/ip/mrmac_v1_1_0 +axi_datamover_v5_1_22=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_22 +xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10 +tcc_encoder_3gpplte_v4_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_16 +rs_decoder_v9_0_17=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_17 +jesd204_v7_2_7=$RDI_DATADIR/xsim/ip/jesd204_v7_2_7 +dds_compiler_v6_0_19=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_19 +generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 +fc32_rs_fec_v1_0_12=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_12 +fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1 +axi_epc_v2_0_23=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_23 +lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 +video_frame_crc_v1_0_2=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_2 +axi_apb_bridge_v3_0_16=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_16 +axi_usb2_device_v5_0_21=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_21 +axis_ila_ct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_0 +multi_channel_25g_rs_fec_v1_0_6=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_6 +util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 +sim_trig_top_v1_0=$RDI_DATADIR/xsim/ip/sim_trig_top_v1_0 +v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0 +xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6 +lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 +util_idelay_ctrl_v1_0_2=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_2 +v_csc_v1_0_14=$RDI_DATADIR/xsim/ip/v_csc_v1_0_14 +axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 +gig_ethernet_pcs_pma_v16_1_7=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_7 +mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 +audio_formatter_v1_0_2=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_2 +xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 +axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0 +tsn_endpoint_ethernet_mac_block_v1_0_5=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_5 +mem_pl_v1_0_0=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_0 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xvlog.log b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xvlog.log new file mode 100644 index 0000000..370669e --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xvlog.log @@ -0,0 +1,10 @@ +INFO: [VRFC 10-2263] Analyzing Verilog file "F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/data_ram/sim/data_ram.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module data_ram +INFO: [VRFC 10-2263] Analyzing Verilog file "F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module inst_rom +INFO: [VRFC 10-2263] Analyzing Verilog file "F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/clkdiv/clkdiv_clk_wiz.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module clkdiv_clk_wiz +INFO: [VRFC 10-2263] Analyzing Verilog file "F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/clkdiv/clkdiv.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module clkdiv +INFO: [VRFC 10-2263] Analyzing Verilog file "F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32_SYS.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module MiniMIPS32_SYS diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xvlog.pb b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 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a/TEMU/mips_sc/src/Makefile.testcase +++ b/TEMU/mips_sc/src/Makefile.testcase @@ -1,3 +1,2 @@ # change the tesctcase name USER_PROGRAM := bltzal - diff --git a/TEMU/mips_sc/src/include/inst_def.h b/TEMU/mips_sc/src/include/inst_def.h index 87b3a7d..c166c3a 100644 --- a/TEMU/mips_sc/src/include/inst_def.h +++ b/TEMU/mips_sc/src/include/inst_def.h @@ -618,3 +618,12 @@ li t0, v0; \ mthi t0; \ mfhi s0 + + + + + + + + + diff --git a/TEMU/mips_sc/src/include/inst_test.h b/TEMU/mips_sc/src/include/inst_test.h index f274297..127054d 100644 --- a/TEMU/mips_sc/src/include/inst_test.h +++ b/TEMU/mips_sc/src/include/inst_test.h @@ -288,4 +288,6 @@ nop; \ addiu s5, s5, 8; \ bne s4, s5, inst_error; \ - nop \ No newline at end of file + nop + + diff --git a/TEMU/mips_sc/src/inst/bgezal.S b/TEMU/mips_sc/src/inst/bgezal.S new file mode 100644 index 0000000..5674729 --- /dev/null +++ b/TEMU/mips_sc/src/inst/bgezal.S @@ -0,0 +1,217 @@ +#include "asm/regdef.h" +#include "asm/asm.h" +#include "asm/context.h" +#include "inst_test.h" +#include "trap.h" + .set noreorder + .set noat + .global main + .text + +main: + ###test inst + TEST_BGEZAL(0x9ec9db66, 0x029aaf84, 0xb5a8cca0, 0x00000000, 0x00000000, 0xbfc0041c, 0xbfc003dc, 0xbfc00414) + TEST_BGEZAL(0x48f555d0, 0x288dbddc, 0xabcf87b8, 0x288dbddc, 0xabcf87b8, 0xbfc004a0, 0xbfc00498, 0xbfc004d0) + TEST_BGEZAL(0xe47b2aa0, 0xc6bf36e0, 0x1eb3e3a0, 0x00000000, 0x00000000, 0xbfc00594, 0xbfc00554, 0xbfc0058c) + TEST_BGEZAL(0x5955ebd6, 0xa44467a3, 0xdbe004f7, 0xa44467a3, 0xdbe004f7, 0xbfc00618, 0xbfc00610, 0xbfc00648) + TEST_BGEZAL(0x3baa4ab0, 0x7998f600, 0xf047d898, 0x7998f600, 0xf047d898, 0xbfc006d4, 0xbfc006cc, 0xbfc00704) + TEST_BGEZAL(0xbff7aa00, 0x82bf9c2c, 0x68d44fa0, 0x00000000, 0x00000000, 0xbfc007c8, 0xbfc00788, 0xbfc007c0) + TEST_BGEZAL(0xf72cd104, 0x72df5726, 0xdfbd8610, 0x00000000, 0x00000000, 0xbfc00884, 0xbfc00844, 0xbfc0087c) + TEST_BGEZAL(0xd8b3ba00, 0x3c5ba4aa, 0x7af32580, 0x00000000, 0x00000000, 0xbfc00940, 0xbfc00900, 0xbfc00938) + TEST_BGEZAL(0x7ade7232, 0xcc24a355, 0x38bd0e50, 0xcc24a355, 0x38bd0e50, 0xbfc009c4, 0xbfc009bc, 0xbfc009f4) + TEST_BGEZAL(0xdecd38ca, 0x448e3e59, 0xf188c7f8, 0x00000000, 0x00000000, 0xbfc00ab8, 0xbfc00a78, 0xbfc00ab0) + TEST_BGEZAL(0x78311f7a, 0xe5b25fb8, 0x7ca7863d, 0xe5b25fb8, 0x7ca7863d, 0xbfc00b3c, 0xbfc00b34, 0xbfc00b6c) + TEST_BGEZAL(0xd72704a0, 0x104f8b6e, 0x2c9eed51, 0x00000000, 0x00000000, 0xbfc00c30, 0xbfc00bf0, 0xbfc00c28) + TEST_BGEZAL(0xd431c144, 0xd85ed6a8, 0x1d5bc2a6, 0x00000000, 0x00000000, 0xbfc00cec, 0xbfc00cac, 0xbfc00ce4) + TEST_BGEZAL(0x91562900, 0x7783a600, 0xdd8f904a, 0x00000000, 0x00000000, 0xbfc00da8, 0xbfc00d68, 0xbfc00da0) + TEST_BGEZAL(0x0ce6fe4c, 0x2e4b13e8, 0x51ce2d10, 0x2e4b13e8, 0x51ce2d10, 0xbfc00e2c, 0xbfc00e24, 0xbfc00e5c) + TEST_BGEZAL(0x26f4c05b, 0x968b3a48, 0x6a70b840, 0x968b3a48, 0x6a70b840, 0xbfc00ee8, 0xbfc00ee0, 0xbfc00f18) + TEST_BGEZAL(0xc76b6cdb, 0xd3f8c2d8, 0xdfffa3a8, 0x00000000, 0x00000000, 0xbfc00fdc, 0xbfc00f9c, 0xbfc00fd4) + TEST_BGEZAL(0x9660824c, 0x68878e40, 0x94471180, 0x00000000, 0x00000000, 0xbfc01098, 0xbfc01058, 0xbfc01090) + TEST_BGEZAL(0x6c99e116, 0xf7b47398, 0xb75b3f50, 0xf7b47398, 0xb75b3f50, 0xbfc0111c, 0xbfc01114, 0xbfc0114c) + TEST_BGEZAL(0xad1ca3a4, 0x86a25bbc, 0xff4d116e, 0x00000000, 0x00000000, 0xbfc01210, 0xbfc011d0, 0xbfc01208) + TEST_BGEZAL(0xbd1deccb, 0x55c6980e, 0x2f318e50, 0x00000000, 0x00000000, 0xbfc012cc, 0xbfc0128c, 0xbfc012c4) + TEST_BGEZAL(0x355b4ad4, 0x67f280e6, 0x075245b0, 0x67f280e6, 0x075245b0, 0xbfc01350, 0xbfc01348, 0xbfc01380) + TEST_BGEZAL(0x3df92cb0, 0x66396481, 0x9cf8f555, 0x66396481, 0x9cf8f555, 0xbfc0140c, 0xbfc01404, 0xbfc0143c) + TEST_BGEZAL(0xe9998d40, 0x9d726900, 0xdff44568, 0x00000000, 0x00000000, 0xbfc01500, 0xbfc014c0, 0xbfc014f8) + TEST_BGEZAL(0xac74d8e0, 0x209b13ea, 0x511abe08, 0x00000000, 0x00000000, 0xbfc015bc, 0xbfc0157c, 0xbfc015b4) + TEST_BGEZAL(0xbf9424d8, 0x49cacf20, 0x42693dc3, 0x00000000, 0x00000000, 0xbfc01678, 0xbfc01638, 0xbfc01670) + TEST_BGEZAL(0x48e3f22e, 0xa523c75c, 0x85bce4c0, 0xa523c75c, 0x85bce4c0, 0xbfc016fc, 0xbfc016f4, 0xbfc0172c) + TEST_BGEZAL(0x8ec77978, 0xb7b716b0, 0x88cb0974, 0x00000000, 0x00000000, 0xbfc017f0, 0xbfc017b0, 0xbfc017e8) + TEST_BGEZAL(0xc15efd20, 0x0ef69dd0, 0xfa8ce8f4, 0x00000000, 0x00000000, 0xbfc018ac, 0xbfc0186c, 0xbfc018a4) + TEST_BGEZAL(0x9c29f658, 0xee20a3d8, 0x2cb20ac8, 0x00000000, 0x00000000, 0xbfc01968, 0xbfc01928, 0xbfc01960) + TEST_BGEZAL(0x1c624d80, 0x838d0cd4, 0xc0a5f39a, 0x838d0cd4, 0xc0a5f39a, 0xbfc019ec, 0xbfc019e4, 0xbfc01a1c) + TEST_BGEZAL(0xfafd1778, 0x2277d010, 0xa31858e4, 0x00000000, 0x00000000, 0xbfc01ae0, 0xbfc01aa0, 0xbfc01ad8) + TEST_BGEZAL(0xb129bb70, 0x4e4cf3c3, 0x65cb3d2a, 0x00000000, 0x00000000, 0xbfc01b9c, 0xbfc01b5c, 0xbfc01b94) + TEST_BGEZAL(0x7ab4682c, 0x3b800bd9, 0xdc102e20, 0x3b800bd9, 0xdc102e20, 0xbfc01c20, 0xbfc01c18, 0xbfc01c50) + TEST_BGEZAL(0xf0c23ef0, 0x3d762dfa, 0xbf9fbd50, 0x00000000, 0x00000000, 0xbfc01d14, 0xbfc01cd4, 0xbfc01d0c) + TEST_BGEZAL(0x3e78666e, 0x5116d1f8, 0xcdabd338, 0x5116d1f8, 0xcdabd338, 0xbfc01d98, 0xbfc01d90, 0xbfc01dc8) + TEST_BGEZAL(0x10331dba, 0x172c9ad7, 0x67ac49e0, 0x172c9ad7, 0x67ac49e0, 0xbfc01e54, 0xbfc01e4c, 0xbfc01e84) + TEST_BGEZAL(0x9af65ad8, 0xc9182114, 0x3db85058, 0x00000000, 0x00000000, 0xbfc01f48, 0xbfc01f08, 0xbfc01f40) + TEST_BGEZAL(0x8613d8e4, 0xd1796a5e, 0x3a497608, 0x00000000, 0x00000000, 0xbfc02004, 0xbfc01fc4, 0xbfc01ffc) + TEST_BGEZAL(0x0361585c, 0xef10cd54, 0x12416476, 0xef10cd54, 0x12416476, 0xbfc02088, 0xbfc02080, 0xbfc020b8) + TEST_BGEZAL(0x774d2398, 0x463c2acc, 0xa046b6ca, 0x463c2acc, 0xa046b6ca, 0xbfc02144, 0xbfc0213c, 0xbfc02174) + TEST_BGEZAL(0xaaa490d0, 0xe3096291, 0x92d167d4, 0x00000000, 0x00000000, 0xbfc02238, 0xbfc021f8, 0xbfc02230) + TEST_BGEZAL(0x530cee60, 0xe2865f30, 0x10c8cf40, 0xe2865f30, 0x10c8cf40, 0xbfc022bc, 0xbfc022b4, 0xbfc022ec) + TEST_BGEZAL(0x103d4d72, 0x801ced08, 0x12db7c88, 0x801ced08, 0x12db7c88, 0xbfc02378, 0xbfc02370, 0xbfc023a8) + TEST_BGEZAL(0x75b35bb0, 0xb5f0b262, 0x61e02650, 0xb5f0b262, 0x61e02650, 0xbfc02434, 0xbfc0242c, 0xbfc02464) + TEST_BGEZAL(0x558ac57d, 0x9b874393, 0x95482680, 0x9b874393, 0x95482680, 0xbfc024f0, 0xbfc024e8, 0xbfc02520) + TEST_BGEZAL(0xdf4f0f00, 0xddbb3172, 0x573c55da, 0x00000000, 0x00000000, 0xbfc025e4, 0xbfc025a4, 0xbfc025dc) + TEST_BGEZAL(0xd05951cb, 0x9adfc9b8, 0x8aa54cc9, 0x00000000, 0x00000000, 0xbfc026a0, 0xbfc02660, 0xbfc02698) + TEST_BGEZAL(0xb5128d6f, 0x1bfa1c20, 0x47ffc5a0, 0x00000000, 0x00000000, 0xbfc0275c, 0xbfc0271c, 0xbfc02754) + TEST_BGEZAL(0xdfd53a06, 0x63100e90, 0xd0f1231c, 0x00000000, 0x00000000, 0xbfc02818, 0xbfc027d8, 0xbfc02810) + TEST_BGEZAL(0x74ba0840, 0x209b93c8, 0x74521540, 0x209b93c8, 0x74521540, 0xbfc0289c, 0xbfc02894, 0xbfc028cc) + TEST_BGEZAL(0xe265cd50, 0x4098744a, 0x31b34048, 0x00000000, 0x00000000, 0xbfc02990, 0xbfc02950, 0xbfc02988) + TEST_BGEZAL(0x6885271e, 0xc1dcfe80, 0x88a4cd80, 0xc1dcfe80, 0x88a4cd80, 0xbfc02a14, 0xbfc02a0c, 0xbfc02a44) + TEST_BGEZAL(0xefc36830, 0x54d12648, 0xe41af3f0, 0x00000000, 0x00000000, 0xbfc02b08, 0xbfc02ac8, 0xbfc02b00) + TEST_BGEZAL(0xad25a725, 0xe86ffef3, 0x6920e15c, 0x00000000, 0x00000000, 0xbfc02bc4, 0xbfc02b84, 0xbfc02bbc) + TEST_BGEZAL(0x771729a0, 0x52213f70, 0x1bbc4d28, 0x52213f70, 0x1bbc4d28, 0xbfc02c48, 0xbfc02c40, 0xbfc02c78) + TEST_BGEZAL(0x051c0bc2, 0xc53e0410, 0x7c0d79e3, 0xc53e0410, 0x7c0d79e3, 0xbfc02d04, 0xbfc02cfc, 0xbfc02d34) + TEST_BGEZAL(0xad4ff0d4, 0x4309ff12, 0x3abf1fbc, 0x00000000, 0x00000000, 0xbfc02df8, 0xbfc02db8, 0xbfc02df0) + TEST_BGEZAL(0xe4dbf4b8, 0x1503ba59, 0x9628c7e0, 0x00000000, 0x00000000, 0xbfc02eb4, 0xbfc02e74, 0xbfc02eac) + TEST_BGEZAL(0xe65eaffc, 0x40ba9d66, 0x5fdbaae0, 0x00000000, 0x00000000, 0xbfc02f70, 0xbfc02f30, 0xbfc02f68) + TEST_BGEZAL(0xbeb0f688, 0x52917aa4, 0xee0a26b0, 0x00000000, 0x00000000, 0xbfc0302c, 0xbfc02fec, 0xbfc03024) + TEST_BGEZAL(0xefdfd000, 0x7880b230, 0x1f93e14a, 0x00000000, 0x00000000, 0xbfc030e8, 0xbfc030a8, 0xbfc030e0) + TEST_BGEZAL(0xe0a736fb, 0x45c93fa8, 0xf646a898, 0x00000000, 0x00000000, 0xbfc031a4, 0xbfc03164, 0xbfc0319c) + TEST_BGEZAL(0x6360c99b, 0xf368cb16, 0x8c03a3f8, 0xf368cb16, 0x8c03a3f8, 0xbfc03228, 0xbfc03220, 0xbfc03258) + TEST_BGEZAL(0x930cf074, 0x52d63224, 0xc7aabdc1, 0x00000000, 0x00000000, 0xbfc0331c, 0xbfc032dc, 0xbfc03314) + TEST_BGEZAL(0xb03418d0, 0x096d96a0, 0xaec62677, 0x00000000, 0x00000000, 0xbfc033d8, 0xbfc03398, 0xbfc033d0) + TEST_BGEZAL(0x79d1e580, 0x20bf711c, 0x1a2e2914, 0x20bf711c, 0x1a2e2914, 0xbfc0345c, 0xbfc03454, 0xbfc0348c) + TEST_BGEZAL(0x81e06df9, 0x212e0cec, 0x9ea07a8c, 0x00000000, 0x00000000, 0xbfc03550, 0xbfc03510, 0xbfc03548) + TEST_BGEZAL(0x6a064cef, 0x18955140, 0x86b2e1f0, 0x18955140, 0x86b2e1f0, 0xbfc035d4, 0xbfc035cc, 0xbfc03604) + TEST_BGEZAL(0x204d8af0, 0xffc3f740, 0xbe11f92f, 0xffc3f740, 0xbe11f92f, 0xbfc03690, 0xbfc03688, 0xbfc036c0) + TEST_BGEZAL(0x2d24d026, 0x760258c8, 0x771f9bc2, 0x760258c8, 0x771f9bc2, 0xbfc0374c, 0xbfc03744, 0xbfc0377c) + TEST_BGEZAL(0xdd6a4690, 0x85197cce, 0xf8c6da8e, 0x00000000, 0x00000000, 0xbfc03840, 0xbfc03800, 0xbfc03838) + TEST_BGEZAL(0xe3a7803c, 0x29fdc410, 0x2c377344, 0x00000000, 0x00000000, 0xbfc038fc, 0xbfc038bc, 0xbfc038f4) + TEST_BGEZAL(0xb1d59e1c, 0xff2889a0, 0x47311a00, 0x00000000, 0x00000000, 0xbfc039b8, 0xbfc03978, 0xbfc039b0) + TEST_BGEZAL(0xba405044, 0x70ba29d0, 0x665a0285, 0x00000000, 0x00000000, 0xbfc03a74, 0xbfc03a34, 0xbfc03a6c) + TEST_BGEZAL(0x966c21d0, 0x95320960, 0x472b06c6, 0x00000000, 0x00000000, 0xbfc03b30, 0xbfc03af0, 0xbfc03b28) + TEST_BGEZAL(0x2640fab0, 0xd2c9245e, 0x261888e8, 0xd2c9245e, 0x261888e8, 0xbfc03bb4, 0xbfc03bac, 0xbfc03be4) + TEST_BGEZAL(0x8919d5ac, 0x8a0b4f16, 0x981f1b40, 0x00000000, 0x00000000, 0xbfc03ca8, 0xbfc03c68, 0xbfc03ca0) + TEST_BGEZAL(0xb4f05260, 0xea8b953c, 0xc7804f58, 0x00000000, 0x00000000, 0xbfc03d64, 0xbfc03d24, 0xbfc03d5c) + TEST_BGEZAL(0x05cbb32d, 0x10e22c70, 0xe7772208, 0x10e22c70, 0xe7772208, 0xbfc03de8, 0xbfc03de0, 0xbfc03e18) + TEST_BGEZAL(0xda6de980, 0xe0d533d6, 0xd48d1074, 0x00000000, 0x00000000, 0xbfc03edc, 0xbfc03e9c, 0xbfc03ed4) + TEST_BGEZAL(0x30043918, 0x6415db60, 0x73aaeff8, 0x6415db60, 0x73aaeff8, 0xbfc03f60, 0xbfc03f58, 0xbfc03f90) + TEST_BGEZAL(0x3f598570, 0xb5adc358, 0x22f12300, 0xb5adc358, 0x22f12300, 0xbfc0401c, 0xbfc04014, 0xbfc0404c) + TEST_BGEZAL(0xd94a1fc4, 0xff41f972, 0xad185750, 0x00000000, 0x00000000, 0xbfc04110, 0xbfc040d0, 0xbfc04108) + TEST_BGEZAL(0x03070850, 0x60342c78, 0x8ae75d1c, 0x60342c78, 0x8ae75d1c, 0xbfc04194, 0xbfc0418c, 0xbfc041c4) + TEST_BGEZAL(0x9d6c5b50, 0x62d50b2c, 0xbf7bbbe0, 0x00000000, 0x00000000, 0xbfc04288, 0xbfc04248, 0xbfc04280) + TEST_BGEZAL(0xefc3fb6d, 0x41adc580, 0x44811cea, 0x00000000, 0x00000000, 0xbfc04344, 0xbfc04304, 0xbfc0433c) + TEST_BGEZAL(0x4461ad06, 0x8d1ebf10, 0x6cbe3a80, 0x8d1ebf10, 0x6cbe3a80, 0xbfc043c8, 0xbfc043c0, 0xbfc043f8) + TEST_BGEZAL(0x3eea0f88, 0x16af2f88, 0x70e0f0c8, 0x16af2f88, 0x70e0f0c8, 0xbfc04484, 0xbfc0447c, 0xbfc044b4) + TEST_BGEZAL(0x00539980, 0x7419e600, 0x857ede78, 0x7419e600, 0x857ede78, 0xbfc04540, 0xbfc04538, 0xbfc04570) + TEST_BGEZAL(0x12755708, 0x7f8d4c60, 0x35baf096, 0x7f8d4c60, 0x35baf096, 0xbfc045fc, 0xbfc045f4, 0xbfc0462c) + TEST_BGEZAL(0xa8566262, 0xa0dc0850, 0x935b76fc, 0x00000000, 0x00000000, 0xbfc046f0, 0xbfc046b0, 0xbfc046e8) + TEST_BGEZAL(0x4312482c, 0x3babfa88, 0x8c744b40, 0x3babfa88, 0x8c744b40, 0xbfc04774, 0xbfc0476c, 0xbfc047a4) + TEST_BGEZAL(0x7258b698, 0x37025294, 0x2442dc78, 0x37025294, 0x2442dc78, 0xbfc04830, 0xbfc04828, 0xbfc04860) + TEST_BGEZAL(0xc8112dce, 0xa7edf5bc, 0xf05ebc8a, 0x00000000, 0x00000000, 0xbfc04924, 0xbfc048e4, 0xbfc0491c) + TEST_BGEZAL(0x76825d9a, 0x1a5e8a78, 0x8b96ed40, 0x1a5e8a78, 0x8b96ed40, 0xbfc049a8, 0xbfc049a0, 0xbfc049d8) + TEST_BGEZAL(0xd5acf404, 0x3786e87b, 0x33e1ad01, 0x00000000, 0x00000000, 0xbfc04a9c, 0xbfc04a5c, 0xbfc04a94) + TEST_BGEZAL(0x2d684380, 0x353a658f, 0x3a78a716, 0x353a658f, 0x3a78a716, 0xbfc04b20, 0xbfc04b18, 0xbfc04b50) + TEST_BGEZAL(0x6d24026c, 0x4c07aa70, 0x262d7a68, 0x4c07aa70, 0x262d7a68, 0xbfc04bdc, 0xbfc04bd4, 0xbfc04c0c) + TEST_BGEZAL(0xe781e987, 0xbb172b3f, 0x9506bf76, 0x00000000, 0x00000000, 0xbfc04cd0, 0xbfc04c90, 0xbfc04cc8) + TEST_BGEZAL(0x849e87e0, 0x95eae311, 0x2a431460, 0x00000000, 0x00000000, 0xbfc04d8c, 0xbfc04d4c, 0xbfc04d84) + TEST_BGEZAL(0xb77b8830, 0xb6cd8f00, 0x599c33ac, 0x00000000, 0x00000000, 0xbfc04e48, 0xbfc04e08, 0xbfc04e40) + TEST_BGEZAL(0x38b32afe, 0xcb06ea2a, 0x12b1bd66, 0xcb06ea2a, 0x12b1bd66, 0xbfc04ecc, 0xbfc04ec4, 0xbfc04efc) + TEST_BGEZAL(0x364547e8, 0x9d0b2668, 0xe1c59c78, 0x9d0b2668, 0xe1c59c78, 0xbfc04f88, 0xbfc04f80, 0xbfc04fb8) + TEST_BGEZAL(0x9488b99c, 0x10cbe1b8, 0x407da648, 0x00000000, 0x00000000, 0xbfc0507c, 0xbfc0503c, 0xbfc05074) + TEST_BGEZAL(0x45557d80, 0x2c5ffe58, 0x41c23300, 0x2c5ffe58, 0x41c23300, 0xbfc05100, 0xbfc050f8, 0xbfc05130) + TEST_BGEZAL(0x4162a47e, 0x4859ca40, 0x62511bd0, 0x4859ca40, 0x62511bd0, 0xbfc051bc, 0xbfc051b4, 0xbfc051ec) + TEST_BGEZAL(0xd40f9260, 0xbdc20ca8, 0x6ad8501b, 0x00000000, 0x00000000, 0xbfc052b0, 0xbfc05270, 0xbfc052a8) + TEST_BGEZAL(0x21e007b0, 0x2f6840b0, 0xd69ebe4f, 0x2f6840b0, 0xd69ebe4f, 0xbfc05334, 0xbfc0532c, 0xbfc05364) + TEST_BGEZAL(0xe3f7d594, 0x7c80bd20, 0xea950588, 0x00000000, 0x00000000, 0xbfc05428, 0xbfc053e8, 0xbfc05420) + TEST_BGEZAL(0x626f9ad8, 0x0f794fbe, 0xa51e32c5, 0x0f794fbe, 0xa51e32c5, 0xbfc054ac, 0xbfc054a4, 0xbfc054dc) + TEST_BGEZAL(0x4f579ee1, 0x84707f22, 0x2986d290, 0x84707f22, 0x2986d290, 0xbfc05568, 0xbfc05560, 0xbfc05598) + TEST_BGEZAL(0x76bf3bd0, 0x7ef6f91e, 0x459f7678, 0x7ef6f91e, 0x459f7678, 0xbfc05624, 0xbfc0561c, 0xbfc05654) + TEST_BGEZAL(0x7fefcdfc, 0xfbba8330, 0x67cc1de8, 0xfbba8330, 0x67cc1de8, 0xbfc056e0, 0xbfc056d8, 0xbfc05710) + TEST_BGEZAL(0xc7f97c10, 0x122c9730, 0x9d2d92cb, 0x00000000, 0x00000000, 0xbfc057d4, 0xbfc05794, 0xbfc057cc) + TEST_BGEZAL(0x98067158, 0x84d71d28, 0x4fe8de78, 0x00000000, 0x00000000, 0xbfc05890, 0xbfc05850, 0xbfc05888) + TEST_BGEZAL(0xccfee4dc, 0x522cff60, 0xacbe58f0, 0x00000000, 0x00000000, 0xbfc0594c, 0xbfc0590c, 0xbfc05944) + TEST_BGEZAL(0x8d4b877a, 0x387f5a58, 0x8ed62e39, 0x00000000, 0x00000000, 0xbfc05a08, 0xbfc059c8, 0xbfc05a00) + TEST_BGEZAL(0xf347705c, 0x72a1d604, 0xeea7aa9e, 0x00000000, 0x00000000, 0xbfc05ac4, 0xbfc05a84, 0xbfc05abc) + TEST_BGEZAL(0x3be3db68, 0x9bdefb1c, 0x5996b860, 0x9bdefb1c, 0x5996b860, 0xbfc05b48, 0xbfc05b40, 0xbfc05b78) + TEST_BGEZAL(0x6e8023a0, 0x7e166bf8, 0x26911a30, 0x7e166bf8, 0x26911a30, 0xbfc05c04, 0xbfc05bfc, 0xbfc05c34) + TEST_BGEZAL(0x3d5084b0, 0x81204f2e, 0x18c7f0aa, 0x81204f2e, 0x18c7f0aa, 0xbfc05cc0, 0xbfc05cb8, 0xbfc05cf0) + TEST_BGEZAL(0x861739d0, 0x62bf92bd, 0xb90f5834, 0x00000000, 0x00000000, 0xbfc05db4, 0xbfc05d74, 0xbfc05dac) + TEST_BGEZAL(0x26df39ca, 0x767dafc8, 0xcf001cc0, 0x767dafc8, 0xcf001cc0, 0xbfc05e38, 0xbfc05e30, 0xbfc05e68) + TEST_BGEZAL(0xa06b4e88, 0xbed08880, 0x0677a59c, 0x00000000, 0x00000000, 0xbfc05f2c, 0xbfc05eec, 0xbfc05f24) + TEST_BGEZAL(0x232859ce, 0x22a64fd2, 0x133f25e0, 0x22a64fd2, 0x133f25e0, 0xbfc05fb0, 0xbfc05fa8, 0xbfc05fe0) + TEST_BGEZAL(0x2b1b825c, 0x173bf5dc, 0x90d36ca0, 0x173bf5dc, 0x90d36ca0, 0xbfc0606c, 0xbfc06064, 0xbfc0609c) + TEST_BGEZAL(0x0b6a9780, 0xc1daa4c0, 0x43d23580, 0xc1daa4c0, 0x43d23580, 0xbfc06128, 0xbfc06120, 0xbfc06158) + TEST_BGEZAL(0x8f7e8f8c, 0x3426946d, 0x9913f9c6, 0x00000000, 0x00000000, 0xbfc0621c, 0xbfc061dc, 0xbfc06214) + TEST_BGEZAL(0x1b2f92a4, 0xaa5510c0, 0x477026b8, 0xaa5510c0, 0x477026b8, 0xbfc062a0, 0xbfc06298, 0xbfc062d0) + TEST_BGEZAL(0x406f92c2, 0x7df268b0, 0xc8f7a25d, 0x7df268b0, 0xc8f7a25d, 0xbfc0635c, 0xbfc06354, 0xbfc0638c) + TEST_BGEZAL(0x5c221ab6, 0x455936a0, 0xd1133fb0, 0x455936a0, 0xd1133fb0, 0xbfc06418, 0xbfc06410, 0xbfc06448) + TEST_BGEZAL(0x2527510a, 0x19a60c80, 0x9659b2f4, 0x19a60c80, 0x9659b2f4, 0xbfc064d4, 0xbfc064cc, 0xbfc06504) + TEST_BGEZAL(0xa55ca800, 0xbc5f15c0, 0x36c63a7a, 0x00000000, 0x00000000, 0xbfc065c8, 0xbfc06588, 0xbfc065c0) + TEST_BGEZAL(0xabe38b6a, 0xe6824b52, 0xd28b8008, 0x00000000, 0x00000000, 0xbfc06684, 0xbfc06644, 0xbfc0667c) + TEST_BGEZAL(0x0bfe49f4, 0x276596c8, 0x3cc61e70, 0x276596c8, 0x3cc61e70, 0xbfc06708, 0xbfc06700, 0xbfc06738) + TEST_BGEZAL(0xa46fdf48, 0x83a774f8, 0x5faba638, 0x00000000, 0x00000000, 0xbfc067fc, 0xbfc067bc, 0xbfc067f4) + TEST_BGEZAL(0x457d808b, 0xc70ffa10, 0xcbbce566, 0xc70ffa10, 0xcbbce566, 0xbfc06880, 0xbfc06878, 0xbfc068b0) + TEST_BGEZAL(0x7d1e89e8, 0x6d04c2e4, 0x904db13e, 0x6d04c2e4, 0x904db13e, 0xbfc0693c, 0xbfc06934, 0xbfc0696c) + TEST_BGEZAL(0x2354ab07, 0x4e4e7f30, 0x3867d3c3, 0x4e4e7f30, 0x3867d3c3, 0xbfc069f8, 0xbfc069f0, 0xbfc06a28) + TEST_BGEZAL(0x2afabf2c, 0xc62f9716, 0x8a69e0bc, 0xc62f9716, 0x8a69e0bc, 0xbfc06ab4, 0xbfc06aac, 0xbfc06ae4) + TEST_BGEZAL(0xa27823c4, 0x623a5c87, 0x77ff0050, 0x00000000, 0x00000000, 0xbfc06ba8, 0xbfc06b68, 0xbfc06ba0) + TEST_BGEZAL(0xbbbbd5d8, 0x27c8b198, 0xab3cc6d1, 0x00000000, 0x00000000, 0xbfc06c64, 0xbfc06c24, 0xbfc06c5c) + TEST_BGEZAL(0x1a540090, 0x2b2c0a24, 0x9eac2008, 0x2b2c0a24, 0x9eac2008, 0xbfc06ce8, 0xbfc06ce0, 0xbfc06d18) + TEST_BGEZAL(0xa690d784, 0x8e453070, 0xf6616562, 0x00000000, 0x00000000, 0xbfc06ddc, 0xbfc06d9c, 0xbfc06dd4) + TEST_BGEZAL(0x4aa82470, 0x82eff34c, 0x0910120a, 0x82eff34c, 0x0910120a, 0xbfc06e60, 0xbfc06e58, 0xbfc06e90) + TEST_BGEZAL(0xc18e7458, 0xb2d0e63c, 0x5fe9d059, 0x00000000, 0x00000000, 0xbfc06f54, 0xbfc06f14, 0xbfc06f4c) + TEST_BGEZAL(0x9e2e9ffb, 0x9d13028c, 0x9bb45b6c, 0x00000000, 0x00000000, 0xbfc07010, 0xbfc06fd0, 0xbfc07008) + TEST_BGEZAL(0x7d54ec72, 0xd4b18300, 0xdd3fb534, 0xd4b18300, 0xdd3fb534, 0xbfc07094, 0xbfc0708c, 0xbfc070c4) + TEST_BGEZAL(0x36c1e088, 0xb9692b00, 0x7567c79a, 0xb9692b00, 0x7567c79a, 0xbfc07150, 0xbfc07148, 0xbfc07180) + TEST_BGEZAL(0x56dca3ac, 0xf53a147e, 0x2da7eb28, 0xf53a147e, 0x2da7eb28, 0xbfc0720c, 0xbfc07204, 0xbfc0723c) + TEST_BGEZAL(0xd4d840c0, 0xf2e7cde0, 0x223d3fac, 0x00000000, 0x00000000, 0xbfc07300, 0xbfc072c0, 0xbfc072f8) + TEST_BGEZAL(0x3ff98fd8, 0xe3458bd0, 0x48f6bd96, 0xe3458bd0, 0x48f6bd96, 0xbfc07384, 0xbfc0737c, 0xbfc073b4) + TEST_BGEZAL(0x3685e90c, 0x1ac65cc5, 0x5ab89bcc, 0x1ac65cc5, 0x5ab89bcc, 0xbfc07440, 0xbfc07438, 0xbfc07470) + TEST_BGEZAL(0xad66e0cb, 0x35dd1bc0, 0xaecdd494, 0x00000000, 0x00000000, 0xbfc07534, 0xbfc074f4, 0xbfc0752c) + TEST_BGEZAL(0xf4bef364, 0xde7dc0ec, 0x756a9dd0, 0x00000000, 0x00000000, 0xbfc075f0, 0xbfc075b0, 0xbfc075e8) + TEST_BGEZAL(0x44b3eecd, 0x6c8ae900, 0x72e814e0, 0x6c8ae900, 0x72e814e0, 0xbfc07674, 0xbfc0766c, 0xbfc076a4) + TEST_BGEZAL(0x6c2f25b0, 0xf02c7460, 0x16b7d970, 0xf02c7460, 0x16b7d970, 0xbfc07730, 0xbfc07728, 0xbfc07760) + TEST_BGEZAL(0x30c2b258, 0xd3deef47, 0x56f462cc, 0xd3deef47, 0x56f462cc, 0xbfc077ec, 0xbfc077e4, 0xbfc0781c) + TEST_BGEZAL(0xe1006a80, 0x3c9fae02, 0x01a8c97c, 0x00000000, 0x00000000, 0xbfc078e0, 0xbfc078a0, 0xbfc078d8) + TEST_BGEZAL(0x5e29043e, 0xf7c217f4, 0x56d1b348, 0xf7c217f4, 0x56d1b348, 0xbfc07964, 0xbfc0795c, 0xbfc07994) + TEST_BGEZAL(0xa54b10c2, 0xd26a7aa0, 0x242b7eee, 0x00000000, 0x00000000, 0xbfc07a58, 0xbfc07a18, 0xbfc07a50) + TEST_BGEZAL(0xafccf104, 0xd77e0478, 0xfe37a7a0, 0x00000000, 0x00000000, 0xbfc07b14, 0xbfc07ad4, 0xbfc07b0c) + TEST_BGEZAL(0x17ad1610, 0x0a367600, 0x555b57c6, 0x0a367600, 0x555b57c6, 0xbfc07b98, 0xbfc07b90, 0xbfc07bc8) + TEST_BGEZAL(0x44a54bd0, 0xd5be015c, 0x174ab26b, 0xd5be015c, 0x174ab26b, 0xbfc07c54, 0xbfc07c4c, 0xbfc07c84) + TEST_BGEZAL(0x389ca1b0, 0x94954be2, 0xb1aac7cc, 0x94954be2, 0xb1aac7cc, 0xbfc07d10, 0xbfc07d08, 0xbfc07d40) + TEST_BGEZAL(0x3e366f4c, 0xed709a88, 0x545cfa94, 0xed709a88, 0x545cfa94, 0xbfc07dcc, 0xbfc07dc4, 0xbfc07dfc) + TEST_BGEZAL(0xca45c980, 0xa9710cc0, 0xfd13f1cb, 0x00000000, 0x00000000, 0xbfc07ec0, 0xbfc07e80, 0xbfc07eb8) + TEST_BGEZAL(0x83ebbf0a, 0xb939ca28, 0xf1d0c517, 0x00000000, 0x00000000, 0xbfc07f7c, 0xbfc07f3c, 0xbfc07f74) + TEST_BGEZAL(0xeacc2eb9, 0x21f90620, 0x782c2ff0, 0x00000000, 0x00000000, 0xbfc08038, 0xbfc07ff8, 0xbfc08030) + TEST_BGEZAL(0xc24d9a50, 0x96e65bb0, 0x79dca77c, 0x00000000, 0x00000000, 0xbfc080f4, 0xbfc080b4, 0xbfc080ec) + TEST_BGEZAL(0x77fae458, 0x11387ac8, 0x28d00080, 0x11387ac8, 0x28d00080, 0xbfc08178, 0xbfc08170, 0xbfc081a8) + TEST_BGEZAL(0x48bff3a4, 0x68f9f840, 0x65980b18, 0x68f9f840, 0x65980b18, 0xbfc08234, 0xbfc0822c, 0xbfc08264) + TEST_BGEZAL(0x6044dfa0, 0x3478fb80, 0x1daecc10, 0x3478fb80, 0x1daecc10, 0xbfc082f0, 0xbfc082e8, 0xbfc08320) + TEST_BGEZAL(0x77d217b0, 0xed14e430, 0x7d2668a0, 0xed14e430, 0x7d2668a0, 0xbfc083ac, 0xbfc083a4, 0xbfc083dc) + TEST_BGEZAL(0x69a58eb6, 0x3d61d900, 0x27e886a3, 0x3d61d900, 0x27e886a3, 0xbfc08468, 0xbfc08460, 0xbfc08498) + TEST_BGEZAL(0x1a22f920, 0x6448d8e0, 0x6961f174, 0x6448d8e0, 0x6961f174, 0xbfc08524, 0xbfc0851c, 0xbfc08554) + TEST_BGEZAL(0x96e424cd, 0xdae21256, 0xb9c0ea84, 0x00000000, 0x00000000, 0xbfc08618, 0xbfc085d8, 0xbfc08610) + TEST_BGEZAL(0x72144dee, 0xf1f2eceb, 0x84cdc5c0, 0xf1f2eceb, 0x84cdc5c0, 0xbfc0869c, 0xbfc08694, 0xbfc086cc) + TEST_BGEZAL(0xbdc51fde, 0x64ff3a3c, 0xcf8014a7, 0x00000000, 0x00000000, 0xbfc08790, 0xbfc08750, 0xbfc08788) + TEST_BGEZAL(0x5ba64bf2, 0x238ab968, 0xe3235e00, 0x238ab968, 0xe3235e00, 0xbfc08814, 0xbfc0880c, 0xbfc08844) + TEST_BGEZAL(0xd7e5a6ce, 0xd2de3c44, 0x477539a5, 0x00000000, 0x00000000, 0xbfc08908, 0xbfc088c8, 0xbfc08900) + TEST_BGEZAL(0x4faa5480, 0x4e661200, 0x74883efc, 0x4e661200, 0x74883efc, 0xbfc0898c, 0xbfc08984, 0xbfc089bc) + TEST_BGEZAL(0x44bae210, 0xc34a99a0, 0x1e0830ef, 0xc34a99a0, 0x1e0830ef, 0xbfc08a48, 0xbfc08a40, 0xbfc08a78) + TEST_BGEZAL(0x61e7c0fd, 0xb8026130, 0xd3fb617c, 0xb8026130, 0xd3fb617c, 0xbfc08b04, 0xbfc08afc, 0xbfc08b34) + TEST_BGEZAL(0x180e3fdc, 0x90216418, 0x5b65ccfc, 0x90216418, 0x5b65ccfc, 0xbfc08bc0, 0xbfc08bb8, 0xbfc08bf0) + TEST_BGEZAL(0xf51d4eae, 0xc221096a, 0xec0fec6c, 0x00000000, 0x00000000, 0xbfc08cb4, 0xbfc08c74, 0xbfc08cac) + TEST_BGEZAL(0xdebfa252, 0x76e76d08, 0x4216c340, 0x00000000, 0x00000000, 0xbfc08d70, 0xbfc08d30, 0xbfc08d68) + TEST_BGEZAL(0xc80f06a0, 0x96de4250, 0x7dd7b2d0, 0x00000000, 0x00000000, 0xbfc08e2c, 0xbfc08dec, 0xbfc08e24) + TEST_BGEZAL(0xda25c957, 0x869e74b0, 0x9f657c90, 0x00000000, 0x00000000, 0xbfc08ee8, 0xbfc08ea8, 0xbfc08ee0) + TEST_BGEZAL(0xe2c16e00, 0x753518e8, 0xc36e7a80, 0x00000000, 0x00000000, 0xbfc08fa4, 0xbfc08f64, 0xbfc08f9c) + TEST_BGEZAL(0x8493ac53, 0xeda6f700, 0x023bb300, 0x00000000, 0x00000000, 0xbfc09060, 0xbfc09020, 0xbfc09058) + TEST_BGEZAL(0xce17d056, 0x73e8ac0c, 0x52136032, 0x00000000, 0x00000000, 0xbfc0911c, 0xbfc090dc, 0xbfc09114) + TEST_BGEZAL(0x1732bc45, 0xd513fa00, 0xed7448b8, 0xd513fa00, 0xed7448b8, 0xbfc091a0, 0xbfc09198, 0xbfc091d0) + TEST_BGEZAL(0x179839ac, 0x066aa5c6, 0x0296d70d, 0x066aa5c6, 0x0296d70d, 0xbfc0925c, 0xbfc09254, 0xbfc0928c) + TEST_BGEZAL(0x221b14f9, 0xcb26ec57, 0x1633f6be, 0xcb26ec57, 0x1633f6be, 0xbfc09318, 0xbfc09310, 0xbfc09348) + TEST_BGEZAL(0x68f6e51f, 0x629967a0, 0xa5936df4, 0x629967a0, 0xa5936df4, 0xbfc093d4, 0xbfc093cc, 0xbfc09404) + TEST_BGEZAL(0xe83781e4, 0xa0123e98, 0xa18dbf90, 0x00000000, 0x00000000, 0xbfc094c8, 0xbfc09488, 0xbfc094c0) + TEST_BGEZAL(0xf624bdb0, 0xaaa3de30, 0x7e6ddd50, 0x00000000, 0x00000000, 0xbfc09584, 0xbfc09544, 0xbfc0957c) + TEST_BGEZAL(0x82f5a6f0, 0xb188d600, 0x206fa380, 0x00000000, 0x00000000, 0xbfc09640, 0xbfc09600, 0xbfc09638) + TEST_BGEZAL(0x00000000, 0x36a36650, 0x44fa7d50, 0x36a36650, 0x44fa7d50, 0xbfc096c4, 0xbfc096bc, 0xbfc096f0) + HIT_GOOD_TRAP + +inst_error: + HIT_BAD_TRAP \ No newline at end of file diff --git a/TEMU/mips_sc/src/inst/bltzal.S b/TEMU/mips_sc/src/inst/bltzal.S index 9a6df1d..6e953ab 100644 --- a/TEMU/mips_sc/src/inst/bltzal.S +++ b/TEMU/mips_sc/src/inst/bltzal.S @@ -1,5 +1,6 @@ #include "asm/regdef.h" #include "asm/asm.h" +#include "asm/context.h" #include "inst_test.h" #include "trap.h" @@ -11,7 +12,206 @@ main: ###test inst TEST_BLTZAL(0xc564aaee, 0xf1026890, 0x39dd5800, 0xf1026890, 0x39dd5800, 0xbfc003e4, 0xbfc003dc, 0xbfc0040c) - + TEST_BLTZAL(0x655e408b, 0x6c41162c, 0x8d5cd86f, 0x00000000, 0x00000000, 0xbfc004ec, 0xbfc004b4, 0xbfc004e4) + TEST_BLTZAL(0xd941dbc8, 0xe6b2af00, 0x4c80b4b6, 0xe6b2af00, 0x4c80b4b6, 0xbfc00594, 0xbfc0058c, 0xbfc005bc) + TEST_BLTZAL(0x935cf5a0, 0x4c9765c4, 0xe2f2ebac, 0x4c9765c4, 0xe2f2ebac, 0xbfc0066c, 0xbfc00664, 0xbfc00694) + TEST_BLTZAL(0x18c1552a, 0x35163822, 0x34ffade0, 0x00000000, 0x00000000, 0xbfc00774, 0xbfc0073c, 0xbfc0076c) + TEST_BLTZAL(0xa80025a1, 0xe079deb3, 0x774bba9e, 0xe079deb3, 0x774bba9e, 0xbfc0081c, 0xbfc00814, 0xbfc00844) + TEST_BLTZAL(0xc58a6f20, 0x50bc904c, 0x42914b48, 0x50bc904c, 0x42914b48, 0xbfc008f4, 0xbfc008ec, 0xbfc0091c) + TEST_BLTZAL(0xc3ed9400, 0x98ba8940, 0x7276c784, 0x98ba8940, 0x7276c784, 0xbfc009cc, 0xbfc009c4, 0xbfc009f4) + TEST_BLTZAL(0x8ff9842b, 0x978af84a, 0xd770ef60, 0x978af84a, 0xd770ef60, 0xbfc00aa4, 0xbfc00a9c, 0xbfc00acc) + TEST_BLTZAL(0x663da924, 0xf95f2930, 0x4654a65c, 0x00000000, 0x00000000, 0xbfc00bac, 0xbfc00b74, 0xbfc00ba4) + TEST_BLTZAL(0xd97064ee, 0xb95ffbe8, 0x619a80f4, 0xb95ffbe8, 0x619a80f4, 0xbfc00c54, 0xbfc00c4c, 0xbfc00c7c) + TEST_BLTZAL(0xdb553f88, 0xee356324, 0x32568200, 0xee356324, 0x32568200, 0xbfc00d2c, 0xbfc00d24, 0xbfc00d54) + TEST_BLTZAL(0x54474420, 0xf6749e10, 0x0f558b00, 0x00000000, 0x00000000, 0xbfc00e34, 0xbfc00dfc, 0xbfc00e2c) + TEST_BLTZAL(0xf3595c58, 0x3610309b, 0xb61e33d0, 0x3610309b, 0xb61e33d0, 0xbfc00edc, 0xbfc00ed4, 0xbfc00f04) + TEST_BLTZAL(0xd8dc4820, 0x557637b4, 0x910e3aa0, 0x557637b4, 0x910e3aa0, 0xbfc00fb4, 0xbfc00fac, 0xbfc00fdc) + TEST_BLTZAL(0xaa8a4c98, 0x27e9c330, 0xae081f3e, 0x27e9c330, 0xae081f3e, 0xbfc0108c, 0xbfc01084, 0xbfc010b4) + TEST_BLTZAL(0xd9c4ed40, 0x635ed0a2, 0xdec2e92c, 0x635ed0a2, 0xdec2e92c, 0xbfc01164, 0xbfc0115c, 0xbfc0118c) + TEST_BLTZAL(0x68397fdc, 0xe165e880, 0x45d1fd2c, 0x00000000, 0x00000000, 0xbfc0126c, 0xbfc01234, 0xbfc01264) + TEST_BLTZAL(0x05172a80, 0x741763bc, 0x3ec46470, 0x00000000, 0x00000000, 0xbfc01344, 0xbfc0130c, 0xbfc0133c) + TEST_BLTZAL(0xae593468, 0xf3dacee9, 0x7606d4f0, 0xf3dacee9, 0x7606d4f0, 0xbfc013ec, 0xbfc013e4, 0xbfc01414) + TEST_BLTZAL(0x91d6b8c2, 0x0551f160, 0x4f006da0, 0x0551f160, 0x4f006da0, 0xbfc014c4, 0xbfc014bc, 0xbfc014ec) + TEST_BLTZAL(0xa06b6b90, 0x97ee8758, 0x17d554a0, 0x97ee8758, 0x17d554a0, 0xbfc0159c, 0xbfc01594, 0xbfc015c4) + TEST_BLTZAL(0x7ba59500, 0x5ec946e0, 0x077f958c, 0x00000000, 0x00000000, 0xbfc016a4, 0xbfc0166c, 0xbfc0169c) + TEST_BLTZAL(0xf952c748, 0x3de2fb80, 0xb3da8ec0, 0x3de2fb80, 0xb3da8ec0, 0xbfc0174c, 0xbfc01744, 0xbfc01774) + TEST_BLTZAL(0xd77c3bd3, 0x7e35d110, 0xc636c3b0, 0x7e35d110, 0xc636c3b0, 0xbfc01824, 0xbfc0181c, 0xbfc0184c) + TEST_BLTZAL(0x26dda6d0, 0x237160b4, 0x4daf87f0, 0x00000000, 0x00000000, 0xbfc0192c, 0xbfc018f4, 0xbfc01924) + TEST_BLTZAL(0xd6cca5b0, 0x86f4172c, 0x9d0769e0, 0x86f4172c, 0x9d0769e0, 0xbfc019d4, 0xbfc019cc, 0xbfc019fc) + TEST_BLTZAL(0x28bc23bd, 0x6b42fd00, 0xdd50cbc0, 0x00000000, 0x00000000, 0xbfc01adc, 0xbfc01aa4, 0xbfc01ad4) + TEST_BLTZAL(0xc7851378, 0x9640f3c6, 0xd36f4cb6, 0x9640f3c6, 0xd36f4cb6, 0xbfc01b84, 0xbfc01b7c, 0xbfc01bac) + TEST_BLTZAL(0x4ae00500, 0xcb9870fa, 0x804c8950, 0x00000000, 0x00000000, 0xbfc01c8c, 0xbfc01c54, 0xbfc01c84) + TEST_BLTZAL(0x3534715c, 0xd3300420, 0xa04818a0, 0x00000000, 0x00000000, 0xbfc01d64, 0xbfc01d2c, 0xbfc01d5c) + TEST_BLTZAL(0x07646087, 0x3de9494e, 0xc0a643e6, 0x00000000, 0x00000000, 0xbfc01e3c, 0xbfc01e04, 0xbfc01e34) + TEST_BLTZAL(0x5e14d5ee, 0x08a57680, 0xa6d5d220, 0x00000000, 0x00000000, 0xbfc01f14, 0xbfc01edc, 0xbfc01f0c) + TEST_BLTZAL(0x8306d605, 0xbef43ef0, 0x19bd16ff, 0xbef43ef0, 0x19bd16ff, 0xbfc01fbc, 0xbfc01fb4, 0xbfc01fe4) + TEST_BLTZAL(0x8af84d10, 0xe5f0dae8, 0x1c097320, 0xe5f0dae8, 0x1c097320, 0xbfc02094, 0xbfc0208c, 0xbfc020bc) + TEST_BLTZAL(0xc6e68f76, 0x06c375f8, 0x0c0e1ec5, 0x06c375f8, 0x0c0e1ec5, 0xbfc0216c, 0xbfc02164, 0xbfc02194) + TEST_BLTZAL(0x502badc0, 0x2918933c, 0x370f69c0, 0x00000000, 0x00000000, 0xbfc02274, 0xbfc0223c, 0xbfc0226c) + TEST_BLTZAL(0xe6da4e94, 0xbff11c9d, 0x40ecfeb1, 0xbff11c9d, 0x40ecfeb1, 0xbfc0231c, 0xbfc02314, 0xbfc02344) + TEST_BLTZAL(0x5c91b880, 0x7829cec0, 0xa2999300, 0x00000000, 0x00000000, 0xbfc02424, 0xbfc023ec, 0xbfc0241c) + TEST_BLTZAL(0x82ea2849, 0x7a767238, 0x4e9660c0, 0x7a767238, 0x4e9660c0, 0xbfc024cc, 0xbfc024c4, 0xbfc024f4) + TEST_BLTZAL(0x94870718, 0x5de24514, 0x5d0421b6, 0x5de24514, 0x5d0421b6, 0xbfc025a4, 0xbfc0259c, 0xbfc025cc) + TEST_BLTZAL(0xe224cb20, 0x18f1fa80, 0x150e5c3a, 0x18f1fa80, 0x150e5c3a, 0xbfc0267c, 0xbfc02674, 0xbfc026a4) + TEST_BLTZAL(0x3a14e59e, 0x4ea5a8bc, 0xb5ed7980, 0x00000000, 0x00000000, 0xbfc02784, 0xbfc0274c, 0xbfc0277c) + TEST_BLTZAL(0xdcbd66d6, 0x8673350c, 0xfb5f83b1, 0x8673350c, 0xfb5f83b1, 0xbfc0282c, 0xbfc02824, 0xbfc02854) + TEST_BLTZAL(0x5c84b110, 0x960a74d8, 0xe239d950, 0x00000000, 0x00000000, 0xbfc02934, 0xbfc028fc, 0xbfc0292c) + TEST_BLTZAL(0xfc08307a, 0x25f6aa30, 0x43d5c894, 0x25f6aa30, 0x43d5c894, 0xbfc029dc, 0xbfc029d4, 0xbfc02a04) + TEST_BLTZAL(0x30aee220, 0x8338ae38, 0xf28dd8d0, 0x00000000, 0x00000000, 0xbfc02ae4, 0xbfc02aac, 0xbfc02adc) + TEST_BLTZAL(0x85bd5b3a, 0xa4f7aacf, 0xa39c66c0, 0xa4f7aacf, 0xa39c66c0, 0xbfc02b8c, 0xbfc02b84, 0xbfc02bb4) + TEST_BLTZAL(0xa171fee0, 0x3feda210, 0x77117a8c, 0x3feda210, 0x77117a8c, 0xbfc02c64, 0xbfc02c5c, 0xbfc02c8c) + TEST_BLTZAL(0x79637610, 0xee52c578, 0x24890ec0, 0x00000000, 0x00000000, 0xbfc02d6c, 0xbfc02d34, 0xbfc02d64) + TEST_BLTZAL(0xbfea29c4, 0x846b8bea, 0x0727fb08, 0x846b8bea, 0x0727fb08, 0xbfc02e14, 0xbfc02e0c, 0xbfc02e3c) + TEST_BLTZAL(0x6c103040, 0xb19f9e78, 0xd53b62e4, 0x00000000, 0x00000000, 0xbfc02f1c, 0xbfc02ee4, 0xbfc02f14) + TEST_BLTZAL(0x4fa26e80, 0xc18b61f1, 0xb8d22ab0, 0x00000000, 0x00000000, 0xbfc02ff4, 0xbfc02fbc, 0xbfc02fec) + TEST_BLTZAL(0x08e14a7e, 0xf327c65e, 0xd36cfac0, 0x00000000, 0x00000000, 0xbfc030cc, 0xbfc03094, 0xbfc030c4) + TEST_BLTZAL(0x95644160, 0x08d5b74a, 0xff5d10e4, 0x08d5b74a, 0xff5d10e4, 0xbfc03174, 0xbfc0316c, 0xbfc0319c) + TEST_BLTZAL(0xe11349c8, 0x38d51fd0, 0x47bcd2f0, 0x38d51fd0, 0x47bcd2f0, 0xbfc0324c, 0xbfc03244, 0xbfc03274) + TEST_BLTZAL(0xab05d540, 0x170d0e20, 0x53a1d234, 0x170d0e20, 0x53a1d234, 0xbfc03324, 0xbfc0331c, 0xbfc0334c) + TEST_BLTZAL(0x00827dc8, 0x77030fa0, 0xe0766080, 0x00000000, 0x00000000, 0xbfc0342c, 0xbfc033f4, 0xbfc03424) + TEST_BLTZAL(0x4fb795e8, 0xff1f696e, 0xc65c117e, 0x00000000, 0x00000000, 0xbfc03504, 0xbfc034cc, 0xbfc034fc) + TEST_BLTZAL(0xe26c3dc8, 0x04c5ea92, 0xd4a9b540, 0x04c5ea92, 0xd4a9b540, 0xbfc035ac, 0xbfc035a4, 0xbfc035d4) + TEST_BLTZAL(0x8ffd2b44, 0x656788a8, 0x9f96adc8, 0x656788a8, 0x9f96adc8, 0xbfc03684, 0xbfc0367c, 0xbfc036ac) + TEST_BLTZAL(0xe3481772, 0x9f2a10ee, 0xdd0e6718, 0x9f2a10ee, 0xdd0e6718, 0xbfc0375c, 0xbfc03754, 0xbfc03784) + TEST_BLTZAL(0x7f7db200, 0xd1f8e093, 0x7db9f89c, 0x00000000, 0x00000000, 0xbfc03864, 0xbfc0382c, 0xbfc0385c) + TEST_BLTZAL(0x8e33fd2a, 0x114b1cf8, 0xf1369ae4, 0x114b1cf8, 0xf1369ae4, 0xbfc0390c, 0xbfc03904, 0xbfc03934) + TEST_BLTZAL(0x083ba18a, 0xe036d934, 0x57d80e38, 0x00000000, 0x00000000, 0xbfc03a14, 0xbfc039dc, 0xbfc03a0c) + TEST_BLTZAL(0x138e07f8, 0xb3b0b3c9, 0x5a21b780, 0x00000000, 0x00000000, 0xbfc03aec, 0xbfc03ab4, 0xbfc03ae4) + TEST_BLTZAL(0x244684db, 0x9b439a00, 0x9a8bf098, 0x00000000, 0x00000000, 0xbfc03bc4, 0xbfc03b8c, 0xbfc03bbc) + TEST_BLTZAL(0xa4f9cfdd, 0x364d45c0, 0x41bbe00c, 0x364d45c0, 0x41bbe00c, 0xbfc03c6c, 0xbfc03c64, 0xbfc03c94) + TEST_BLTZAL(0xa31a8b88, 0x80dffe44, 0x2bfa1dd8, 0x80dffe44, 0x2bfa1dd8, 0xbfc03d44, 0xbfc03d3c, 0xbfc03d6c) + TEST_BLTZAL(0x23b524bc, 0xe8347c34, 0x870d1ff4, 0x00000000, 0x00000000, 0xbfc03e4c, 0xbfc03e14, 0xbfc03e44) + TEST_BLTZAL(0xff76fa3d, 0x64c2d25c, 0x3d4fc9c0, 0x64c2d25c, 0x3d4fc9c0, 0xbfc03ef4, 0xbfc03eec, 0xbfc03f1c) + TEST_BLTZAL(0x71e48460, 0xaeb07f00, 0x869f7090, 0x00000000, 0x00000000, 0xbfc03ffc, 0xbfc03fc4, 0xbfc03ff4) + TEST_BLTZAL(0xa249a008, 0x69391de0, 0x7b0199e0, 0x69391de0, 0x7b0199e0, 0xbfc040a4, 0xbfc0409c, 0xbfc040cc) + TEST_BLTZAL(0x12265bf2, 0x68d3270c, 0x6567a780, 0x00000000, 0x00000000, 0xbfc041ac, 0xbfc04174, 0xbfc041a4) + TEST_BLTZAL(0xebc8e65c, 0xae782cc0, 0xcaac1b2c, 0xae782cc0, 0xcaac1b2c, 0xbfc04254, 0xbfc0424c, 0xbfc0427c) + TEST_BLTZAL(0xaaca9c46, 0x86936b00, 0xf3df3180, 0x86936b00, 0xf3df3180, 0xbfc0432c, 0xbfc04324, 0xbfc04354) + TEST_BLTZAL(0x0590d170, 0x260a16a4, 0x2529fc78, 0x00000000, 0x00000000, 0xbfc04434, 0xbfc043fc, 0xbfc0442c) + TEST_BLTZAL(0x2e8b5724, 0xf1306ec4, 0x8e7ae168, 0x00000000, 0x00000000, 0xbfc0450c, 0xbfc044d4, 0xbfc04504) + TEST_BLTZAL(0x1de8443d, 0x1d807f90, 0xc7435a42, 0x00000000, 0x00000000, 0xbfc045e4, 0xbfc045ac, 0xbfc045dc) + TEST_BLTZAL(0xbb81451a, 0x03eb1ab0, 0xb7f4cb55, 0x03eb1ab0, 0xb7f4cb55, 0xbfc0468c, 0xbfc04684, 0xbfc046b4) + TEST_BLTZAL(0xdf5984b1, 0x905956a4, 0x146a6860, 0x905956a4, 0x146a6860, 0xbfc04764, 0xbfc0475c, 0xbfc0478c) + TEST_BLTZAL(0x59146e08, 0x22b11500, 0xfc9d8e9c, 0x00000000, 0x00000000, 0xbfc0486c, 0xbfc04834, 0xbfc04864) + TEST_BLTZAL(0xb2e7acf8, 0xc31eb966, 0x2990605c, 0xc31eb966, 0x2990605c, 0xbfc04914, 0xbfc0490c, 0xbfc0493c) + TEST_BLTZAL(0x4ce3d900, 0x0c50da00, 0xd2352291, 0x00000000, 0x00000000, 0xbfc04a1c, 0xbfc049e4, 0xbfc04a14) + TEST_BLTZAL(0x1b42e17a, 0xc11a1dd4, 0xe80a7020, 0x00000000, 0x00000000, 0xbfc04af4, 0xbfc04abc, 0xbfc04aec) + TEST_BLTZAL(0xa8ea5e19, 0x5101aab0, 0x9d6deeae, 0x5101aab0, 0x9d6deeae, 0xbfc04b9c, 0xbfc04b94, 0xbfc04bc4) + TEST_BLTZAL(0xd7b3d020, 0xf99aa7f0, 0xc18af5b2, 0xf99aa7f0, 0xc18af5b2, 0xbfc04c74, 0xbfc04c6c, 0xbfc04c9c) + TEST_BLTZAL(0x734b6230, 0x6068878c, 0x09fe7964, 0x00000000, 0x00000000, 0xbfc04d7c, 0xbfc04d44, 0xbfc04d74) + TEST_BLTZAL(0x6cd76d80, 0x90d7d0ce, 0xda41d700, 0x00000000, 0x00000000, 0xbfc04e54, 0xbfc04e1c, 0xbfc04e4c) + TEST_BLTZAL(0x68a71f22, 0x62210357, 0xc83f4770, 0x00000000, 0x00000000, 0xbfc04f2c, 0xbfc04ef4, 0xbfc04f24) + TEST_BLTZAL(0xc5586160, 0xefc1c3f4, 0xce234d00, 0xefc1c3f4, 0xce234d00, 0xbfc04fd4, 0xbfc04fcc, 0xbfc04ffc) + TEST_BLTZAL(0x6b831b04, 0x27cfaf60, 0x584df110, 0x00000000, 0x00000000, 0xbfc050dc, 0xbfc050a4, 0xbfc050d4) + TEST_BLTZAL(0x4140cd6e, 0x946f9584, 0x192ecb2a, 0x00000000, 0x00000000, 0xbfc051b4, 0xbfc0517c, 0xbfc051ac) + TEST_BLTZAL(0x5761276c, 0xb7c925c0, 0x655060ba, 0x00000000, 0x00000000, 0xbfc0528c, 0xbfc05254, 0xbfc05284) + TEST_BLTZAL(0x595c9842, 0x3d38d68e, 0x3e17fa50, 0x00000000, 0x00000000, 0xbfc05364, 0xbfc0532c, 0xbfc0535c) + TEST_BLTZAL(0x4ab5152d, 0x649e1726, 0xf3523180, 0x00000000, 0x00000000, 0xbfc0543c, 0xbfc05404, 0xbfc05434) + TEST_BLTZAL(0x92e90da4, 0x34e6f946, 0x82cb1092, 0x34e6f946, 0x82cb1092, 0xbfc054e4, 0xbfc054dc, 0xbfc0550c) + TEST_BLTZAL(0xbba9590a, 0x48f10aa2, 0x0a4be0a8, 0x48f10aa2, 0x0a4be0a8, 0xbfc055bc, 0xbfc055b4, 0xbfc055e4) + TEST_BLTZAL(0x99f0dc78, 0xcca74d4a, 0x9fb73588, 0xcca74d4a, 0x9fb73588, 0xbfc05694, 0xbfc0568c, 0xbfc056bc) + TEST_BLTZAL(0xb08a88a0, 0xd718c9e6, 0x9a1aaa50, 0xd718c9e6, 0x9a1aaa50, 0xbfc0576c, 0xbfc05764, 0xbfc05794) + TEST_BLTZAL(0x5f2c6063, 0x48162660, 0x1af590b0, 0x00000000, 0x00000000, 0xbfc05874, 0xbfc0583c, 0xbfc0586c) + TEST_BLTZAL(0x40113b20, 0x49cdaad7, 0x225d54dc, 0x00000000, 0x00000000, 0xbfc0594c, 0xbfc05914, 0xbfc05944) + TEST_BLTZAL(0x5e7f637c, 0x331c8554, 0x60cb46c0, 0x00000000, 0x00000000, 0xbfc05a24, 0xbfc059ec, 0xbfc05a1c) + TEST_BLTZAL(0x028a5cdc, 0xca727700, 0xd1acb3d8, 0x00000000, 0x00000000, 0xbfc05afc, 0xbfc05ac4, 0xbfc05af4) + TEST_BLTZAL(0xf4158168, 0x5b36fb58, 0xdac1338c, 0x5b36fb58, 0xdac1338c, 0xbfc05ba4, 0xbfc05b9c, 0xbfc05bcc) + TEST_BLTZAL(0xaede9100, 0x9aefd3e0, 0xeb172cbe, 0x9aefd3e0, 0xeb172cbe, 0xbfc05c7c, 0xbfc05c74, 0xbfc05ca4) + TEST_BLTZAL(0x7d933080, 0xa7436d60, 0x2f1814c4, 0x00000000, 0x00000000, 0xbfc05d84, 0xbfc05d4c, 0xbfc05d7c) + TEST_BLTZAL(0x1ca8c258, 0x50c557cc, 0xa722bd38, 0x00000000, 0x00000000, 0xbfc05e5c, 0xbfc05e24, 0xbfc05e54) + TEST_BLTZAL(0x466b58c0, 0x832cfa20, 0x8175f686, 0x00000000, 0x00000000, 0xbfc05f34, 0xbfc05efc, 0xbfc05f2c) + TEST_BLTZAL(0x22b2b3b4, 0xe9cb6c40, 0x53edd6b4, 0x00000000, 0x00000000, 0xbfc0600c, 0xbfc05fd4, 0xbfc06004) + TEST_BLTZAL(0x5b78e940, 0x8dcec176, 0xb8726e32, 0x00000000, 0x00000000, 0xbfc060e4, 0xbfc060ac, 0xbfc060dc) + TEST_BLTZAL(0x2f5f8070, 0x58205fc0, 0xe57e23ad, 0x00000000, 0x00000000, 0xbfc061bc, 0xbfc06184, 0xbfc061b4) + TEST_BLTZAL(0xda7308f4, 0x9b86c9b8, 0x913775a0, 0x9b86c9b8, 0x913775a0, 0xbfc06264, 0xbfc0625c, 0xbfc0628c) + TEST_BLTZAL(0xe9c9da6a, 0xc2339e20, 0xa4268ba0, 0xc2339e20, 0xa4268ba0, 0xbfc0633c, 0xbfc06334, 0xbfc06364) + TEST_BLTZAL(0xab39c2d2, 0xa3d5a878, 0x1727c53b, 0xa3d5a878, 0x1727c53b, 0xbfc06414, 0xbfc0640c, 0xbfc0643c) + TEST_BLTZAL(0xbe97cbea, 0xd1834712, 0x81b9b444, 0xd1834712, 0x81b9b444, 0xbfc064ec, 0xbfc064e4, 0xbfc06514) + TEST_BLTZAL(0xccbb6fe8, 0x58edca80, 0xe32f1c00, 0x58edca80, 0xe32f1c00, 0xbfc065c4, 0xbfc065bc, 0xbfc065ec) + TEST_BLTZAL(0xca8292c0, 0x05b81cc8, 0x5dc2535b, 0x05b81cc8, 0x5dc2535b, 0xbfc0669c, 0xbfc06694, 0xbfc066c4) + TEST_BLTZAL(0x87216bb1, 0x5745c9ac, 0x559f39ac, 0x5745c9ac, 0x559f39ac, 0xbfc06774, 0xbfc0676c, 0xbfc0679c) + TEST_BLTZAL(0xc4660448, 0xbd2e3330, 0x48eeaa30, 0xbd2e3330, 0x48eeaa30, 0xbfc0684c, 0xbfc06844, 0xbfc06874) + TEST_BLTZAL(0x443ff57c, 0x6c6efe6f, 0x878908f7, 0x00000000, 0x00000000, 0xbfc06954, 0xbfc0691c, 0xbfc0694c) + TEST_BLTZAL(0x7d6ee738, 0xe0611dfc, 0x9f031122, 0x00000000, 0x00000000, 0xbfc06a2c, 0xbfc069f4, 0xbfc06a24) + TEST_BLTZAL(0xd3d10d4d, 0x7d247ed0, 0xf5722c22, 0x7d247ed0, 0xf5722c22, 0xbfc06ad4, 0xbfc06acc, 0xbfc06afc) + TEST_BLTZAL(0x1f949120, 0x820b11fe, 0xdc05404a, 0x00000000, 0x00000000, 0xbfc06bdc, 0xbfc06ba4, 0xbfc06bd4) + TEST_BLTZAL(0xc68f0040, 0x77c6a186, 0x9f2c9ee6, 0x77c6a186, 0x9f2c9ee6, 0xbfc06c84, 0xbfc06c7c, 0xbfc06cac) + TEST_BLTZAL(0xc7312578, 0x3be03aec, 0xc0fee200, 0x3be03aec, 0xc0fee200, 0xbfc06d5c, 0xbfc06d54, 0xbfc06d84) + TEST_BLTZAL(0x309ac032, 0xaadf3100, 0x497ec7b0, 0x00000000, 0x00000000, 0xbfc06e64, 0xbfc06e2c, 0xbfc06e5c) + TEST_BLTZAL(0x5cb29501, 0xd6019ed2, 0x4808d27a, 0x00000000, 0x00000000, 0xbfc06f3c, 0xbfc06f04, 0xbfc06f34) + TEST_BLTZAL(0x24c24528, 0x23081e7c, 0x23a423a5, 0x00000000, 0x00000000, 0xbfc07014, 0xbfc06fdc, 0xbfc0700c) + TEST_BLTZAL(0x2092e460, 0xea8c1a16, 0x7fb0dc44, 0x00000000, 0x00000000, 0xbfc070ec, 0xbfc070b4, 0xbfc070e4) + TEST_BLTZAL(0xf724628b, 0x24cd6a00, 0x06d5bbd0, 0x24cd6a00, 0x06d5bbd0, 0xbfc07194, 0xbfc0718c, 0xbfc071bc) + TEST_BLTZAL(0x33bf4222, 0xb8acf8f9, 0xdafc8a00, 0x00000000, 0x00000000, 0xbfc0729c, 0xbfc07264, 0xbfc07294) + TEST_BLTZAL(0x9e234e33, 0x7172c748, 0x61ac8e1e, 0x7172c748, 0x61ac8e1e, 0xbfc07344, 0xbfc0733c, 0xbfc0736c) + TEST_BLTZAL(0xf9756dbc, 0x021822c8, 0xa5ed4b94, 0x021822c8, 0xa5ed4b94, 0xbfc0741c, 0xbfc07414, 0xbfc07444) + TEST_BLTZAL(0x60880d60, 0xd8442aaf, 0xaac6de74, 0x00000000, 0x00000000, 0xbfc07524, 0xbfc074ec, 0xbfc0751c) + TEST_BLTZAL(0x62fc9300, 0x36454702, 0xd297fe88, 0x00000000, 0x00000000, 0xbfc075fc, 0xbfc075c4, 0xbfc075f4) + TEST_BLTZAL(0x12cdb320, 0x13bf17a2, 0x6a1085c6, 0x00000000, 0x00000000, 0xbfc076d4, 0xbfc0769c, 0xbfc076cc) + TEST_BLTZAL(0x33699318, 0xeb2f7fcc, 0xdcfbd7b6, 0x00000000, 0x00000000, 0xbfc077ac, 0xbfc07774, 0xbfc077a4) + TEST_BLTZAL(0x1beacb00, 0xe333f8e8, 0xd492d830, 0x00000000, 0x00000000, 0xbfc07884, 0xbfc0784c, 0xbfc0787c) + TEST_BLTZAL(0xf3abd08a, 0xc25e31c0, 0xf178fcc7, 0xc25e31c0, 0xf178fcc7, 0xbfc0792c, 0xbfc07924, 0xbfc07954) + TEST_BLTZAL(0xbbb85c80, 0x747014c0, 0xa2f6fdf0, 0x747014c0, 0xa2f6fdf0, 0xbfc07a04, 0xbfc079fc, 0xbfc07a2c) + TEST_BLTZAL(0x3a43003a, 0xeeed819a, 0xb2fad2e0, 0x00000000, 0x00000000, 0xbfc07b0c, 0xbfc07ad4, 0xbfc07b04) + TEST_BLTZAL(0x5037f2c4, 0xdc5b45a0, 0x2ec3ec30, 0x00000000, 0x00000000, 0xbfc07be4, 0xbfc07bac, 0xbfc07bdc) + TEST_BLTZAL(0xa8456f6e, 0xaff24380, 0x319e3974, 0xaff24380, 0x319e3974, 0xbfc07c8c, 0xbfc07c84, 0xbfc07cb4) + TEST_BLTZAL(0x414853a0, 0x637439d2, 0x6693d9c0, 0x00000000, 0x00000000, 0xbfc07d94, 0xbfc07d5c, 0xbfc07d8c) + TEST_BLTZAL(0xe7456b0a, 0x51b4161c, 0xfeaa18a0, 0x51b4161c, 0xfeaa18a0, 0xbfc07e3c, 0xbfc07e34, 0xbfc07e64) + TEST_BLTZAL(0xbb74e538, 0x6ed74130, 0x984f6072, 0x6ed74130, 0x984f6072, 0xbfc07f14, 0xbfc07f0c, 0xbfc07f3c) + TEST_BLTZAL(0x22d313b0, 0xa42543e0, 0x4e7cf014, 0x00000000, 0x00000000, 0xbfc0801c, 0xbfc07fe4, 0xbfc08014) + TEST_BLTZAL(0x5879a989, 0x80ef8300, 0x3576293c, 0x00000000, 0x00000000, 0xbfc080f4, 0xbfc080bc, 0xbfc080ec) + TEST_BLTZAL(0x6dd7a283, 0x67f82b20, 0x3eeddf3c, 0x00000000, 0x00000000, 0xbfc081cc, 0xbfc08194, 0xbfc081c4) + TEST_BLTZAL(0x8c3e6232, 0x6b6cd290, 0x360783ea, 0x6b6cd290, 0x360783ea, 0xbfc08274, 0xbfc0826c, 0xbfc0829c) + TEST_BLTZAL(0x9935c478, 0xcaaa3fe0, 0xbfbf76f0, 0xcaaa3fe0, 0xbfbf76f0, 0xbfc0834c, 0xbfc08344, 0xbfc08374) + TEST_BLTZAL(0xaa40e800, 0xd0658f18, 0x27947ea4, 0xd0658f18, 0x27947ea4, 0xbfc08424, 0xbfc0841c, 0xbfc0844c) + TEST_BLTZAL(0x95c54b0e, 0x2c0a79d8, 0xba269468, 0x2c0a79d8, 0xba269468, 0xbfc084fc, 0xbfc084f4, 0xbfc08524) + TEST_BLTZAL(0x0c643508, 0xb70c9fb0, 0xfc6798bc, 0x00000000, 0x00000000, 0xbfc08604, 0xbfc085cc, 0xbfc085fc) + TEST_BLTZAL(0x7c26fe64, 0x1bde5440, 0x0a02d616, 0x00000000, 0x00000000, 0xbfc086dc, 0xbfc086a4, 0xbfc086d4) + TEST_BLTZAL(0xfd4d12cc, 0x375d3388, 0x931732c2, 0x375d3388, 0x931732c2, 0xbfc08784, 0xbfc0877c, 0xbfc087ac) + TEST_BLTZAL(0x3bb516cb, 0x9a02b930, 0xbca4f17c, 0x00000000, 0x00000000, 0xbfc0888c, 0xbfc08854, 0xbfc08884) + TEST_BLTZAL(0x72a53c58, 0xdc2567e4, 0x70280859, 0x00000000, 0x00000000, 0xbfc08964, 0xbfc0892c, 0xbfc0895c) + TEST_BLTZAL(0x99119a2e, 0x184ac668, 0x2127b7d2, 0x184ac668, 0x2127b7d2, 0xbfc08a0c, 0xbfc08a04, 0xbfc08a34) + TEST_BLTZAL(0xb446190a, 0x7d1f992e, 0x3cde2960, 0x7d1f992e, 0x3cde2960, 0xbfc08ae4, 0xbfc08adc, 0xbfc08b0c) + TEST_BLTZAL(0x1b8f96bc, 0xf3cdf593, 0x97e1fbbc, 0x00000000, 0x00000000, 0xbfc08bec, 0xbfc08bb4, 0xbfc08be4) + TEST_BLTZAL(0x789194bf, 0xdcdbab7f, 0x1e341cf8, 0x00000000, 0x00000000, 0xbfc08cc4, 0xbfc08c8c, 0xbfc08cbc) + TEST_BLTZAL(0x23698dbe, 0x9962e5f0, 0xad6ccba6, 0x00000000, 0x00000000, 0xbfc08d9c, 0xbfc08d64, 0xbfc08d94) + TEST_BLTZAL(0x7b96aa28, 0xb96f903d, 0x85e76370, 0x00000000, 0x00000000, 0xbfc08e74, 0xbfc08e3c, 0xbfc08e6c) + TEST_BLTZAL(0x6a9ae400, 0x5257a372, 0x865c7e28, 0x00000000, 0x00000000, 0xbfc08f4c, 0xbfc08f14, 0xbfc08f44) + TEST_BLTZAL(0x63c50b28, 0x061e6658, 0x322ff830, 0x00000000, 0x00000000, 0xbfc09024, 0xbfc08fec, 0xbfc0901c) + TEST_BLTZAL(0x46e906bc, 0xc06953e0, 0xa92e9bbc, 0x00000000, 0x00000000, 0xbfc090fc, 0xbfc090c4, 0xbfc090f4) + TEST_BLTZAL(0x3bc5a0e0, 0x563a0440, 0x0817b7a8, 0x00000000, 0x00000000, 0xbfc091d4, 0xbfc0919c, 0xbfc091cc) + TEST_BLTZAL(0x92c167f8, 0xe27e6888, 0x4e28c838, 0xe27e6888, 0x4e28c838, 0xbfc0927c, 0xbfc09274, 0xbfc092a4) + TEST_BLTZAL(0x3ee483a8, 0x3e09bb40, 0x65b17d20, 0x00000000, 0x00000000, 0xbfc09384, 0xbfc0934c, 0xbfc0937c) + TEST_BLTZAL(0x4eaa5a80, 0x6edf66a4, 0x27264b04, 0x00000000, 0x00000000, 0xbfc0945c, 0xbfc09424, 0xbfc09454) + TEST_BLTZAL(0xc25a94c0, 0x16648180, 0xceff49a0, 0x16648180, 0xceff49a0, 0xbfc09504, 0xbfc094fc, 0xbfc0952c) + TEST_BLTZAL(0x178e29a0, 0xa5b5a538, 0xc4440224, 0x00000000, 0x00000000, 0xbfc0960c, 0xbfc095d4, 0xbfc09604) + TEST_BLTZAL(0x1946faac, 0xaa83b7aa, 0xc9244bf5, 0x00000000, 0x00000000, 0xbfc096e4, 0xbfc096ac, 0xbfc096dc) + TEST_BLTZAL(0x8a6e27ba, 0x5479233d, 0x0fe51340, 0x5479233d, 0x0fe51340, 0xbfc0978c, 0xbfc09784, 0xbfc097b4) + TEST_BLTZAL(0xc1a17acc, 0x4081010d, 0xff791604, 0x4081010d, 0xff791604, 0xbfc09864, 0xbfc0985c, 0xbfc0988c) + TEST_BLTZAL(0x45e5dec0, 0xd701b72c, 0x5888fdd8, 0x00000000, 0x00000000, 0xbfc0996c, 0xbfc09934, 0xbfc09964) + TEST_BLTZAL(0x93326582, 0xf1f955c0, 0xcf5e55ca, 0xf1f955c0, 0xcf5e55ca, 0xbfc09a14, 0xbfc09a0c, 0xbfc09a3c) + TEST_BLTZAL(0x00928868, 0x090455b2, 0xf5c1b600, 0x00000000, 0x00000000, 0xbfc09b1c, 0xbfc09ae4, 0xbfc09b14) + TEST_BLTZAL(0xf7ccd1e8, 0x16332a88, 0x54968884, 0x16332a88, 0x54968884, 0xbfc09bc4, 0xbfc09bbc, 0xbfc09bec) + TEST_BLTZAL(0x6ec43ef0, 0xfb8f16d5, 0x09b69d60, 0x00000000, 0x00000000, 0xbfc09ccc, 0xbfc09c94, 0xbfc09cc4) + TEST_BLTZAL(0x16c9ba2e, 0x37daacd7, 0x7986d400, 0x00000000, 0x00000000, 0xbfc09da4, 0xbfc09d6c, 0xbfc09d9c) + TEST_BLTZAL(0xbae401b8, 0xe096eec2, 0x15e2e1e0, 0xe096eec2, 0x15e2e1e0, 0xbfc09e4c, 0xbfc09e44, 0xbfc09e74) + TEST_BLTZAL(0x7a4a5eb6, 0x1fd9b7a8, 0x7f6b7a00, 0x00000000, 0x00000000, 0xbfc09f54, 0xbfc09f1c, 0xbfc09f4c) + TEST_BLTZAL(0x59b20d00, 0xdc65605e, 0xddb8579c, 0x00000000, 0x00000000, 0xbfc0a02c, 0xbfc09ff4, 0xbfc0a024) + TEST_BLTZAL(0x48e7307c, 0xde52b38f, 0x14848570, 0x00000000, 0x00000000, 0xbfc0a104, 0xbfc0a0cc, 0xbfc0a0fc) + TEST_BLTZAL(0x2fe03e13, 0xb9eb186e, 0x403ccc04, 0x00000000, 0x00000000, 0xbfc0a1dc, 0xbfc0a1a4, 0xbfc0a1d4) + TEST_BLTZAL(0x50d83460, 0x5b458d34, 0xb3e5b6c0, 0x00000000, 0x00000000, 0xbfc0a2b4, 0xbfc0a27c, 0xbfc0a2ac) + TEST_BLTZAL(0x42e7c900, 0xe3efdfde, 0x0d3d9b80, 0x00000000, 0x00000000, 0xbfc0a38c, 0xbfc0a354, 0xbfc0a384) + TEST_BLTZAL(0xf8841282, 0x729968e0, 0x16e13cca, 0x729968e0, 0x16e13cca, 0xbfc0a434, 0xbfc0a42c, 0xbfc0a45c) + TEST_BLTZAL(0xa98425f8, 0xbc443ce7, 0xae756fac, 0xbc443ce7, 0xae756fac, 0xbfc0a50c, 0xbfc0a504, 0xbfc0a534) + TEST_BLTZAL(0x6c1f0d47, 0x1afdcbfa, 0x9ccde33e, 0x00000000, 0x00000000, 0xbfc0a614, 0xbfc0a5dc, 0xbfc0a60c) + TEST_BLTZAL(0xfcf950ca, 0x8954be60, 0x82ec2818, 0x8954be60, 0x82ec2818, 0xbfc0a6bc, 0xbfc0a6b4, 0xbfc0a6e4) + TEST_BLTZAL(0x74f524b2, 0xb1151634, 0xa1cb0328, 0x00000000, 0x00000000, 0xbfc0a7c4, 0xbfc0a78c, 0xbfc0a7bc) + TEST_BLTZAL(0xc9bca1a8, 0x2a1a3688, 0xea2bb980, 0x2a1a3688, 0xea2bb980, 0xbfc0a86c, 0xbfc0a864, 0xbfc0a894) + TEST_BLTZAL(0x4f8b1162, 0x560409a8, 0x5df83060, 0x00000000, 0x00000000, 0xbfc0a974, 0xbfc0a93c, 0xbfc0a96c) + TEST_BLTZAL(0x00dba000, 0xff655f88, 0xe7eb1ef4, 0x00000000, 0x00000000, 0xbfc0aa4c, 0xbfc0aa14, 0xbfc0aa44) + TEST_BLTZAL(0xa199561e, 0x92b64a0c, 0xe8669a08, 0x92b64a0c, 0xe8669a08, 0xbfc0aaf4, 0xbfc0aaec, 0xbfc0ab1c) + TEST_BLTZAL(0x73ee8202, 0xd7a56490, 0x79518f38, 0x00000000, 0x00000000, 0xbfc0abfc, 0xbfc0abc4, 0xbfc0abf4) + TEST_BLTZAL(0x00000000, 0xafbac4d4, 0xf06fb6ae, 0x00000000, 0x00000000, 0xbfc0acd0, 0xbfc0ac9c, 0xbfc0acc8) HIT_GOOD_TRAP inst_error: diff --git a/TEMU/mips_sc/src/inst/jal.S b/TEMU/mips_sc/src/inst/jal.S index 4bfe359..10ff081 100644 --- a/TEMU/mips_sc/src/inst/jal.S +++ b/TEMU/mips_sc/src/inst/jal.S @@ -10,207 +10,12 @@ main: ###test inst - TEST_JAL(0x8c3e1efa, 0xeb2bd57c, 0x8c3e1efa, 0xeb2bd57c) - TEST_JAL(0xfbc1f5d0, 0xb91bc0b0, 0xfbc1f5d0, 0xb91bc0b0) - TEST_JAL(0xc1062356, 0xf8d60c60, 0xc1062356, 0xf8d60c60) - TEST_JAL(0x0b2dc8e4, 0xff276d2f, 0x0b2dc8e4, 0xff276d2f) - TEST_JAL(0x312fabd9, 0x970387ac, 0x312fabd9, 0x970387ac) - TEST_JAL(0x46360a68, 0xf903f5cd, 0x46360a68, 0xf903f5cd) - TEST_JAL(0x41cc660a, 0x52295cdc, 0x41cc660a, 0x52295cdc) - TEST_JAL(0x48fa3a04, 0x69636126, 0x48fa3a04, 0x69636126) - TEST_JAL(0xbcd7cfec, 0x779a95ec, 0xbcd7cfec, 0x779a95ec) - TEST_JAL(0x5fc96388, 0xc43c4580, 0x5fc96388, 0xc43c4580) - TEST_JAL(0x2e6acb2a, 0x3ff930e4, 0x2e6acb2a, 0x3ff930e4) - TEST_JAL(0x570165c0, 0x984bd878, 0x570165c0, 0x984bd878) - TEST_JAL(0x881d5800, 0x034e6000, 0x881d5800, 0x034e6000) - TEST_JAL(0x8a5b3be0, 0xb94b6376, 0x8a5b3be0, 0xb94b6376) - TEST_JAL(0x8b75ce52, 0x13b7a780, 0x8b75ce52, 0x13b7a780) - TEST_JAL(0xfcdb1218, 0xff483538, 0xfcdb1218, 0xff483538) - TEST_JAL(0x2e450deb, 0x10609f0c, 0x2e450deb, 0x10609f0c) - TEST_JAL(0x3e80cb3e, 0xc960e400, 0x3e80cb3e, 0xc960e400) - TEST_JAL(0x44af9ce0, 0x800d3820, 0x44af9ce0, 0x800d3820) - TEST_JAL(0x08eec534, 0xb7735884, 0x08eec534, 0xb7735884) - TEST_JAL(0xbc5a66a4, 0xdf144ab4, 0xbc5a66a4, 0xdf144ab4) - TEST_JAL(0x2aeb3f3c, 0xedcc9ce0, 0x2aeb3f3c, 0xedcc9ce0) - TEST_JAL(0xcd784df5, 0xaff92f84, 0xcd784df5, 0xaff92f84) - TEST_JAL(0xa34d260a, 0xb77c87f4, 0xa34d260a, 0xb77c87f4) - TEST_JAL(0xa0d86880, 0xafeba4e4, 0xa0d86880, 0xafeba4e4) - TEST_JAL(0xf7b8f37b, 0x911de040, 0xf7b8f37b, 0x911de040) - TEST_JAL(0x7c777a50, 0xe14e1a90, 0x7c777a50, 0xe14e1a90) - TEST_JAL(0x7b1a2aa1, 0x944c4918, 0x7b1a2aa1, 0x944c4918) - TEST_JAL(0x7e86eb59, 0xb5428b4c, 0x7e86eb59, 0xb5428b4c) - TEST_JAL(0x7bf88eb0, 0x7730b200, 0x7bf88eb0, 0x7730b200) - TEST_JAL(0x68e11960, 0x8bb65900, 0x68e11960, 0x8bb65900) - TEST_JAL(0x761df4e4, 0xa9cb4b94, 0x761df4e4, 0xa9cb4b94) - TEST_JAL(0xcf09190a, 0x38d5a080, 0xcf09190a, 0x38d5a080) - TEST_JAL(0xe30a8d18, 0xc20c3730, 0xe30a8d18, 0xc20c3730) - TEST_JAL(0xed6878d8, 0xf351a7d0, 0xed6878d8, 0xf351a7d0) - TEST_JAL(0x2ce27912, 0xe112dcc0, 0x2ce27912, 0xe112dcc0) - TEST_JAL(0xcf2e7144, 0x35530400, 0xcf2e7144, 0x35530400) - TEST_JAL(0xc7819b20, 0x8274cb2e, 0xc7819b20, 0x8274cb2e) - TEST_JAL(0xc1799706, 0x493e5d5c, 0xc1799706, 0x493e5d5c) - TEST_JAL(0xd28b3668, 0xdb280f90, 0xd28b3668, 0xdb280f90) - TEST_JAL(0x026aa762, 0x3e6cae50, 0x026aa762, 0x3e6cae50) - TEST_JAL(0x66ef8290, 0x649f12da, 0x66ef8290, 0x649f12da) - TEST_JAL(0x62b6f780, 0x3a972800, 0x62b6f780, 0x3a972800) - TEST_JAL(0xc820cfb0, 0xfb4f92d6, 0xc820cfb0, 0xfb4f92d6) - TEST_JAL(0xafb11450, 0x6f3f4ac4, 0xafb11450, 0x6f3f4ac4) - TEST_JAL(0x4f07fcf0, 0xc90ed8f2, 0x4f07fcf0, 0xc90ed8f2) - TEST_JAL(0x348bcc32, 0xaf14d88e, 0x348bcc32, 0xaf14d88e) - TEST_JAL(0xac0d1b82, 0x859c9fa0, 0xac0d1b82, 0x859c9fa0) - TEST_JAL(0x2967a800, 0x9be679e0, 0x2967a800, 0x9be679e0) - TEST_JAL(0x54682b9b, 0xf6afc130, 0x54682b9b, 0xf6afc130) - TEST_JAL(0x546c98f0, 0x54bb0a06, 0x546c98f0, 0x54bb0a06) - TEST_JAL(0x0b51bf3f, 0x31c22efc, 0x0b51bf3f, 0x31c22efc) - TEST_JAL(0x04ad485a, 0x39e85f59, 0x04ad485a, 0x39e85f59) - TEST_JAL(0xe7e576d8, 0x68ca0df9, 0xe7e576d8, 0x68ca0df9) - TEST_JAL(0xba12c92e, 0x85577d42, 0xba12c92e, 0x85577d42) - TEST_JAL(0x403b4458, 0x6becb754, 0x403b4458, 0x6becb754) - TEST_JAL(0x8f6d6b48, 0xe1563e28, 0x8f6d6b48, 0xe1563e28) - TEST_JAL(0xb41d3203, 0x96329e80, 0xb41d3203, 0x96329e80) - TEST_JAL(0xe6aec8cb, 0x27ef5f5b, 0xe6aec8cb, 0x27ef5f5b) - TEST_JAL(0x5eedde10, 0x94eb3844, 0x5eedde10, 0x94eb3844) - TEST_JAL(0x83b08836, 0x22173eb0, 0x83b08836, 0x22173eb0) - TEST_JAL(0x59931aae, 0xdbc9d400, 0x59931aae, 0xdbc9d400) - TEST_JAL(0x062253c0, 0x2628a368, 0x062253c0, 0x2628a368) - TEST_JAL(0xb4f84c50, 0xd5d39399, 0xb4f84c50, 0xd5d39399) - TEST_JAL(0xeb44ae38, 0xdc7d3918, 0xeb44ae38, 0xdc7d3918) - TEST_JAL(0x53335424, 0x9eeec7c0, 0x53335424, 0x9eeec7c0) - TEST_JAL(0x0cb4fb1c, 0x5d38a700, 0x0cb4fb1c, 0x5d38a700) - TEST_JAL(0x94074b4a, 0x19de1db2, 0x94074b4a, 0x19de1db2) - TEST_JAL(0x47bfb4b8, 0x48c0ff80, 0x47bfb4b8, 0x48c0ff80) - TEST_JAL(0x6f543ca0, 0xa3afbfd0, 0x6f543ca0, 0xa3afbfd0) - TEST_JAL(0xe415ada8, 0xbf884e60, 0xe415ada8, 0xbf884e60) - TEST_JAL(0x0b96ab22, 0xc0d6f7c4, 0x0b96ab22, 0xc0d6f7c4) - TEST_JAL(0x5ae28f04, 0xf13ea9c0, 0x5ae28f04, 0xf13ea9c0) - TEST_JAL(0x2a34a7e4, 0xcbaf7220, 0x2a34a7e4, 0xcbaf7220) - TEST_JAL(0xd0ad4298, 0xf331669e, 0xd0ad4298, 0xf331669e) - TEST_JAL(0xa0666600, 0xd2dbb338, 0xa0666600, 0xd2dbb338) - TEST_JAL(0x78bc78cc, 0x5b6016a0, 0x78bc78cc, 0x5b6016a0) - TEST_JAL(0xe7050f78, 0x39d5936c, 0xe7050f78, 0x39d5936c) - TEST_JAL(0x19918b5e, 0x4434cce4, 0x19918b5e, 0x4434cce4) - TEST_JAL(0xfb6658fc, 0x55f6c180, 0xfb6658fc, 0x55f6c180) - TEST_JAL(0x5c597442, 0x97069b95, 0x5c597442, 0x97069b95) - TEST_JAL(0x40641bb4, 0xa4a7e410, 0x40641bb4, 0xa4a7e410) - TEST_JAL(0xa6f177e0, 0x6297679f, 0xa6f177e0, 0x6297679f) - TEST_JAL(0xde4805a8, 0x831d0fe8, 0xde4805a8, 0x831d0fe8) - TEST_JAL(0xd71129d0, 0x07e1fff8, 0xd71129d0, 0x07e1fff8) - TEST_JAL(0xa57eea80, 0xead68300, 0xa57eea80, 0xead68300) - TEST_JAL(0x8c126738, 0x729c97f4, 0x8c126738, 0x729c97f4) - TEST_JAL(0xc2f019bc, 0xa123d420, 0xc2f019bc, 0xa123d420) - TEST_JAL(0x4e60cfa6, 0xdf8b1860, 0x4e60cfa6, 0xdf8b1860) - TEST_JAL(0x88977aa0, 0xdd38d0b8, 0x88977aa0, 0xdd38d0b8) - TEST_JAL(0x8273a980, 0x15daba38, 0x8273a980, 0x15daba38) - TEST_JAL(0x2e33290a, 0xd9346c82, 0x2e33290a, 0xd9346c82) - TEST_JAL(0x864e94e4, 0xa20d82e4, 0x864e94e4, 0xa20d82e4) - TEST_JAL(0x63677728, 0x3d83ac49, 0x63677728, 0x3d83ac49) - TEST_JAL(0xdc9e95bc, 0x80890af0, 0xdc9e95bc, 0x80890af0) - TEST_JAL(0x62987b70, 0xb80855ae, 0x62987b70, 0xb80855ae) - TEST_JAL(0xb5b70534, 0x6507ff98, 0xb5b70534, 0x6507ff98) - TEST_JAL(0xac72d980, 0xbf989ac0, 0xac72d980, 0xbf989ac0) - TEST_JAL(0xf330e230, 0x3e8946c8, 0xf330e230, 0x3e8946c8) - TEST_JAL(0xa6d166cc, 0xe1821d9f, 0xa6d166cc, 0xe1821d9f) - TEST_JAL(0xf2a1547c, 0x27507968, 0xf2a1547c, 0x27507968) - TEST_JAL(0x22da9500, 0x3567c320, 0x22da9500, 0x3567c320) - TEST_JAL(0x456843ac, 0x9078aa46, 0x456843ac, 0x9078aa46) - TEST_JAL(0xf6374800, 0xfec9001c, 0xf6374800, 0xfec9001c) - TEST_JAL(0x7772970e, 0x5c93caaf, 0x7772970e, 0x5c93caaf) - TEST_JAL(0xd0deecae, 0x9242f92c, 0xd0deecae, 0x9242f92c) - TEST_JAL(0xf706e3d4, 0xd80065c8, 0xf706e3d4, 0xd80065c8) - TEST_JAL(0x88ed1d00, 0x01132628, 0x88ed1d00, 0x01132628) - TEST_JAL(0xf1d6dafe, 0xf8edf824, 0xf1d6dafe, 0xf8edf824) - TEST_JAL(0x65394174, 0xcc264320, 0x65394174, 0xcc264320) - TEST_JAL(0x7f95e490, 0xb64262d0, 0x7f95e490, 0xb64262d0) - TEST_JAL(0xe67c8576, 0x14fc505c, 0xe67c8576, 0x14fc505c) - TEST_JAL(0x54be7440, 0xf66c762e, 0x54be7440, 0xf66c762e) + TEST_JAL(0xd7a7e4e6, 0xcab5f8fb, 0xd7a7e4e6, 0xcab5f8fb) TEST_JAL(0x626c7a3b, 0xc2279a00, 0x626c7a3b, 0xc2279a00) - TEST_JAL(0xd058ca5d, 0x87033d19, 0xd058ca5d, 0x87033d19) - TEST_JAL(0x4883255a, 0x527231d0, 0x4883255a, 0x527231d0) - TEST_JAL(0x482d4ba0, 0x166fe362, 0x482d4ba0, 0x166fe362) - TEST_JAL(0xaa8af5cc, 0x12fdc654, 0xaa8af5cc, 0x12fdc654) - TEST_JAL(0x60c6b2c4, 0x6d83e80a, 0x60c6b2c4, 0x6d83e80a) - TEST_JAL(0x86479cb8, 0xb78fb7a2, 0x86479cb8, 0xb78fb7a2) - TEST_JAL(0xab6b767c, 0x3de37136, 0xab6b767c, 0x3de37136) - TEST_JAL(0x4f2c6700, 0x5c6e1608, 0x4f2c6700, 0x5c6e1608) - TEST_JAL(0x837221e0, 0xf67a1882, 0x837221e0, 0xf67a1882) - TEST_JAL(0xe8609af3, 0xe8c6d23c, 0xe8609af3, 0xe8c6d23c) - TEST_JAL(0x397df8e2, 0xdad4d9c8, 0x397df8e2, 0xdad4d9c8) - TEST_JAL(0x50a379d0, 0xcebec140, 0x50a379d0, 0xcebec140) - TEST_JAL(0x3af9c4d7, 0x9d770cfe, 0x3af9c4d7, 0x9d770cfe) - TEST_JAL(0xe0814d80, 0x535d93c0, 0xe0814d80, 0x535d93c0) - TEST_JAL(0x9886e010, 0x300135f0, 0x9886e010, 0x300135f0) - TEST_JAL(0x70f4bbd4, 0x0afa6080, 0x70f4bbd4, 0x0afa6080) - TEST_JAL(0x957d3bd2, 0x5726030a, 0x957d3bd2, 0x5726030a) - TEST_JAL(0xff441412, 0x93520ef6, 0xff441412, 0x93520ef6) - TEST_JAL(0xa3ad1eca, 0x0f86f200, 0xa3ad1eca, 0x0f86f200) - TEST_JAL(0xe6bd89c0, 0x01dc0560, 0xe6bd89c0, 0x01dc0560) - TEST_JAL(0xf5e4174e, 0xbefbf528, 0xf5e4174e, 0xbefbf528) - TEST_JAL(0x0e2e04b8, 0x5e3ad5e9, 0x0e2e04b8, 0x5e3ad5e9) - TEST_JAL(0xf0132abc, 0x6a99fa90, 0xf0132abc, 0x6a99fa90) - TEST_JAL(0xd29b6d80, 0x5fde970c, 0xd29b6d80, 0x5fde970c) - TEST_JAL(0xb35fc4b0, 0x0b665f50, 0xb35fc4b0, 0x0b665f50) - TEST_JAL(0x8f73c708, 0x60315db8, 0x8f73c708, 0x60315db8) - TEST_JAL(0x148c1328, 0xb37f2bf5, 0x148c1328, 0xb37f2bf5) - TEST_JAL(0x7731562a, 0xb0d0928d, 0x7731562a, 0xb0d0928d) - TEST_JAL(0xe8469a78, 0xf1e42cc0, 0xe8469a78, 0xf1e42cc0) - TEST_JAL(0x872f83e8, 0x9e525fe0, 0x872f83e8, 0x9e525fe0) - TEST_JAL(0xca114c7f, 0xd1613e14, 0xca114c7f, 0xd1613e14) - TEST_JAL(0x1f771c40, 0x5c131564, 0x1f771c40, 0x5c131564) - TEST_JAL(0x59892de4, 0x7c4d6241, 0x59892de4, 0x7c4d6241) - TEST_JAL(0x762014e5, 0xb748edf0, 0x762014e5, 0xb748edf0) - TEST_JAL(0x0630a598, 0xbf4fc5a0, 0x0630a598, 0xbf4fc5a0) - TEST_JAL(0x3d40efc0, 0xedfb0588, 0x3d40efc0, 0xedfb0588) - TEST_JAL(0xf36d1638, 0x04b484c0, 0xf36d1638, 0x04b484c0) - TEST_JAL(0xaf105dfc, 0xa7ba2b5c, 0xaf105dfc, 0xa7ba2b5c) - TEST_JAL(0x443323f8, 0xf9a5cf25, 0x443323f8, 0xf9a5cf25) - TEST_JAL(0x958083cc, 0x7abfbd64, 0x958083cc, 0x7abfbd64) - TEST_JAL(0x0849c579, 0x494076ef, 0x0849c579, 0x494076ef) - TEST_JAL(0x0c3d52a0, 0x095f1c90, 0x0c3d52a0, 0x095f1c90) - TEST_JAL(0x7869bfbc, 0x5b92ccac, 0x7869bfbc, 0x5b92ccac) - TEST_JAL(0xc45cefa4, 0x7006ab64, 0xc45cefa4, 0x7006ab64) - TEST_JAL(0x9641dae6, 0x21bd0b07, 0x9641dae6, 0x21bd0b07) - TEST_JAL(0x4cd7ccef, 0xb838965b, 0x4cd7ccef, 0xb838965b) - TEST_JAL(0xd924322a, 0x9ebbb9dc, 0xd924322a, 0x9ebbb9dc) - TEST_JAL(0xb9080a70, 0xcffad758, 0xb9080a70, 0xcffad758) - TEST_JAL(0x53a61c51, 0xd9776eae, 0x53a61c51, 0xd9776eae) - TEST_JAL(0xa2afbf34, 0x47562800, 0xa2afbf34, 0x47562800) - TEST_JAL(0x5edf2815, 0x09654c40, 0x5edf2815, 0x09654c40) - TEST_JAL(0x18fd52d0, 0x83ff1689, 0x18fd52d0, 0x83ff1689) - TEST_JAL(0xc18668c2, 0xec028728, 0xc18668c2, 0xec028728) - TEST_JAL(0x6cc55230, 0x9a0af75e, 0x6cc55230, 0x9a0af75e) - TEST_JAL(0xf5aaab48, 0xd1b0328c, 0xf5aaab48, 0xd1b0328c) - TEST_JAL(0xf3ff4eac, 0xce6aecb3, 0xf3ff4eac, 0xce6aecb3) - TEST_JAL(0x0947cf11, 0x2c07ace8, 0x0947cf11, 0x2c07ace8) - TEST_JAL(0x5eaec54e, 0x94d512f8, 0x5eaec54e, 0x94d512f8) - TEST_JAL(0xa07b8e00, 0xddfdbc60, 0xa07b8e00, 0xddfdbc60) - TEST_JAL(0xcf09fb60, 0x23296371, 0xcf09fb60, 0x23296371) - TEST_JAL(0x00cda400, 0x526632b0, 0x00cda400, 0x526632b0) - TEST_JAL(0xf2367e0c, 0xdb2154f8, 0xf2367e0c, 0xdb2154f8) - TEST_JAL(0x5b73db50, 0x23c55346, 0x5b73db50, 0x23c55346) - TEST_JAL(0x99393820, 0xb3472a6c, 0x99393820, 0xb3472a6c) - TEST_JAL(0xca33c824, 0x38659bc8, 0xca33c824, 0x38659bc8) - TEST_JAL(0x3d8d2c44, 0xe6595cd2, 0x3d8d2c44, 0xe6595cd2) - TEST_JAL(0x9db739aa, 0x940d49fe, 0x9db739aa, 0x940d49fe) - TEST_JAL(0x34af7570, 0x30a1f5c4, 0x34af7570, 0x30a1f5c4) - TEST_JAL(0x2d1b57d7, 0x559e4a76, 0x2d1b57d7, 0x559e4a76) - TEST_JAL(0xa424d030, 0x4a029754, 0xa424d030, 0x4a029754) - TEST_JAL(0xf5f1fea0, 0x17c22c9e, 0xf5f1fea0, 0x17c22c9e) - TEST_JAL(0xc2e26918, 0x555e1066, 0xc2e26918, 0x555e1066) - TEST_JAL(0x2eb1d6d6, 0x0f003580, 0x2eb1d6d6, 0x0f003580) - TEST_JAL(0x32eae280, 0x174f4580, 0x32eae280, 0x174f4580) - TEST_JAL(0x824c9710, 0xb2d3fe09, 0x824c9710, 0xb2d3fe09) - TEST_JAL(0xf41338d8, 0x7d527120, 0xf41338d8, 0x7d527120) - TEST_JAL(0x2ff13590, 0xe51179de, 0x2ff13590, 0xe51179de) - TEST_JAL(0x6310dd60, 0x9423fac0, 0x6310dd60, 0x9423fac0) - TEST_JAL(0x9f434002, 0x775d06fc, 0x9f434002, 0x775d06fc) - TEST_JAL(0x49b9c1c0, 0xa4a1f200, 0x49b9c1c0, 0xa4a1f200) - TEST_JAL(0x52eafe00, 0xfaddf60c, 0x52eafe00, 0xfaddf60c) - TEST_JAL(0xd280ee0a, 0x2176f4c0, 0xd280ee0a, 0x2176f4c0) - TEST_JAL(0xe9bc5a90, 0xab0421a6, 0xe9bc5a90, 0xab0421a6) - TEST_JAL(0x8335d66d, 0xdaf2c222, 0x8335d66d, 0xdaf2c222) + TEST_JAL(0x18e08d00, 0x6fa3619e, 0x18e08d00, 0x6fa3619e) HIT_GOOD_TRAP inst_error: - HIT_BAD_TRAP \ No newline at end of file + HIT_BAD_TRAP diff --git "a/TEMU/mips_sc/src/\346\265\213\350\257\225\346\214\207\344\273\244.md" "b/TEMU/mips_sc/src/\346\265\213\350\257\225\346\214\207\344\273\244.md" index 7562c57..662e3d2 100644 --- "a/TEMU/mips_sc/src/\346\265\213\350\257\225\346\214\207\344\273\244.md" +++ "b/TEMU/mips_sc/src/\346\265\213\350\257\225\346\214\207\344\273\244.md" @@ -36,7 +36,7 @@ | bltz | | | | bgezal | | | | bltzal | | | -| j | | 1 | +| j | | | | jal | for | 1 | | jr | for | 1 | | jalr | | | -- Gitee From de64fc19d6f165afb2d0d0fcae2652e88baa3d27 Mon Sep 17 00:00:00 2001 From: hua-yi-123 <1342881632@qq.com> Date: Wed, 3 Nov 2021 15:01:50 +0800 Subject: [PATCH 3/3] temp --- .../ip/2019.2/9888347cfb290ede/stats.txt | 2 + .../MiniMIPS32.cache/wt/gui_handlers.wdf | 21 +- .../wt/java_command_handlers.wdf | 7 +- .../MiniMIPS32.cache/wt/project.wpc | 2 +- .../MiniMIPS32.cache/wt/synthesis.wdf | 39 - .../MiniMIPS32.cache/wt/webtalk_pa.xml | 30 +- .../sim_scripts/inst_rom/activehdl/README.txt | 2 +- .../sim_scripts/inst_rom/activehdl/compile.do | 6 +- .../inst_rom/activehdl/file_info.txt | 6 +- .../inst_rom/activehdl/inst_rom.sh | 4 +- .../sim_scripts/inst_rom/ies/README.txt | 2 +- .../sim_scripts/inst_rom/ies/file_info.txt | 6 +- .../sim_scripts/inst_rom/ies/inst_rom.sh | 2 +- .../sim_scripts/inst_rom/ies/run.f | 6 +- .../sim_scripts/inst_rom/modelsim/README.txt | 2 +- .../sim_scripts/inst_rom/modelsim/compile.do | 6 +- .../inst_rom/modelsim/file_info.txt | 6 +- .../sim_scripts/inst_rom/modelsim/inst_rom.sh | 4 +- .../sim_scripts/inst_rom/questa/README.txt | 2 +- .../sim_scripts/inst_rom/questa/compile.do | 6 +- .../sim_scripts/inst_rom/questa/file_info.txt | 6 +- .../sim_scripts/inst_rom/questa/inst_rom.sh | 4 +- .../sim_scripts/inst_rom/riviera/README.txt | 2 +- .../sim_scripts/inst_rom/riviera/compile.do | 6 +- .../inst_rom/riviera/file_info.txt | 6 +- .../sim_scripts/inst_rom/riviera/inst_rom.sh | 4 +- .../sim_scripts/inst_rom/vcs/README.txt | 2 +- .../sim_scripts/inst_rom/vcs/file_info.txt | 6 +- .../sim_scripts/inst_rom/vcs/inst_rom.sh | 8 +- .../sim_scripts/inst_rom/xcelium/README.txt | 2 +- .../inst_rom/xcelium/file_info.txt | 6 +- .../sim_scripts/inst_rom/xcelium/inst_rom.sh | 2 +- .../sim_scripts/inst_rom/xcelium/run.f | 6 +- .../sim_scripts/inst_rom/xsim/README.txt | 2 +- .../sim_scripts/inst_rom/xsim/inst_rom.sh | 6 +- .../MiniMIPS32.runs/.jobs/vrs_config_15.xml | 9 + .../.Vivado_Synthesis.queue.rst | 0 .../inst_rom_synth_1/.vivado.begin.rst | 5 - .../inst_rom_synth_1/.vivado.end.rst | 0 .../inst_rom_synth_1/ISEWrap.js | 270 ---- .../inst_rom_synth_1/ISEWrap.sh | 67 - .../__synthesis_is_complete__ | 0 .../inst_rom_synth_1/dont_touch.xdc | 16 - .../inst_rom_synth_1/gen_run.xml | 45 - .../MiniMIPS32.runs/inst_rom_synth_1/htr.txt | 9 - .../inst_rom_synth_1/inst_rom.dcp | Bin 39220 -> 0 bytes .../inst_rom_synth_1/inst_rom.tcl | 170 --- .../inst_rom_synth_1/inst_rom.vds | 456 ------ .../inst_rom_utilization_synth.pb | Bin 289 -> 0 bytes .../inst_rom_utilization_synth.rpt | 174 --- .../inst_rom_synth_1/project.wdf | 34 - .../inst_rom_synth_1/rundef.js | 36 - .../inst_rom_synth_1/runme.bat | 10 - .../inst_rom_synth_1/runme.log | 455 ------ .../MiniMIPS32.runs/inst_rom_synth_1/runme.sh | 43 - .../inst_rom_synth_1/vivado.jou | 12 - .../inst_rom_synth_1/vivado.pb | Bin 55181 -> 0 bytes .../behav/xsim/MiniMIPS32_SYS_tb_behav.wdb | Bin 214102 -> 215979 bytes .../sim_1/behav/xsim/compile.bat | 2 +- .../sim_1/behav/xsim/compile.log | 10 - .../sim_1/behav/xsim/elaborate.bat | 2 +- .../sim_1/behav/xsim/elaborate.log | 50 - .../sim_1/behav/xsim/simulate.bat | 2 +- .../sim_1/behav/xsim/webtalk.jou | 4 +- .../sim_1/behav/xsim/webtalk.log | 6 +- .../sim_1/behav/xsim/webtalk_23084.backup.jou | 12 + .../sim_1/behav/xsim/webtalk_23084.backup.log | 13 + .../sim_1/behav/xsim/webtalk_26756.backup.jou | 12 + .../sim_1/behav/xsim/webtalk_26756.backup.log | 13 + .../MiniMIPS32.sim/sim_1/behav/xsim/xelab.pb | Bin 7383 -> 7710 bytes .../obj/xsim_0.win64.obj | Bin 956334 -> 959299 bytes .../MiniMIPS32_SYS_tb_behav/obj/xsim_1.c | 177 +-- .../obj/xsim_1.win64.obj | Bin 29943 -> 30504 bytes .../webtalk/usage_statistics_ext_xsim.wdm | 38 - .../webtalk/xsim_webtalk.tcl | 32 - .../xsim.dir/MiniMIPS32_SYS_tb_behav/xsim.dbg | Bin 183744 -> 184336 bytes .../xsim.dir/MiniMIPS32_SYS_tb_behav/xsim.mem | Bin 62346 -> 62776 bytes .../MiniMIPS32_SYS_tb_behav/xsim.reloc | Bin 52162 -> 52671 bytes .../xsim.dir/MiniMIPS32_SYS_tb_behav/xsim.rlx | 2 +- .../MiniMIPS32_SYS_tb_behav/xsim.rtti | Bin 547 -> 547 bytes .../MiniMIPS32_SYS_tb_behav/xsim.xdbg | Bin 144096 -> 146400 bytes .../MiniMIPS32_SYS_tb_behav/xsimSettings.ini | 2 +- .../MiniMIPS32_SYS_tb_behav/xsimk.exe | Bin 908644 -> 912071 bytes .../MiniMIPS32_SYS_tb_behav/xsimkernel.log | 10 +- .../xil_defaultlib/@mini@m@i@p@s32.sdb | Bin 15627 -> 16030 bytes .../xil_defaultlib/@mini@m@i@p@s32_@s@y@s.sdb | Bin 2322 -> 2343 bytes .../xsim/xsim.dir/xil_defaultlib/alu.sdb | Bin 1678 -> 1636 bytes .../xsim/xsim.dir/xil_defaultlib/clkdiv.sdb | Bin 1229 -> 1250 bytes .../xil_defaultlib/clkdiv_clk_wiz.sdb | Bin 4913 -> 4934 bytes .../xsim/xsim.dir/xil_defaultlib/data_ram.sdb | Bin 6908 -> 6929 bytes .../xsim/xsim.dir/xil_defaultlib/dcu.sdb | Bin 30429 -> 30335 bytes .../xsim.dir/xil_defaultlib/exemem_reg.sdb | Bin 3104 -> 3062 bytes .../xsim/xsim.dir/xil_defaultlib/hilo.sdb | Bin 1536 -> 1494 bytes .../xsim.dir/xil_defaultlib/idexe_reg.sdb | Bin 3724 -> 3682 bytes .../xsim/xsim.dir/xil_defaultlib/ifid_reg.sdb | Bin 1518 -> 1476 bytes .../xsim/xsim.dir/xil_defaultlib/inst_rom.sdb | Bin 6628 -> 6649 bytes .../xsim/xsim.dir/xil_defaultlib/mcu.sdb | Bin 8011 -> 7969 bytes .../xsim.dir/xil_defaultlib/memwb_reg.sdb | Bin 2647 -> 2890 bytes .../xsim/xsim.dir/xil_defaultlib/mux2.sdb | Bin 959 -> 917 bytes .../xsim/xsim.dir/xil_defaultlib/mux3.sdb | Bin 1380 -> 1338 bytes .../xsim/xsim.dir/xil_defaultlib/mux4.sdb | Bin 1479 -> 1437 bytes .../xsim/xsim.dir/xil_defaultlib/mux5.sdb | Bin 1614 -> 1572 bytes .../xsim/xsim.dir/xil_defaultlib/pc_reg.sdb | Bin 1523 -> 1481 bytes .../xsim/xsim.dir/xil_defaultlib/register.sdb | Bin 4869 -> 4827 bytes .../xsim/xsim.dir/xil_defaultlib/scu.sdb | Bin 1066 -> 1024 bytes .../xil_defaultlib/xil_defaultlib.rlx | 4 +- .../MiniMIPS32.sim/sim_1/behav/xsim/xvlog.log | 30 + .../MiniMIPS32.sim/sim_1/behav/xsim/xvlog.pb | Bin 1822 -> 6973 bytes .../sources_1/ip/inst_rom/inst_rom.dcp | Bin 39220 -> 0 bytes .../sources_1/ip/inst_rom/inst_rom.xci | 2 +- .../sources_1/ip/inst_rom/inst_rom.xml | 132 +- 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-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a303873:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313135372e3234324d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3835352e3532334d42:00:00 -eof:2444511432 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/webtalk_pa.xml b/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/webtalk_pa.xml index cba3e9f..f1f366a 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/webtalk_pa.xml +++ b/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +

@@ -17,25 +17,27 @@ This means code written to parse this file will need to be revisited each subseq - + + - + - + - - - - - - + + + + + + + - - + + @@ -43,9 +45,9 @@ This means code written to parse this file will need to be revisited each subseq - + - +
diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/README.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/README.txt index 06805b0..312b6d1 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/README.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Oct 30 21:48:40 +0800 2021 +# Generated by export_simulation on Tue Nov 02 23:18:58 +0800 2021 # ################################################################################ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/compile.do b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/compile.do index 5676c20..fd60353 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/compile.do +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/compile.do @@ -10,11 +10,11 @@ vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 vmap xil_defaultlib activehdl/xil_defaultlib vlog -work xpm -sv2k12 \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -93 \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work blk_mem_gen_v8_4_4 -v2k5 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/file_info.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/file_info.txt index 1d40a9a..428eee3 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/file_info.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, inst_rom.v,verilog,xil_defaultlib,../../../../MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/inst_rom.sh b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/inst_rom.sh index 58c5a8c..076fee9 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/inst_rom.sh +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/activehdl/inst_rom.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Oct 30 21:48:40 +0800 2021 +# Generated by Vivado on Tue Nov 02 23:18:58 +0800 2021 # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -96,7 +96,7 @@ map_setup_file() if [[ ($1 != "") ]]; then lib_map_path="$1" else - lib_map_path="G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/compile_simlib/activehdl" + lib_map_path="F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/compile_simlib/activehdl" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/README.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/README.txt index b58153b..5b215a7 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/README.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Oct 30 21:48:40 +0800 2021 +# Generated by export_simulation on Tue Nov 02 23:18:58 +0800 2021 # ################################################################################ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/file_info.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/file_info.txt index 1d40a9a..428eee3 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/file_info.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, inst_rom.v,verilog,xil_defaultlib,../../../../MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/inst_rom.sh b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/inst_rom.sh index acc885d..f6908ad 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/inst_rom.sh +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/inst_rom.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Oct 30 21:48:40 +0800 2021 +# Generated by Vivado on Tue Nov 02 23:18:58 +0800 2021 # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/run.f b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/run.f index ced7e8d..26309e5 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/run.f +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/ies/run.f @@ -1,9 +1,9 @@ -makelib ies_lib/xpm -sv \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ -endlib -makelib ies_lib/xpm \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ -endlib -makelib ies_lib/blk_mem_gen_v8_4_4 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/README.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/README.txt index 06805b0..312b6d1 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/README.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Oct 30 21:48:40 +0800 2021 +# Generated by export_simulation on Tue Nov 02 23:18:58 +0800 2021 # ################################################################################ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/compile.do b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/compile.do index 52bb69b..359f091 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/compile.do +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/compile.do @@ -10,11 +10,11 @@ vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib vlog -work xpm -64 -incr -sv \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -64 -93 \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work blk_mem_gen_v8_4_4 -64 -incr \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/file_info.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/file_info.txt index 1d40a9a..428eee3 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/file_info.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, inst_rom.v,verilog,xil_defaultlib,../../../../MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/inst_rom.sh b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/inst_rom.sh index 9bf547b..66e7b5a 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/inst_rom.sh +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/modelsim/inst_rom.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Oct 30 21:48:40 +0800 2021 +# Generated by Vivado on Tue Nov 02 23:18:58 +0800 2021 # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -98,7 +98,7 @@ copy_setup_file() if [[ ($1 != "") ]]; then lib_map_path="$1" else - lib_map_path="G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/compile_simlib/modelsim" + lib_map_path="F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/compile_simlib/modelsim" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/README.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/README.txt index 06805b0..312b6d1 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/README.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Oct 30 21:48:40 +0800 2021 +# Generated by export_simulation on Tue Nov 02 23:18:58 +0800 2021 # ################################################################################ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/compile.do b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/compile.do index 0804405..f80f561 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/compile.do +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/compile.do @@ -10,11 +10,11 @@ vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 vmap xil_defaultlib questa_lib/msim/xil_defaultlib vlog -work xpm -64 -sv \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -64 -93 \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work blk_mem_gen_v8_4_4 -64 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/file_info.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/file_info.txt index 1d40a9a..428eee3 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/file_info.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, inst_rom.v,verilog,xil_defaultlib,../../../../MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/inst_rom.sh b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/inst_rom.sh index 10f54f7..40ff08e 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/inst_rom.sh +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/questa/inst_rom.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Oct 30 21:48:40 +0800 2021 +# Generated by Vivado on Tue Nov 02 23:18:58 +0800 2021 # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -105,7 +105,7 @@ copy_setup_file() if [[ ($1 != "") ]]; then lib_map_path="$1" else - lib_map_path="G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/compile_simlib/questa" + lib_map_path="F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/compile_simlib/questa" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/README.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/README.txt index 06805b0..312b6d1 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/README.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Oct 30 21:48:40 +0800 2021 +# Generated by export_simulation on Tue Nov 02 23:18:58 +0800 2021 # ################################################################################ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/compile.do b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/compile.do index 8902359..64e3966 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/compile.do +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/compile.do @@ -10,11 +10,11 @@ vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 vmap xil_defaultlib riviera/xil_defaultlib vlog -work xpm -sv2k12 \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -93 \ -"F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ +"E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work blk_mem_gen_v8_4_4 -v2k5 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/file_info.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/file_info.txt index 1d40a9a..428eee3 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/file_info.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, inst_rom.v,verilog,xil_defaultlib,../../../../MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/inst_rom.sh b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/inst_rom.sh index c4a09ce..64189d9 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/inst_rom.sh +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/riviera/inst_rom.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Oct 30 21:48:40 +0800 2021 +# Generated by Vivado on Tue Nov 02 23:18:58 +0800 2021 # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -96,7 +96,7 @@ map_setup_file() if [[ ($1 != "") ]]; then lib_map_path="$1" else - lib_map_path="G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/compile_simlib/riviera" + lib_map_path="F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/compile_simlib/riviera" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/README.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/README.txt index 06805b0..312b6d1 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/README.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Oct 30 21:48:40 +0800 2021 +# Generated by export_simulation on Tue Nov 02 23:18:58 +0800 2021 # ################################################################################ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/file_info.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/file_info.txt index 1d40a9a..428eee3 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/file_info.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, inst_rom.v,verilog,xil_defaultlib,../../../../MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/inst_rom.sh b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/inst_rom.sh index 5446459..14da028 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/inst_rom.sh +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/vcs/inst_rom.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Oct 30 21:48:40 +0800 2021 +# Generated by Vivado on Tue Nov 02 23:18:58 +0800 2021 # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -71,12 +71,12 @@ compile() { # Compile design files vlogan -work xpm $vlogan_opts -sverilog \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ 2>&1 | tee -a vlogan.log vhdlan -work xpm $vhdlan_opts \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ 2>&1 | tee -a vhdlan.log vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k \ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/README.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/README.txt index b58153b..5b215a7 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/README.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Oct 30 21:48:40 +0800 2021 +# Generated by export_simulation on Tue Nov 02 23:18:58 +0800 2021 # ################################################################################ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/file_info.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/file_info.txt index 1d40a9a..428eee3 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/file_info.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, inst_rom.v,verilog,xil_defaultlib,../../../../MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/inst_rom.sh b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/inst_rom.sh index 902d7cd..72b1d48 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/inst_rom.sh +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/inst_rom.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Oct 30 21:48:40 +0800 2021 +# Generated by Vivado on Tue Nov 02 23:18:58 +0800 2021 # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/run.f b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/run.f index c88b553..addd3aa 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/run.f +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xcelium/run.f @@ -1,9 +1,9 @@ -makelib xcelium_lib/xpm -sv \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ -endlib -makelib xcelium_lib/xpm \ - "F:/vivado/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ + "E:/xlinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ -endlib -makelib xcelium_lib/blk_mem_gen_v8_4_4 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xsim/README.txt b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xsim/README.txt index 06805b0..312b6d1 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xsim/README.txt +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Oct 30 21:48:40 +0800 2021 +# Generated by export_simulation on Tue Nov 02 23:18:58 +0800 2021 # ################################################################################ diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xsim/inst_rom.sh b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xsim/inst_rom.sh index 2034a73..babb88d 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xsim/inst_rom.sh +++ b/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/sim_scripts/inst_rom/xsim/inst_rom.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Oct 30 21:48:40 +0800 2021 +# Generated by Vivado on Tue Nov 02 23:18:58 +0800 2021 # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -22,7 +22,7 @@ #********************************************************************************************************* # Command line options -xv_boost_lib_path=F:/vivado/Vivado/2019.2/tps/boost_1_64_0 +xv_boost_lib_path=E:/xlinx/Vivado/2019.2/tps/boost_1_64_0 xvlog_opts="--relax" @@ -92,7 +92,7 @@ setup() copy_setup_file() { file="xsim.ini" - lib_map_path="F:/vivado/Vivado/2019.2/data/xsim" + lib_map_path="E:/xlinx/Vivado/2019.2/data/xsim" if [[ ($1 != "") ]]; then lib_map_path="$1" fi diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/.jobs/vrs_config_15.xml b/CPU_core/MiniMIPS32/MiniMIPS32.runs/.jobs/vrs_config_15.xml new file mode 100644 index 0000000..d796a91 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/.jobs/vrs_config_15.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/.Vivado_Synthesis.queue.rst b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29..0000000 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/.vivado.begin.rst b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/.vivado.begin.rst deleted file mode 100644 index 99e9d9c..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/.vivado.end.rst b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/ISEWrap.js b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/ISEWrap.js deleted file mode 100644 index 97a2ecb..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/ISEWrap.sh b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/__synthesis_is_complete__ b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29..0000000 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc deleted file mode 100644 index ba0bb78..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc +++ /dev/null @@ -1,16 +0,0 @@ -# This file is automatically generated. -# It contains project source information necessary for synthesis and implementation. - -# IP: G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xci -# IP: The module: 'inst_rom' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: g:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'inst_rom'. Do not add the DONT_TOUCH constraint. -set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# IP: G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xci -# IP: The module: 'inst_rom' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: g:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'inst_rom'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/gen_run.xml b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/gen_run.xml deleted file mode 100644 index 4f74933..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/gen_run.xml +++ /dev/null @@ -1,45 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/htr.txt b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/htr.txt deleted file mode 100644 index 7a50776..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log inst_rom.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_rom.tcl diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp deleted file mode 100644 index 866d8bdb36b4b31015071e00604771a81a2feea3..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 39220 zcmc$_WmH^Ex9>}Eg1ZF>PH=Y#1b26Lch}(7xVr^+cL`2#cXxLh&uyOfyl3xy?%3y! z{po(Gn)08s*6QxD#;>cZ<)t7XF~GpUV8OQcF{V#YyF{l2Su0`bDNIdQq$sgNp{4t zEsVB?V7M0nOqtSyq~{O4M5K%4L=+;6`1;ATa{hIne*X?B>cPeYBh|mV487XG0kb0j zhj=KK8UGAJRVOrm-CM?qncHT+4kjShmqC!woybQ2>t=q$U4ZezIQcDG$lZuFME(n= z*(;d@F;Z0Y(zlI$XAQ}1NYgZv!@{K6P0j#C=rr<{U-yTU7)(xaXAUDdRK+5+3@@)S zIn&fJCKM5YGX@2AYT2i$?%{e#zF1+w6*P18onYN%yLFiXSCiL{X!ty~SHcSh#+I84 zq?8&LcPFooB#6sH>IJ{o?U{oIYjo}aYgTl278{l3k+eIH{hwc_HbN@d2PI~-6{}}| z85RER6s`7XE{Vzs9k9l~H>28ZBa2%xvn!q&-I&(Y3?-o)5+-N!0nhqLYh_=G9!$GJ*iwqdKs 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file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param project.vivado.isBlockSynthRun true -set_msg_config -msgmgr_mode ooc_run -create_project -in_memory -part xc7k325tffg900-2 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/wt [current_project] -set_property parent.project_path G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.xpr [current_project] -set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language Verilog [current_project] -set_property ip_output_repo g:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xci -set_property used_in_implementation false [get_files -all g:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_ooc.xdc] - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -read_xdc dont_touch.xdc -set_property used_in_implementation false [get_files dont_touch.xdc] -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1 -new_name inst_rom -ip [get_ips inst_rom]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top inst_rom -part xc7k325tffg900-2 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix inst_rom_ inst_rom.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ inst_rom_stub.v - lappend ipCachedFiles inst_rom_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ inst_rom_stub.vhdl - lappend ipCachedFiles inst_rom_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ inst_rom_sim_netlist.v - lappend ipCachedFiles inst_rom_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ inst_rom_sim_netlist.vhdl - lappend ipCachedFiles inst_rom_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp inst_rom.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips inst_rom] -} - -rename_ref -prefix_all inst_rom_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef inst_rom.dcp -create_report "inst_rom_synth_1_synth_report_utilization_0" "report_utilization -file inst_rom_utilization_synth.rpt -pb inst_rom_utilization_synth.pb" - -if { [catch { - file copy -force G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - write_verilog -force -mode synth_stub G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -if { [catch { - file copy -force G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.dcp -} _RESULT ] } { - send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - file rename -force G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_stub.v G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_stub.vhdl G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_sim_netlist.v G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - file rename -force G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_sim_netlist.vhdl G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -}; # end if cached_ip - -if {[file isdir G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/ip/inst_rom]} { - catch { - file copy -force G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/ip/inst_rom - } -} - -if {[file isdir G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/ip/inst_rom]} { - catch { - file copy -force G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.ip_user_files/ip/inst_rom - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.vds b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.vds deleted file mode 100644 index 24e233d..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.vds +++ /dev/null @@ -1,456 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.2 (64-bit) -# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 -# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 -# Start of session at: Fri Oct 29 14:29:11 2021 -# Process ID: 21032 -# Current directory: G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1 -# Command line: vivado.exe -log inst_rom.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_rom.tcl -# Log file: G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.vds -# Journal file: G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1\vivado.jou -#----------------------------------------------------------- -source inst_rom.tcl -notrace -Command: synth_design -top inst_rom -part xc7k325tffg900-2 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' -INFO: [Device 21-403] Loading part xc7k325tffg900-2 -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 13896 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 865.531 ; gain = 234.852 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'inst_rom' [g:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/synth/inst_rom.vhd:68] - Parameter C_FAMILY bound to: kintex7 - type: string - Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string - Parameter C_ELABORATION_DIR bound to: ./ - type: string - Parameter C_INTERFACE_TYPE bound to: 0 - type: integer - Parameter C_AXI_TYPE bound to: 1 - type: integer - Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer - Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer - Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer - Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string - Parameter C_HAS_AXI_ID bound to: 0 - type: integer - Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer - Parameter C_MEM_TYPE bound to: 3 - type: integer - Parameter C_BYTE_SIZE bound to: 9 - type: integer - Parameter C_ALGORITHM bound to: 1 - type: integer - Parameter C_PRIM_TYPE bound to: 1 - type: integer - Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer - Parameter C_INIT_FILE_NAME bound to: inst_rom.mif - type: string - Parameter C_INIT_FILE bound to: inst_rom.mem - type: string - Parameter C_USE_DEFAULT_DATA bound to: 0 - type: integer - Parameter C_DEFAULT_DATA bound to: 0 - type: string - Parameter C_HAS_RSTA bound to: 0 - type: integer - Parameter C_RST_PRIORITY_A bound to: CE - type: string - Parameter C_RSTRAM_A bound to: 0 - type: integer - Parameter C_INITA_VAL bound to: 0 - type: string - Parameter C_HAS_ENA bound to: 1 - type: integer - Parameter C_HAS_REGCEA bound to: 0 - type: integer - Parameter C_USE_BYTE_WEA bound to: 0 - type: integer - Parameter C_WEA_WIDTH bound to: 1 - type: integer - Parameter C_WRITE_MODE_A bound to: WRITE_FIRST - type: string - Parameter C_WRITE_WIDTH_A bound to: 32 - type: integer - Parameter C_READ_WIDTH_A bound to: 32 - type: integer - Parameter C_WRITE_DEPTH_A bound to: 2048 - type: integer - Parameter C_READ_DEPTH_A bound to: 2048 - type: integer - Parameter C_ADDRA_WIDTH bound to: 11 - type: integer - Parameter C_HAS_RSTB bound to: 0 - type: integer - Parameter C_RST_PRIORITY_B bound to: CE - type: string - Parameter C_RSTRAM_B bound to: 0 - type: integer - Parameter C_INITB_VAL bound to: 0 - type: string - Parameter C_HAS_ENB bound to: 0 - type: integer - Parameter C_HAS_REGCEB bound to: 0 - type: integer - Parameter C_USE_BYTE_WEB bound to: 0 - type: integer - Parameter C_WEB_WIDTH bound to: 1 - type: integer - Parameter C_WRITE_MODE_B bound to: WRITE_FIRST - type: string - Parameter C_WRITE_WIDTH_B bound to: 32 - type: integer - Parameter C_READ_WIDTH_B bound to: 32 - type: integer - Parameter C_WRITE_DEPTH_B bound to: 2048 - type: integer - Parameter C_READ_DEPTH_B bound to: 2048 - type: integer - Parameter C_ADDRB_WIDTH bound to: 11 - type: integer - Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 0 - type: integer - Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 0 - type: integer - Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 0 - type: integer - Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer - Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer - Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer - Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer - Parameter C_USE_SOFTECC bound to: 0 - type: integer - Parameter C_USE_ECC bound to: 0 - type: integer - Parameter C_EN_ECC_PIPE bound to: 0 - type: integer - Parameter C_READ_LATENCY_A bound to: 1 - type: integer - Parameter C_READ_LATENCY_B bound to: 1 - type: integer - Parameter C_HAS_INJECTERR bound to: 0 - type: integer - Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string - Parameter C_COMMON_CLK bound to: 0 - type: integer - Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer - Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer - Parameter C_USE_URAM bound to: 0 - type: integer - Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer - Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer - Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer - Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer - Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer - Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer - Parameter C_COUNT_36K_BRAM bound to: 2 - type: string - Parameter C_COUNT_18K_BRAM bound to: 0 - type: string - Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 4.8711 mW - type: string -INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_4' declared at 'g:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_4' [g:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/synth/inst_rom.vhd:232] -INFO: [Synth 8-256] done synthesizing module 'inst_rom' (9#1) [g:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/synth/inst_rom.vhd:68] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port CLKB -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[31] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[30] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[29] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[28] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[27] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[26] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[25] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[24] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[23] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[22] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[21] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[20] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[19] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[18] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[17] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[16] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[15] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[14] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[13] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[12] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[11] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[10] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[9] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[8] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[7] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[6] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[5] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[4] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[3] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[2] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[1] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[0] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port SBITERR_I -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DBITERR_I -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[10] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[9] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[8] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[7] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[6] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[5] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[4] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[3] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[2] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[1] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[0] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port SSRA -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port CLKB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port SSRB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ENB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port REGCEB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port WEB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[10] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[9] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[8] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[7] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[6] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[5] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[4] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[3] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[2] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[1] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[17] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[16] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[15] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[14] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[13] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[12] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[11] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[10] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[9] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[8] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[7] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[6] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[5] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[4] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[3] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[2] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[1] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port SLEEP -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port INJECTSBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port INJECTDBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ECCPIPECE -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ram_rstram_b -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ram_rstreg_b -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRA -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port CLKB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ENB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port REGCEB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port WEB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[10] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[9] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[8] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[7] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[6] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[5] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[4] -INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1157.242 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [g:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_ooc.xdc] for cell 'U0' -Finished Parsing XDC File [g:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_ooc.xdc] for cell 'U0' -Parsing XDC File [G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc] -Finished Parsing XDC File [G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc] -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1157.242 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1157.242 ; gain = 0.000 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7k325tffg900-2 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- -Applied set_property DONT_TOUCH = true for U0. (constraint file G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc, line 9). ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:48 ; elapsed = 00:00:50 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 840 (col length:140) -BRAMs: 890 (col length: RAMB18 140 RAMB36 70) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:49 ; elapsed = 00:00:51 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:57 ; elapsed = 00:00:59 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:57 ; elapsed = 00:00:59 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:57 ; elapsed = 00:00:59 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+-----------+------+ -| |Cell |Count | -+------+-----------+------+ -|1 |RAMB36E1 | 1| -|2 |RAMB36E1_1 | 1| -+------+-----------+------+ - -Report Instance Areas: -+------+---------------------------------------------+----------------------------------------------+------+ -| |Instance |Module |Cells | -+------+---------------------------------------------+----------------------------------------------+------+ -|1 |top | | 2| -|2 | U0 |blk_mem_gen_v8_4_4 | 2| -|3 | inst_blk_mem_gen |blk_mem_gen_v8_4_4_synth | 2| -|4 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top | 2| -|5 | \valid.cstr |blk_mem_gen_generic_cstr | 2| -|6 | \ramloop[0].ram.r |blk_mem_gen_prim_width | 1| -|7 | \prim_init.ram |blk_mem_gen_prim_wrapper_init | 1| -|8 | \ramloop[1].ram.r |blk_mem_gen_prim_width__parameterized0 | 1| -|9 | \prim_init.ram |blk_mem_gen_prim_wrapper_init__parameterized0 | 1| -+------+---------------------------------------------+----------------------------------------------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 230 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:01:00 . Memory (MB): peak = 1157.242 ; gain = 526.562 -Synthesis Optimization Complete : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 1157.242 ; gain = 526.562 -INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1157.242 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1157.242 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -17 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:01:06 ; elapsed = 00:01:09 . Memory (MB): peak = 1157.242 ; gain = 856.020 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1157.242 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp' has been generated. -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP inst_rom, cache-ID = 9888347cfb290ede -INFO: [Coretcl 2-1174] Renamed 8 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1157.242 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file inst_rom_utilization_synth.rpt -pb inst_rom_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri Oct 29 14:30:24 2021... diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_utilization_synth.pb b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_utilization_synth.pb deleted file mode 100644 index 6fab4e3897aef35a8388625017045ef7c7e26338..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 289 zcmd;LGcqu=)H9mItPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp- z7ZADE6(rK?24eSmgUGu;vcYkw4~YHAN6I}U!qq6=+27aK b-%kh1@o@C>bM;vp2vYJFNH*9X4Fa(Nu0BT0 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_utilization_synth.rpt b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_utilization_synth.rpt deleted file mode 100644 index e86ff19..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom_utilization_synth.rpt +++ /dev/null @@ -1,174 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 -| Date : Fri Oct 29 14:30:24 2021 -| Host : LAPTOP-M01GHSS7 running 64-bit major release (build 9200) -| Command : report_utilization -file inst_rom_utilization_synth.rpt -pb inst_rom_utilization_synth.pb -| Design : inst_rom -| Device : 7k325tffg900-2 -| Design State : Synthesized ------------------------------------------------------------------------------------------------------------ - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 0 | 0 | 203800 | 0.00 | -| LUT as Logic | 0 | 0 | 203800 | 0.00 | -| LUT as Memory | 0 | 0 | 64000 | 0.00 | -| Slice Registers | 0 | 0 | 407600 | 0.00 | -| Register as Flip Flop | 0 | 0 | 407600 | 0.00 | -| Register as Latch | 0 | 0 | 407600 | 0.00 | -| F7 Muxes | 0 | 0 | 101900 | 0.00 | -| F8 Muxes | 0 | 0 | 50950 | 0.00 | -+-------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 0 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+-------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------+------+-------+-----------+-------+ -| Block RAM Tile | 2 | 0 | 445 | 0.45 | -| RAMB36/FIFO* | 2 | 0 | 445 | 0.45 | -| RAMB36E1 only | 2 | | | | -| RAMB18 | 0 | 0 | 890 | 0.00 | -+-------------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 840 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 500 | 0.00 | -| Bonded IPADs | 0 | 0 | 50 | 0.00 | -| Bonded OPADs | 0 | 0 | 32 | 0.00 | -| PHY_CONTROL | 0 | 0 | 10 | 0.00 | -| PHASER_REF | 0 | 0 | 10 | 0.00 | -| OUT_FIFO | 0 | 0 | 40 | 0.00 | -| IN_FIFO | 0 | 0 | 40 | 0.00 | -| IDELAYCTRL | 0 | 0 | 10 | 0.00 | -| IBUFDS | 0 | 0 | 480 | 0.00 | -| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | -| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | -| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | -| ILOGIC | 0 | 0 | 500 | 0.00 | -| OLOGIC | 0 | 0 | 500 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 40 | 0.00 | -| MMCME2_ADV | 0 | 0 | 10 | 0.00 | -| PLLE2_ADV | 0 | 0 | 10 | 0.00 | -| BUFMRCE | 0 | 0 | 20 | 0.00 | -| BUFHCE | 0 | 0 | 168 | 0.00 | -| BUFR | 0 | 0 | 40 | 0.00 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| RAMB36E1 | 2 | Block Memory | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/project.wdf b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/project.wdf deleted file mode 100644 index 8e5271c..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/project.wdf +++ /dev/null @@ -1,34 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3137:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:34:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:34:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f345c636c6b646976:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f345c646174615f72616d:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f345c696e73745f726f6d:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3730:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3131:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3131:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3131:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3131:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3131:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3131:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3131:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6262316439623662383537613436623238383633623139316435353136326561:506172656e742050412070726f6a656374204944:00 -eof:1394867323 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/rundef.js b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/rundef.js deleted file mode 100644 index 8387ddd..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "F:/vivado/Vivado/2019.2/ids_lite/ISE/bin/nt64;F:/vivado/Vivado/2019.2/ids_lite/ISE/lib/nt64;F:/vivado/Vivado/2019.2/bin;"; -} else { - PathVal = "F:/vivado/Vivado/2019.2/ids_lite/ISE/bin/nt64;F:/vivado/Vivado/2019.2/ids_lite/ISE/lib/nt64;F:/vivado/Vivado/2019.2/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log inst_rom.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_rom.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.bat b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.bat deleted file mode 100644 index 1760626..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.log b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.log deleted file mode 100644 index 538ca71..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.log +++ /dev/null @@ -1,455 +0,0 @@ - -*** Running vivado - with args -log inst_rom.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_rom.tcl - - -****** Vivado v2019.2 (64-bit) - **** SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 - **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 - ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - -source inst_rom.tcl -notrace -Command: synth_design -top inst_rom -part xc7k325tffg900-2 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' -INFO: [Device 21-403] Loading part xc7k325tffg900-2 -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 13896 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 865.531 ; gain = 234.852 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'inst_rom' [g:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/synth/inst_rom.vhd:68] - Parameter C_FAMILY bound to: kintex7 - type: string - Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string - Parameter C_ELABORATION_DIR bound to: ./ - type: string - Parameter C_INTERFACE_TYPE bound to: 0 - type: integer - Parameter C_AXI_TYPE bound to: 1 - type: integer - Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer - Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer - Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer - Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string - Parameter C_HAS_AXI_ID bound to: 0 - type: integer - Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer - Parameter C_MEM_TYPE bound to: 3 - type: integer - Parameter C_BYTE_SIZE bound to: 9 - type: integer - Parameter C_ALGORITHM bound to: 1 - type: integer - Parameter C_PRIM_TYPE bound to: 1 - type: integer - Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer - Parameter C_INIT_FILE_NAME bound to: inst_rom.mif - type: string - Parameter C_INIT_FILE bound to: inst_rom.mem - type: string - Parameter C_USE_DEFAULT_DATA bound to: 0 - type: integer - Parameter C_DEFAULT_DATA bound to: 0 - type: string - Parameter C_HAS_RSTA bound to: 0 - type: integer - Parameter C_RST_PRIORITY_A bound to: CE - type: string - Parameter C_RSTRAM_A bound to: 0 - type: integer - Parameter C_INITA_VAL bound to: 0 - type: string - Parameter C_HAS_ENA bound to: 1 - type: integer - Parameter C_HAS_REGCEA bound to: 0 - type: integer - Parameter C_USE_BYTE_WEA bound to: 0 - type: integer - Parameter C_WEA_WIDTH bound to: 1 - type: integer - Parameter C_WRITE_MODE_A bound to: WRITE_FIRST - type: string - Parameter C_WRITE_WIDTH_A bound to: 32 - type: integer - Parameter C_READ_WIDTH_A bound to: 32 - type: integer - Parameter C_WRITE_DEPTH_A bound to: 2048 - type: integer - Parameter C_READ_DEPTH_A bound to: 2048 - type: integer - Parameter C_ADDRA_WIDTH bound to: 11 - type: integer - Parameter C_HAS_RSTB bound to: 0 - type: integer - Parameter C_RST_PRIORITY_B bound to: CE - type: string - Parameter C_RSTRAM_B bound to: 0 - type: integer - Parameter C_INITB_VAL bound to: 0 - type: string - Parameter C_HAS_ENB bound to: 0 - type: integer - Parameter C_HAS_REGCEB bound to: 0 - type: integer - Parameter C_USE_BYTE_WEB bound to: 0 - type: integer - Parameter C_WEB_WIDTH bound to: 1 - type: integer - Parameter C_WRITE_MODE_B bound to: WRITE_FIRST - type: string - Parameter C_WRITE_WIDTH_B bound to: 32 - type: integer - Parameter C_READ_WIDTH_B bound to: 32 - type: integer - Parameter C_WRITE_DEPTH_B bound to: 2048 - type: integer - Parameter C_READ_DEPTH_B bound to: 2048 - type: integer - Parameter C_ADDRB_WIDTH bound to: 11 - type: integer - Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 0 - type: integer - Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 0 - type: integer - Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 0 - type: integer - Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer - Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer - Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer - Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer - Parameter C_USE_SOFTECC bound to: 0 - type: integer - Parameter C_USE_ECC bound to: 0 - type: integer - Parameter C_EN_ECC_PIPE bound to: 0 - type: integer - Parameter C_READ_LATENCY_A bound to: 1 - type: integer - Parameter C_READ_LATENCY_B bound to: 1 - type: integer - Parameter C_HAS_INJECTERR bound to: 0 - type: integer - Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string - Parameter C_COMMON_CLK bound to: 0 - type: integer - Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer - Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer - Parameter C_USE_URAM bound to: 0 - type: integer - Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer - Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer - Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer - Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer - Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer - Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer - Parameter C_COUNT_36K_BRAM bound to: 2 - type: string - Parameter C_COUNT_18K_BRAM bound to: 0 - type: string - Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 4.8711 mW - type: string -INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_4' declared at 'g:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_4' [g:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/synth/inst_rom.vhd:232] -INFO: [Synth 8-256] done synthesizing module 'inst_rom' (9#1) [g:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/synth/inst_rom.vhd:68] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port CLKB -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[31] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[30] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[29] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[28] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[27] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[26] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[25] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[24] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[23] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[22] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[21] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[20] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[19] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[18] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[17] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[16] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[15] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[14] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[13] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[12] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[11] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[10] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[9] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[8] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[7] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[6] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[5] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[4] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[3] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[2] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[1] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[0] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port SBITERR_I -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DBITERR_I -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[10] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[9] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[8] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[7] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[6] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[5] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[4] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[3] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[2] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[1] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[0] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port SSRA -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port CLKB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port SSRB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ENB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port REGCEB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port WEB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[10] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[9] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[8] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[7] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[6] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[5] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[4] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[3] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[2] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[1] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ADDRB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[17] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[16] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[15] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[14] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[13] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[12] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[11] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[10] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[9] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[8] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[7] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[6] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[5] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[4] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[3] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[2] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[1] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port DINB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port SLEEP -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port INJECTSBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port INJECTDBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ECCPIPECE -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ram_rstram_b -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ram_rstreg_b -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRA -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port CLKB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ENB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port REGCEB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port WEB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[10] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[9] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[8] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[7] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[6] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[5] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[4] -INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1157.242 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [g:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_ooc.xdc] for cell 'U0' -Finished Parsing XDC File [g:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_ooc.xdc] for cell 'U0' -Parsing XDC File [G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc] -Finished Parsing XDC File [G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc] -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1157.242 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1157.242 ; gain = 0.000 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7k325tffg900-2 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- -Applied set_property DONT_TOUCH = true for U0. (constraint file G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/dont_touch.xdc, line 9). ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:48 ; elapsed = 00:00:50 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 840 (col length:140) -BRAMs: 890 (col length: RAMB18 140 RAMB36 70) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:49 ; elapsed = 00:00:51 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:57 ; elapsed = 00:00:59 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:57 ; elapsed = 00:00:59 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:57 ; elapsed = 00:00:59 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+-----------+------+ -| |Cell |Count | -+------+-----------+------+ -|1 |RAMB36E1 | 1| -|2 |RAMB36E1_1 | 1| -+------+-----------+------+ - -Report Instance Areas: -+------+---------------------------------------------+----------------------------------------------+------+ -| |Instance |Module |Cells | -+------+---------------------------------------------+----------------------------------------------+------+ -|1 |top | | 2| -|2 | U0 |blk_mem_gen_v8_4_4 | 2| -|3 | inst_blk_mem_gen |blk_mem_gen_v8_4_4_synth | 2| -|4 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top | 2| -|5 | \valid.cstr |blk_mem_gen_generic_cstr | 2| -|6 | \ramloop[0].ram.r |blk_mem_gen_prim_width | 1| -|7 | \prim_init.ram |blk_mem_gen_prim_wrapper_init | 1| -|8 | \ramloop[1].ram.r |blk_mem_gen_prim_width__parameterized0 | 1| -|9 | \prim_init.ram |blk_mem_gen_prim_wrapper_init__parameterized0 | 1| -+------+---------------------------------------------+----------------------------------------------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 1157.242 ; gain = 526.562 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 230 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:01:00 . Memory (MB): peak = 1157.242 ; gain = 526.562 -Synthesis Optimization Complete : Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 1157.242 ; gain = 526.562 -INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1157.242 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1157.242 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -17 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:01:06 ; elapsed = 00:01:09 . Memory (MB): peak = 1157.242 ; gain = 856.020 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1157.242 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp' has been generated. -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP inst_rom, cache-ID = 9888347cfb290ede -INFO: [Coretcl 2-1174] Renamed 8 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1157.242 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file inst_rom_utilization_synth.rpt -pb inst_rom_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri Oct 29 14:30:24 2021... diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.sh b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.sh deleted file mode 100644 index bdbe9b3..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=F:/vivado/Vivado/2019.2/ids_lite/ISE/bin/nt64;F:/vivado/Vivado/2019.2/ids_lite/ISE/lib/nt64:F:/vivado/Vivado/2019.2/bin -else - PATH=F:/vivado/Vivado/2019.2/ids_lite/ISE/bin/nt64;F:/vivado/Vivado/2019.2/ids_lite/ISE/lib/nt64:F:/vivado/Vivado/2019.2/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log inst_rom.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_rom.tcl diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/vivado.jou b/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/vivado.jou deleted file mode 100644 index 4aa3a2c..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.2 (64-bit) -# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 -# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 -# Start of session at: Fri Oct 29 14:29:11 2021 -# Process ID: 21032 -# Current directory: G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1 -# Command line: vivado.exe -log inst_rom.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_rom.tcl -# Log file: G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.runs/inst_rom_synth_1/inst_rom.vds -# Journal file: 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zbZ;J{jIQiF`2pdh8lJc(e^P<3&Y@L-&5m-4PbTjcXYZRO8B?#uC|z0?0oj~CkpTlM%>L|T6hTrc>!OqtZ9RQAAP5mX7FbZ#&ne9aLB;_;E~Jfq z9&mTn`v~>!ra?tOf$#BO?sO-{TtEcWcgSxytHbjVAkfsObkX=jcYhV!8knZC$9v(G z4qe}4;phfD4aQ|T>V;i2Rc|eowMfC-RedWkQW4M=B#*wU+V-Csobn8J11PBPAO6Zn zfB#S!>!AVz*2klhD|$$A?wI$Q@(-GOQCrV0+z>kdyO7U7zXWvT4sQCdONnntg3Svg zrTLG`^@_wTYr?j+nR5?rU#*)7Ee>oAyb+lD=_ltghi4)4KG&|EJ$1?CU3aD~_~E8R zGq&?39|a$8)6c{*2kL18HidHVVW=enmC>FmdjX7Rr-I97bK?h?53Bg=Get0UXTI%0 zF;OHwt*?g||QF z+uBd_abm<`TmnM(Vu*G;WP#>NI?cE6`%6EF25wFkbb~95PSZ%mmW6lW?2hz9@;F^r z(;|haKO^op3^9Wx(h)SwC|qU{k{#a=m>Ku45U!{zisAgqiiBq(Mq82C_UmeQ*Mf(A zq0hB1St-c+&WXZ#5Lfd&B(X6vDZwYwk6fE^r71U&&(rV6;LlTPF23fl1>*_rtl8#>UKf8^?mGdS1PXyb`w9 z{&@MTzoE|^-ef+m4>Ugrx2q)&OPF}G6cxMVd{tfk<=&<!jy5>lbsSDerspd5P1_bt#YS_p`6y%M#G_oaw^At|`>I<| zdB-`dtQfcciW%-NalYmSo$jc)Uc$>6ailer7j~v$>JN11cEV9rN$5n6so7d8gtIr0 zQ;w{yf?eTdViDxDSR_EUUtk*8o!huLEW*K~%7)tvy^sX-vj8Y})VbDE*Cx{F3|=#p zBPy2mvK)`iXl$k>doZMPwxJBoc7Ky``0P8YbY{W=E;E*Eh$C1g*rwaDZB|LEIhr+{ zi&L*4TBMb9%X>dud6c1Ox^V6-->0%Kumt};%1VxF>Sb9+vB}-}Ok4pwo;3H$r2kKr M&2WFTj*!9mHx|*1pa1{> diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/compile.bat b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/compile.bat index d63851f..ab8782a 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/compile.bat +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/compile.bat @@ -6,7 +6,7 @@ REM Filename : compile.bat REM Simulator : Xilinx Vivado Simulator REM Description : Script for compiling the simulation design source files REM -REM Generated by Vivado on Fri Oct 29 12:20:13 +0800 2021 +REM Generated by Vivado on Tue Nov 02 23:16:09 +0800 2021 REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 REM REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/compile.log b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/compile.log deleted file mode 100644 index 370669e..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/compile.log +++ /dev/null @@ -1,10 +0,0 @@ -INFO: [VRFC 10-2263] Analyzing Verilog file "F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/data_ram/sim/data_ram.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module data_ram -INFO: [VRFC 10-2263] Analyzing Verilog file "F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/sim/inst_rom.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module inst_rom -INFO: [VRFC 10-2263] Analyzing Verilog file "F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/clkdiv/clkdiv_clk_wiz.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module clkdiv_clk_wiz -INFO: [VRFC 10-2263] Analyzing Verilog file "F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/clkdiv/clkdiv.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module clkdiv -INFO: [VRFC 10-2263] Analyzing Verilog file "F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32_SYS.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module MiniMIPS32_SYS diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/elaborate.bat b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/elaborate.bat index c258528..4debf67 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/elaborate.bat +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/elaborate.bat @@ -6,7 +6,7 @@ REM Filename : elaborate.bat REM Simulator : Xilinx Vivado Simulator REM Description : Script for elaborating the compiled design REM -REM Generated by Vivado on Fri Oct 29 12:20:15 +0800 2021 +REM Generated by Vivado on Tue Nov 02 23:16:12 +0800 2021 REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 REM REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/elaborate.log b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/elaborate.log deleted file mode 100644 index 073aa28..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/elaborate.log +++ /dev/null @@ -1,50 +0,0 @@ -Vivado Simulator 2019.2 -Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved. -Running: E:/xlinx/Vivado/2019.2/bin/unwrapped/win64.o/xelab.exe -wto bb1d9b6b857a46b28863b191d55162ea --incr --debug typical --relax --mt 2 -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot MiniMIPS32_SYS_tb_behav xil_defaultlib.MiniMIPS32_SYS_tb xil_defaultlib.glbl -log elaborate.log -Using 2 slave threads. -Starting static elaboration -Pass Through NonSizing Optimizer -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 11 for port 'addra' [F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32_SYS.v:37] -WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 32 for port 'D1' [F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32.sv:138] -WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 32 for port 'D0' [F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32.sv:139] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'D1' [F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32.sv:152] -WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 32 for port 'D0' [F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32.sv:154] -WARNING: [VRFC 10-3091] actual bit length 64 differs from formal bit length 32 for port 'D0' [F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32.sv:222] -WARNING: [VRFC 10-5021] port 're1' is not connected on this instance [F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/MiniMIPS32.sv:123] -WARNING: [VRFC 10-3823] variable 'sll' might have multiple concurrent drivers [F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/new/dcu.sv:108] -Completed static elaboration -Starting simulation data flow analysis -Completed simulation data flow analysis -Time Resolution for simulation is 1ps -Compiling module unisims_ver.IBUFDS -Compiling module unisims_ver.MMCME2_ADV(CLKIN1_PERIOD=5.0,CLK... -Compiling module unisims_ver.BUFG -Compiling module xil_defaultlib.clkdiv_clk_wiz -Compiling module xil_defaultlib.clkdiv -Compiling module blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_output_stage(... -Compiling module blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_softecc_outpu... -Compiling module blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_mem_module(C_... -Compiling module blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4(C_FAMILY="kin... -Compiling module xil_defaultlib.inst_rom -Compiling module blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_mem_module(C_... -Compiling module blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4(C_FAMILY="kin... -Compiling module xil_defaultlib.data_ram -Compiling module xil_defaultlib.pc_reg -Compiling module xil_defaultlib.mux4(width=32) -Compiling module xil_defaultlib.mux2(width=32) -Compiling module xil_defaultlib.ifid_reg -Compiling module xil_defaultlib.dcu -Compiling module xil_defaultlib.register -Compiling module xil_defaultlib.idexe_reg -Compiling module xil_defaultlib.alu -Compiling module xil_defaultlib.hilo -Compiling module xil_defaultlib.scu -Compiling module xil_defaultlib.mux3(width=32) -Compiling module xil_defaultlib.exemem_reg -Compiling module xil_defaultlib.mcu -Compiling module xil_defaultlib.memwb_reg -Compiling module xil_defaultlib.MiniMIPS32 -Compiling module xil_defaultlib.MiniMIPS32_SYS -Compiling module xil_defaultlib.MiniMIPS32_SYS_tb -Compiling module xil_defaultlib.glbl -Built simulation snapshot MiniMIPS32_SYS_tb_behav diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/simulate.bat b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/simulate.bat index c3a6376..3481572 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/simulate.bat +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/simulate.bat @@ -6,7 +6,7 @@ REM Filename : simulate.bat REM Simulator : Xilinx Vivado Simulator REM Description : Script for simulating the design by launching the simulator REM -REM Generated by Vivado on Fri Oct 29 12:20:21 +0800 2021 +REM Generated by Vivado on Tue Nov 02 23:16:20 +0800 2021 REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 REM REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.jou b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.jou index 9065b5d..add3b5c 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.jou +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.jou @@ -2,8 +2,8 @@ # Webtalk v2019.2 (64-bit) # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 -# Start of session at: Fri Oct 29 12:18:47 2021 -# Process ID: 23084 +# Start of session at: Tue Nov 2 23:19:13 2021 +# Process ID: 26072 # Current directory: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim # Command line: wbtcv.exe -mode batch -source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log index 6e1a36c..9e00253 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log @@ -2,12 +2,12 @@ # Webtalk v2019.2 (64-bit) # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 # IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 -# Start of session at: Fri Oct 29 12:18:47 2021 -# Process ID: 23084 +# Start of session at: Tue Nov 2 23:19:13 2021 +# Process ID: 26072 # Current directory: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim # Command line: wbtcv.exe -mode batch -source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log # Journal file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace -INFO: [Common 17-206] Exiting Webtalk at Fri Oct 29 12:18:47 2021... +INFO: [Common 17-206] Exiting Webtalk at Tue Nov 2 23:19:13 2021... diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_23084.backup.jou b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_23084.backup.jou new file mode 100644 index 0000000..9065b5d --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_23084.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Fri Oct 29 12:18:47 2021 +# Process ID: 23084 +# Current directory: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_23084.backup.log b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_23084.backup.log new file mode 100644 index 0000000..6e1a36c --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_23084.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Fri Oct 29 12:18:47 2021 +# Process ID: 23084 +# Current directory: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Fri Oct 29 12:18:47 2021... diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_26756.backup.jou b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_26756.backup.jou new file mode 100644 index 0000000..16c068c --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_26756.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Tue Nov 2 23:16:20 2021 +# Process ID: 26756 +# Current directory: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_26756.backup.log b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_26756.backup.log new file mode 100644 index 0000000..40d4ab6 --- /dev/null +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk_26756.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Tue Nov 2 23:16:20 2021 +# Process ID: 26756 +# Current directory: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source 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zsd1T9Q?tvi$$%+znZ7Vt_^y29DZ9ti*v9V}VT#_ji?U6T%RFgn_SiLZO^wSeHZ^8rrzvu&k4;g~E()0%mpKKKz0a;W3sdAWmrTuvc8#YoYFwtGA1eDJ zyQr2aa+!vv=3~3YXKGxgovGPx*Yq?sE;G>79I$J$%-?4JyZF5@0;|Etg15b5r9otxXMnn;2FBrU<`h z5@|bVioUYV7pBH#3QY}uNhH$so2hY`E2aj&3lgb`Zi1QhLK{c)MUy~;eA3tgMgOf);IzI6IEN|7oOVhlA z0u`U|-n1j_3GaKQqf!G!GrYG|YUO!o>O&7cHu<4p$*o!&)jTj_rZ>Ucs!b$FPYTSL z=}ig@pNlzf&G*IxexB)_7L~SRpx?VBYRBaq@2jPwd~DwLjJIl~B<)Q}N)CMgjQ2@j ziltI5j;x;)SurIkZO03=Fj$)4@`K@J8;Lb=e(Pu;v(fK$!U=>$?1Wtx!!6! zu(=LVfu-}kv4LwZc&o%EM@mv6t*O4`K%)iT#JI?&Qhkw4CAGrO*(~%{3rt$zeHhpE z*#hr?sMdi7FM1OLnJ;<^t;IVsDSAHh~sPyfyJ( zZI)oK|5@T4kE`#$G_3Alif_%Nqy*M1#Seg{rUniz^|r0uDzbiBtH_g{)~Z#YZor$A zXuSxBC8hd&_N&r}q`;|Z-o`QRvb6NT{D3#LReF-Uyj838|1VnqKarMXT5AU?FY`7W znx69iQru0~O0ClW-@vs0zr!?Nw?$w`--yQ=FEbx})}TZ=+I`lYNmF za&l5qpx?{h`VS;Wp1tJcNLO;QRhwchmJ)esCZ|MR5y`2MJDzUUr>7(b4!rCgosygy z*=1T<eg6mCWZoG7 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/obj/xsim_1.c b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/obj/xsim_1.c index 2f9f25d..192dad2 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/obj/xsim_1.c +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/obj/xsim_1.c @@ -48,21 +48,21 @@ #endif typedef void (*funcp)(char *, char *); extern int main(int, char**); -extern void execute_244(char*, char *); extern void execute_245(char*, char *); extern void execute_246(char*, char *); -extern void execute_855(char*, char *); -extern void execute_856(char*, char *); +extern void execute_247(char*, char *); +extern void execute_863(char*, char *); +extern void execute_864(char*, char *); +extern void execute_865(char*, char *); extern void execute_857(char*, char *); -extern void execute_849(char*, char *); -extern void execute_850(char*, char *); -extern void execute_851(char*, char *); -extern void execute_852(char*, char *); -extern void execute_853(char*, char *); -extern void execute_854(char*, char *); +extern void execute_858(char*, char *); +extern void execute_859(char*, char *); +extern void execute_860(char*, char *); +extern void execute_861(char*, char *); +extern void execute_862(char*, char *); extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); -extern void execute_332(char*, char *); -extern void execute_335(char*, char *); +extern void execute_333(char*, char *); +extern void execute_336(char*, char *); extern void execute_6(char*, char *); extern void execute_7(char*, char *); extern void execute_8(char*, char *); @@ -177,11 +177,10 @@ extern void execute_117(char*, char *); extern void execute_118(char*, char *); extern void execute_119(char*, char *); extern void execute_135(char*, char *); -extern void execute_254(char*, char *); extern void execute_255(char*, char *); -extern void execute_258(char*, char *); +extern void execute_256(char*, char *); extern void execute_259(char*, char *); -extern void execute_271(char*, char *); +extern void execute_260(char*, char *); extern void execute_272(char*, char *); extern void execute_273(char*, char *); extern void execute_274(char*, char *); @@ -239,55 +238,55 @@ extern void execute_325(char*, char *); extern void execute_326(char*, char *); extern void execute_327(char*, char *); extern void execute_328(char*, char *); -extern void execute_468(char*, char *); -extern void execute_474(char*, char *); +extern void execute_329(char*, char *); +extern void execute_469(char*, char *); extern void execute_475(char*, char *); -extern void execute_484(char*, char *); +extern void execute_476(char*, char *); extern void execute_485(char*, char *); extern void execute_486(char*, char *); extern void execute_487(char*, char *); extern void execute_488(char*, char *); -extern void execute_490(char*, char *); -extern void execute_495(char*, char *); +extern void execute_489(char*, char *); +extern void execute_491(char*, char *); extern void execute_496(char*, char *); extern void execute_497(char*, char *); extern void execute_498(char*, char *); extern void execute_499(char*, char *); +extern void execute_500(char*, char *); extern void execute_140(char*, char *); extern void execute_168(char*, char *); -extern void execute_458(char*, char *); extern void execute_459(char*, char *); extern void execute_460(char*, char *); extern void execute_461(char*, char *); extern void execute_462(char*, char *); extern void execute_463(char*, char *); extern void execute_464(char*, char *); +extern void execute_465(char*, char *); extern void execute_149(char*, char *); extern void execute_150(char*, char *); extern void execute_151(char*, char *); extern void execute_165(char*, char *); extern void execute_166(char*, char *); extern void execute_167(char*, char *); -extern void execute_390(char*, char *); extern void execute_391(char*, char *); extern void execute_392(char*, char *); extern void execute_393(char*, char *); extern void execute_394(char*, char *); extern void execute_395(char*, char *); extern void execute_396(char*, char *); -extern void execute_398(char*, char *); +extern void execute_397(char*, char *); extern void execute_399(char*, char *); extern void execute_400(char*, char *); extern void execute_401(char*, char *); -extern void execute_405(char*, char *); -extern void execute_409(char*, char *); +extern void execute_402(char*, char *); +extern void execute_406(char*, char *); extern void execute_410(char*, char *); extern void execute_411(char*, char *); extern void execute_412(char*, char *); extern void execute_413(char*, char *); extern void execute_414(char*, char *); -extern void execute_417(char*, char *); -extern void execute_419(char*, char *); +extern void execute_415(char*, char *); +extern void execute_418(char*, char *); extern void execute_420(char*, char *); extern void execute_421(char*, char *); extern void execute_422(char*, char *); @@ -301,65 +300,65 @@ extern void execute_429(char*, char *); extern void execute_430(char*, char *); extern void execute_431(char*, char *); extern void execute_432(char*, char *); +extern void execute_433(char*, char *); extern void execute_153(char*, char *); extern void execute_154(char*, char *); extern void execute_155(char*, char *); extern void execute_156(char*, char *); -extern void execute_402(char*, char *); extern void execute_403(char*, char *); extern void execute_404(char*, char *); +extern void execute_405(char*, char *); extern void execute_163(char*, char *); extern void execute_164(char*, char *); -extern void execute_633(char*, char *); extern void execute_634(char*, char *); extern void execute_635(char*, char *); -extern void execute_644(char*, char *); +extern void execute_636(char*, char *); extern void execute_645(char*, char *); extern void execute_646(char*, char *); extern void execute_647(char*, char *); extern void execute_648(char*, char *); -extern void execute_650(char*, char *); +extern void execute_649(char*, char *); extern void execute_651(char*, char *); -extern void execute_655(char*, char *); +extern void execute_652(char*, char *); extern void execute_656(char*, char *); extern void execute_657(char*, char *); extern void execute_658(char*, char *); extern void execute_659(char*, char *); +extern void execute_660(char*, char *); extern void execute_171(char*, char *); extern void execute_199(char*, char *); -extern void execute_620(char*, char *); extern void execute_621(char*, char *); extern void execute_622(char*, char *); extern void execute_623(char*, char *); extern void execute_624(char*, char *); extern void execute_625(char*, char *); extern void execute_626(char*, char *); +extern void execute_627(char*, char *); extern void execute_180(char*, char *); extern void execute_181(char*, char *); extern void execute_182(char*, char *); extern void execute_196(char*, char *); extern void execute_197(char*, char *); extern void execute_198(char*, char *); -extern void execute_552(char*, char *); extern void execute_553(char*, char *); extern void execute_554(char*, char *); extern void execute_555(char*, char *); extern void execute_556(char*, char *); extern void execute_557(char*, char *); extern void execute_558(char*, char *); -extern void execute_560(char*, char *); +extern void execute_559(char*, char *); extern void execute_561(char*, char *); extern void execute_562(char*, char *); extern void execute_563(char*, char *); -extern void execute_567(char*, char *); -extern void execute_571(char*, char *); +extern void execute_564(char*, char *); +extern void execute_568(char*, char *); extern void execute_572(char*, char *); extern void execute_573(char*, char *); extern void execute_574(char*, char *); extern void execute_575(char*, char *); extern void execute_576(char*, char *); -extern void execute_579(char*, char *); -extern void execute_581(char*, char *); +extern void execute_577(char*, char *); +extern void execute_580(char*, char *); extern void execute_582(char*, char *); extern void execute_583(char*, char *); extern void execute_584(char*, char *); @@ -373,23 +372,22 @@ extern void execute_591(char*, char *); extern void execute_592(char*, char *); extern void execute_593(char*, char *); extern void execute_594(char*, char *); -extern void execute_217(char*, char *); -extern void execute_223(char*, char *); -extern void execute_664(char*, char *); +extern void execute_595(char*, char *); +extern void execute_218(char*, char *); +extern void execute_224(char*, char *); +extern void execute_665(char*, char *); extern void vlog_simple_process_execute_0_fast_for_reg(char*, char*, char*); -extern void execute_666(char*, char *); extern void execute_667(char*, char *); -extern void execute_670(char*, char *); +extern void execute_668(char*, char *); extern void execute_671(char*, char *); extern void execute_672(char*, char *); extern void execute_673(char*, char *); -extern void execute_720(char*, char *); +extern void execute_674(char*, char *); extern void execute_721(char*, char *); +extern void execute_722(char*, char *); extern void execute_723(char*, char *); -extern void execute_724(char*, char *); -extern void execute_729(char*, char *); -extern void execute_742(char*, char *); -extern void execute_743(char*, char *); +extern void execute_725(char*, char *); +extern void execute_731(char*, char *); extern void execute_744(char*, char *); extern void execute_745(char*, char *); extern void execute_746(char*, char *); @@ -495,12 +493,19 @@ extern void execute_845(char*, char *); extern void execute_846(char*, char *); extern void execute_847(char*, char *); extern void execute_848(char*, char *); +extern void execute_849(char*, char *); +extern void execute_850(char*, char *); +extern void execute_851(char*, char *); +extern void execute_852(char*, char *); +extern void execute_853(char*, char *); +extern void execute_854(char*, char *); +extern void execute_855(char*, char *); +extern void execute_856(char*, char *); extern void execute_202(char*, char *); -extern void execute_204(char*, char *); extern void execute_669(char*, char *); -extern void execute_207(char*, char *); -extern void execute_209(char*, char *); -extern void execute_674(char*, char *); +extern void execute_205(char*, char *); +extern void execute_208(char*, char *); +extern void execute_210(char*, char *); extern void execute_675(char*, char *); extern void execute_676(char*, char *); extern void execute_677(char*, char *); @@ -546,18 +551,17 @@ extern void execute_716(char*, char *); extern void execute_717(char*, char *); extern void execute_718(char*, char *); extern void execute_719(char*, char *); -extern void execute_211(char*, char *); +extern void execute_720(char*, char *); extern void execute_212(char*, char *); extern void execute_213(char*, char *); -extern void execute_225(char*, char *); -extern void execute_227(char*, char *); -extern void execute_229(char*, char *); -extern void execute_231(char*, char *); -extern void execute_233(char*, char *); -extern void execute_238(char*, char *); -extern void execute_240(char*, char *); -extern void execute_731(char*, char *); -extern void execute_732(char*, char *); +extern void execute_214(char*, char *); +extern void execute_226(char*, char *); +extern void execute_228(char*, char *); +extern void execute_230(char*, char *); +extern void execute_232(char*, char *); +extern void execute_234(char*, char *); +extern void execute_239(char*, char *); +extern void execute_241(char*, char *); extern void execute_733(char*, char *); extern void execute_734(char*, char *); extern void execute_735(char*, char *); @@ -566,15 +570,17 @@ extern void execute_737(char*, char *); extern void execute_738(char*, char *); extern void execute_739(char*, char *); extern void execute_740(char*, char *); -extern void execute_242(char*, char *); -extern void execute_248(char*, char *); +extern void execute_741(char*, char *); +extern void execute_742(char*, char *); +extern void execute_243(char*, char *); extern void execute_249(char*, char *); extern void execute_250(char*, char *); -extern void execute_858(char*, char *); -extern void execute_859(char*, char *); -extern void execute_860(char*, char *); -extern void execute_861(char*, char *); -extern void execute_862(char*, char *); +extern void execute_251(char*, char *); +extern void execute_866(char*, char *); +extern void execute_867(char*, char *); +extern void execute_868(char*, char *); +extern void execute_869(char*, char *); +extern void execute_870(char*, char *); extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); extern void transaction_15(char*, char*, unsigned, unsigned, unsigned); extern void transaction_17(char*, char*, unsigned, unsigned, unsigned); @@ -600,16 +606,20 @@ extern void transaction_43(char*, char*, unsigned, unsigned, unsigned); extern void transaction_47(char*, char*, unsigned, unsigned, unsigned); extern void transaction_51(char*, char*, unsigned, unsigned, unsigned); extern void transaction_54(char*, char*, unsigned, unsigned, unsigned); -extern void transaction_1467(char*, char*, unsigned, unsigned, unsigned); -extern void transaction_1471(char*, char*, unsigned, unsigned, unsigned); -extern void transaction_1557(char*, char*, unsigned, unsigned, unsigned); -extern void transaction_1558(char*, char*, unsigned, unsigned, unsigned); -extern void transaction_1561(char*, char*, unsigned, unsigned, unsigned); -extern void transaction_1573(char*, char*, unsigned, unsigned, unsigned); -extern void transaction_1574(char*, char*, unsigned, unsigned, unsigned); -extern void transaction_1577(char*, char*, unsigned, unsigned, unsigned); -extern void transaction_1600(char*, char*, unsigned, unsigned, unsigned); -extern void transaction_1601(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1465(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1469(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1473(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1477(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1484(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1566(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1567(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1570(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1582(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1583(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1586(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1609(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1610(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1615(char*, char*, unsigned, unsigned, unsigned); extern void transaction_211(char*, char*, unsigned, unsigned, unsigned); extern void transaction_212(char*, char*, unsigned, unsigned, unsigned); extern void transaction_288(char*, char*, unsigned, unsigned, unsigned); @@ -617,14 +627,15 @@ extern void transaction_289(char*, char*, unsigned, unsigned, unsigned); extern void transaction_290(char*, char*, unsigned, unsigned, unsigned); extern void transaction_291(char*, char*, unsigned, unsigned, unsigned); extern void transaction_321(char*, char*, unsigned, unsigned, unsigned); -extern void transaction_1400(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_1380(char*, char*, unsigned, unsigned, unsigned); extern void transaction_1401(char*, char*, unsigned, unsigned, unsigned); -funcp funcTab[571] = {(funcp)execute_244, (funcp)execute_245, (funcp)execute_246, (funcp)execute_855, (funcp)execute_856, (funcp)execute_857, (funcp)execute_849, (funcp)execute_850, (funcp)execute_851, (funcp)execute_852, (funcp)execute_853, (funcp)execute_854, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_332, (funcp)execute_335, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)execute_54, (funcp)execute_55, (funcp)execute_56, (funcp)execute_57, (funcp)execute_58, (funcp)execute_59, (funcp)execute_60, (funcp)execute_61, (funcp)execute_62, (funcp)execute_63, (funcp)execute_64, (funcp)execute_65, (funcp)execute_66, (funcp)execute_67, (funcp)execute_68, (funcp)execute_69, (funcp)execute_70, (funcp)execute_71, (funcp)execute_72, (funcp)execute_73, (funcp)execute_74, (funcp)execute_75, (funcp)execute_76, (funcp)execute_77, (funcp)execute_78, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_84, (funcp)execute_85, (funcp)execute_86, (funcp)execute_87, (funcp)execute_88, (funcp)execute_89, (funcp)execute_90, (funcp)execute_91, (funcp)execute_92, (funcp)execute_93, (funcp)execute_94, (funcp)execute_95, (funcp)execute_96, (funcp)execute_97, (funcp)execute_98, (funcp)execute_99, (funcp)execute_100, (funcp)execute_101, (funcp)execute_102, (funcp)execute_103, (funcp)execute_104, (funcp)execute_105, (funcp)execute_106, (funcp)execute_107, (funcp)execute_108, (funcp)execute_109, (funcp)execute_110, (funcp)execute_111, (funcp)execute_112, (funcp)execute_113, (funcp)execute_114, (funcp)execute_115, (funcp)execute_116, (funcp)execute_117, (funcp)execute_118, (funcp)execute_119, (funcp)execute_135, (funcp)execute_254, (funcp)execute_255, (funcp)execute_258, (funcp)execute_259, (funcp)execute_271, (funcp)execute_272, (funcp)execute_273, (funcp)execute_274, (funcp)execute_275, (funcp)execute_276, (funcp)execute_277, (funcp)execute_278, (funcp)execute_279, (funcp)execute_280, (funcp)execute_281, (funcp)execute_282, (funcp)execute_283, (funcp)execute_284, (funcp)execute_285, (funcp)execute_286, (funcp)execute_287, (funcp)execute_288, (funcp)execute_289, (funcp)execute_290, (funcp)execute_291, (funcp)execute_292, (funcp)execute_293, (funcp)execute_294, (funcp)execute_295, (funcp)execute_296, (funcp)execute_297, (funcp)execute_298, (funcp)execute_299, (funcp)execute_300, (funcp)execute_301, (funcp)execute_302, (funcp)execute_303, (funcp)execute_304, (funcp)execute_305, (funcp)execute_306, (funcp)execute_307, (funcp)execute_308, (funcp)execute_309, (funcp)execute_310, (funcp)execute_311, (funcp)execute_312, (funcp)execute_313, (funcp)execute_314, (funcp)execute_315, (funcp)execute_316, (funcp)execute_317, (funcp)execute_318, (funcp)execute_319, (funcp)execute_320, (funcp)execute_321, (funcp)execute_322, (funcp)execute_323, (funcp)execute_324, (funcp)execute_325, (funcp)execute_326, (funcp)execute_327, (funcp)execute_328, (funcp)execute_468, (funcp)execute_474, (funcp)execute_475, (funcp)execute_484, (funcp)execute_485, (funcp)execute_486, (funcp)execute_487, (funcp)execute_488, (funcp)execute_490, (funcp)execute_495, (funcp)execute_496, (funcp)execute_497, (funcp)execute_498, (funcp)execute_499, (funcp)execute_140, (funcp)execute_168, (funcp)execute_458, (funcp)execute_459, (funcp)execute_460, (funcp)execute_461, (funcp)execute_462, (funcp)execute_463, (funcp)execute_464, (funcp)execute_149, (funcp)execute_150, (funcp)execute_151, (funcp)execute_165, (funcp)execute_166, (funcp)execute_167, (funcp)execute_390, (funcp)execute_391, (funcp)execute_392, (funcp)execute_393, (funcp)execute_394, (funcp)execute_395, (funcp)execute_396, (funcp)execute_398, (funcp)execute_399, (funcp)execute_400, (funcp)execute_401, (funcp)execute_405, (funcp)execute_409, (funcp)execute_410, (funcp)execute_411, (funcp)execute_412, (funcp)execute_413, (funcp)execute_414, (funcp)execute_417, (funcp)execute_419, (funcp)execute_420, (funcp)execute_421, (funcp)execute_422, (funcp)execute_423, (funcp)execute_424, (funcp)execute_425, (funcp)execute_426, (funcp)execute_427, (funcp)execute_428, (funcp)execute_429, (funcp)execute_430, (funcp)execute_431, (funcp)execute_432, (funcp)execute_153, (funcp)execute_154, (funcp)execute_155, (funcp)execute_156, (funcp)execute_402, (funcp)execute_403, (funcp)execute_404, (funcp)execute_163, (funcp)execute_164, (funcp)execute_633, (funcp)execute_634, (funcp)execute_635, (funcp)execute_644, (funcp)execute_645, (funcp)execute_646, (funcp)execute_647, (funcp)execute_648, (funcp)execute_650, (funcp)execute_651, (funcp)execute_655, (funcp)execute_656, (funcp)execute_657, (funcp)execute_658, (funcp)execute_659, (funcp)execute_171, (funcp)execute_199, (funcp)execute_620, (funcp)execute_621, (funcp)execute_622, (funcp)execute_623, (funcp)execute_624, (funcp)execute_625, (funcp)execute_626, (funcp)execute_180, (funcp)execute_181, (funcp)execute_182, (funcp)execute_196, (funcp)execute_197, (funcp)execute_198, (funcp)execute_552, (funcp)execute_553, (funcp)execute_554, (funcp)execute_555, (funcp)execute_556, (funcp)execute_557, (funcp)execute_558, (funcp)execute_560, (funcp)execute_561, (funcp)execute_562, (funcp)execute_563, (funcp)execute_567, (funcp)execute_571, (funcp)execute_572, (funcp)execute_573, (funcp)execute_574, (funcp)execute_575, (funcp)execute_576, (funcp)execute_579, (funcp)execute_581, (funcp)execute_582, (funcp)execute_583, (funcp)execute_584, (funcp)execute_585, (funcp)execute_586, (funcp)execute_587, (funcp)execute_588, (funcp)execute_589, (funcp)execute_590, (funcp)execute_591, (funcp)execute_592, (funcp)execute_593, (funcp)execute_594, (funcp)execute_217, (funcp)execute_223, (funcp)execute_664, (funcp)vlog_simple_process_execute_0_fast_for_reg, (funcp)execute_666, (funcp)execute_667, (funcp)execute_670, (funcp)execute_671, (funcp)execute_672, (funcp)execute_673, (funcp)execute_720, (funcp)execute_721, (funcp)execute_723, (funcp)execute_724, (funcp)execute_729, (funcp)execute_742, (funcp)execute_743, (funcp)execute_744, (funcp)execute_745, (funcp)execute_746, (funcp)execute_747, (funcp)execute_748, (funcp)execute_749, (funcp)execute_750, (funcp)execute_751, (funcp)execute_752, (funcp)execute_753, (funcp)execute_754, (funcp)execute_755, (funcp)execute_756, (funcp)execute_757, (funcp)execute_758, (funcp)execute_759, (funcp)execute_760, (funcp)execute_761, (funcp)execute_762, (funcp)execute_763, (funcp)execute_764, (funcp)execute_765, (funcp)execute_766, (funcp)execute_767, (funcp)execute_768, (funcp)execute_769, (funcp)execute_770, (funcp)execute_771, (funcp)execute_772, (funcp)execute_773, (funcp)execute_774, (funcp)execute_775, (funcp)execute_776, (funcp)execute_777, (funcp)execute_778, (funcp)execute_779, (funcp)execute_780, (funcp)execute_781, (funcp)execute_782, (funcp)execute_783, (funcp)execute_784, (funcp)execute_785, (funcp)execute_786, (funcp)execute_787, (funcp)execute_788, (funcp)execute_789, (funcp)execute_790, (funcp)execute_791, (funcp)execute_792, (funcp)execute_793, (funcp)execute_794, (funcp)execute_795, (funcp)execute_796, (funcp)execute_797, (funcp)execute_798, (funcp)execute_799, (funcp)execute_800, (funcp)execute_801, (funcp)execute_802, (funcp)execute_803, (funcp)execute_804, (funcp)execute_805, (funcp)execute_806, (funcp)execute_807, (funcp)execute_808, (funcp)execute_809, (funcp)execute_810, (funcp)execute_811, (funcp)execute_812, (funcp)execute_813, (funcp)execute_814, (funcp)execute_815, (funcp)execute_816, (funcp)execute_817, (funcp)execute_818, (funcp)execute_819, (funcp)execute_820, (funcp)execute_821, (funcp)execute_822, (funcp)execute_823, (funcp)execute_824, (funcp)execute_825, (funcp)execute_826, (funcp)execute_827, (funcp)execute_828, (funcp)execute_829, (funcp)execute_830, (funcp)execute_831, (funcp)execute_832, (funcp)execute_833, (funcp)execute_834, (funcp)execute_835, (funcp)execute_836, (funcp)execute_837, (funcp)execute_838, (funcp)execute_839, (funcp)execute_840, (funcp)execute_841, (funcp)execute_842, (funcp)execute_843, (funcp)execute_844, (funcp)execute_845, (funcp)execute_846, (funcp)execute_847, (funcp)execute_848, (funcp)execute_202, (funcp)execute_204, (funcp)execute_669, (funcp)execute_207, (funcp)execute_209, (funcp)execute_674, (funcp)execute_675, (funcp)execute_676, (funcp)execute_677, (funcp)execute_678, (funcp)execute_679, (funcp)execute_680, (funcp)execute_681, (funcp)execute_682, (funcp)execute_683, (funcp)execute_684, (funcp)execute_685, (funcp)execute_686, (funcp)execute_687, (funcp)execute_688, (funcp)execute_689, (funcp)execute_690, (funcp)execute_691, (funcp)execute_692, (funcp)execute_693, (funcp)execute_694, (funcp)execute_695, (funcp)execute_696, (funcp)execute_697, (funcp)execute_698, (funcp)execute_699, (funcp)execute_700, (funcp)execute_701, (funcp)execute_702, (funcp)execute_703, (funcp)execute_704, (funcp)execute_705, (funcp)execute_706, (funcp)execute_707, (funcp)execute_708, (funcp)execute_709, (funcp)execute_710, (funcp)execute_711, (funcp)execute_712, (funcp)execute_713, (funcp)execute_714, (funcp)execute_715, (funcp)execute_716, (funcp)execute_717, (funcp)execute_718, (funcp)execute_719, (funcp)execute_211, (funcp)execute_212, (funcp)execute_213, (funcp)execute_225, (funcp)execute_227, (funcp)execute_229, (funcp)execute_231, (funcp)execute_233, (funcp)execute_238, (funcp)execute_240, (funcp)execute_731, (funcp)execute_732, (funcp)execute_733, (funcp)execute_734, (funcp)execute_735, (funcp)execute_736, (funcp)execute_737, (funcp)execute_738, (funcp)execute_739, (funcp)execute_740, (funcp)execute_242, (funcp)execute_248, (funcp)execute_249, (funcp)execute_250, (funcp)execute_858, (funcp)execute_859, (funcp)execute_860, (funcp)execute_861, (funcp)execute_862, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_15, (funcp)transaction_17, (funcp)transaction_24, (funcp)transaction_25, (funcp)transaction_26, (funcp)transaction_27, (funcp)transaction_28, (funcp)transaction_30, (funcp)transaction_31, (funcp)transaction_32, (funcp)transaction_33, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_37, (funcp)transaction_38, (funcp)transaction_39, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43, (funcp)transaction_47, (funcp)transaction_51, (funcp)transaction_54, (funcp)transaction_1467, (funcp)transaction_1471, (funcp)transaction_1557, (funcp)transaction_1558, (funcp)transaction_1561, (funcp)transaction_1573, (funcp)transaction_1574, (funcp)transaction_1577, (funcp)transaction_1600, (funcp)transaction_1601, (funcp)transaction_211, (funcp)transaction_212, (funcp)transaction_288, (funcp)transaction_289, (funcp)transaction_290, (funcp)transaction_291, (funcp)transaction_321, (funcp)transaction_1400, (funcp)transaction_1401}; -const int NumRelocateId= 571; +extern void transaction_1402(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[582] = {(funcp)execute_245, (funcp)execute_246, (funcp)execute_247, (funcp)execute_863, (funcp)execute_864, (funcp)execute_865, (funcp)execute_857, (funcp)execute_858, (funcp)execute_859, (funcp)execute_860, (funcp)execute_861, (funcp)execute_862, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_333, (funcp)execute_336, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)execute_54, (funcp)execute_55, (funcp)execute_56, (funcp)execute_57, (funcp)execute_58, (funcp)execute_59, (funcp)execute_60, (funcp)execute_61, (funcp)execute_62, (funcp)execute_63, (funcp)execute_64, (funcp)execute_65, (funcp)execute_66, (funcp)execute_67, (funcp)execute_68, (funcp)execute_69, (funcp)execute_70, (funcp)execute_71, (funcp)execute_72, (funcp)execute_73, (funcp)execute_74, (funcp)execute_75, (funcp)execute_76, (funcp)execute_77, (funcp)execute_78, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_84, (funcp)execute_85, (funcp)execute_86, (funcp)execute_87, (funcp)execute_88, (funcp)execute_89, (funcp)execute_90, (funcp)execute_91, (funcp)execute_92, (funcp)execute_93, (funcp)execute_94, (funcp)execute_95, (funcp)execute_96, (funcp)execute_97, (funcp)execute_98, (funcp)execute_99, (funcp)execute_100, (funcp)execute_101, (funcp)execute_102, (funcp)execute_103, (funcp)execute_104, (funcp)execute_105, (funcp)execute_106, (funcp)execute_107, (funcp)execute_108, (funcp)execute_109, (funcp)execute_110, (funcp)execute_111, (funcp)execute_112, (funcp)execute_113, (funcp)execute_114, (funcp)execute_115, (funcp)execute_116, (funcp)execute_117, (funcp)execute_118, (funcp)execute_119, (funcp)execute_135, (funcp)execute_255, (funcp)execute_256, (funcp)execute_259, (funcp)execute_260, (funcp)execute_272, (funcp)execute_273, (funcp)execute_274, (funcp)execute_275, (funcp)execute_276, (funcp)execute_277, (funcp)execute_278, (funcp)execute_279, (funcp)execute_280, (funcp)execute_281, (funcp)execute_282, (funcp)execute_283, (funcp)execute_284, (funcp)execute_285, (funcp)execute_286, (funcp)execute_287, (funcp)execute_288, (funcp)execute_289, (funcp)execute_290, (funcp)execute_291, (funcp)execute_292, (funcp)execute_293, (funcp)execute_294, (funcp)execute_295, (funcp)execute_296, (funcp)execute_297, (funcp)execute_298, (funcp)execute_299, (funcp)execute_300, (funcp)execute_301, (funcp)execute_302, (funcp)execute_303, (funcp)execute_304, (funcp)execute_305, (funcp)execute_306, (funcp)execute_307, (funcp)execute_308, (funcp)execute_309, (funcp)execute_310, (funcp)execute_311, (funcp)execute_312, (funcp)execute_313, (funcp)execute_314, (funcp)execute_315, (funcp)execute_316, (funcp)execute_317, (funcp)execute_318, (funcp)execute_319, (funcp)execute_320, (funcp)execute_321, (funcp)execute_322, (funcp)execute_323, (funcp)execute_324, (funcp)execute_325, (funcp)execute_326, (funcp)execute_327, (funcp)execute_328, (funcp)execute_329, (funcp)execute_469, (funcp)execute_475, (funcp)execute_476, (funcp)execute_485, (funcp)execute_486, (funcp)execute_487, (funcp)execute_488, (funcp)execute_489, (funcp)execute_491, (funcp)execute_496, (funcp)execute_497, (funcp)execute_498, (funcp)execute_499, (funcp)execute_500, (funcp)execute_140, (funcp)execute_168, (funcp)execute_459, (funcp)execute_460, (funcp)execute_461, (funcp)execute_462, (funcp)execute_463, (funcp)execute_464, (funcp)execute_465, (funcp)execute_149, (funcp)execute_150, (funcp)execute_151, (funcp)execute_165, (funcp)execute_166, (funcp)execute_167, (funcp)execute_391, (funcp)execute_392, (funcp)execute_393, (funcp)execute_394, (funcp)execute_395, (funcp)execute_396, (funcp)execute_397, (funcp)execute_399, (funcp)execute_400, (funcp)execute_401, (funcp)execute_402, (funcp)execute_406, (funcp)execute_410, (funcp)execute_411, (funcp)execute_412, (funcp)execute_413, (funcp)execute_414, (funcp)execute_415, (funcp)execute_418, (funcp)execute_420, (funcp)execute_421, (funcp)execute_422, (funcp)execute_423, (funcp)execute_424, (funcp)execute_425, (funcp)execute_426, (funcp)execute_427, (funcp)execute_428, (funcp)execute_429, (funcp)execute_430, (funcp)execute_431, (funcp)execute_432, (funcp)execute_433, (funcp)execute_153, (funcp)execute_154, (funcp)execute_155, (funcp)execute_156, (funcp)execute_403, (funcp)execute_404, (funcp)execute_405, (funcp)execute_163, (funcp)execute_164, (funcp)execute_634, (funcp)execute_635, (funcp)execute_636, (funcp)execute_645, (funcp)execute_646, (funcp)execute_647, (funcp)execute_648, (funcp)execute_649, (funcp)execute_651, (funcp)execute_652, (funcp)execute_656, (funcp)execute_657, (funcp)execute_658, (funcp)execute_659, (funcp)execute_660, (funcp)execute_171, (funcp)execute_199, (funcp)execute_621, (funcp)execute_622, (funcp)execute_623, (funcp)execute_624, (funcp)execute_625, (funcp)execute_626, (funcp)execute_627, (funcp)execute_180, (funcp)execute_181, (funcp)execute_182, (funcp)execute_196, (funcp)execute_197, (funcp)execute_198, (funcp)execute_553, (funcp)execute_554, (funcp)execute_555, (funcp)execute_556, (funcp)execute_557, (funcp)execute_558, (funcp)execute_559, (funcp)execute_561, (funcp)execute_562, (funcp)execute_563, (funcp)execute_564, (funcp)execute_568, (funcp)execute_572, (funcp)execute_573, (funcp)execute_574, (funcp)execute_575, (funcp)execute_576, (funcp)execute_577, (funcp)execute_580, (funcp)execute_582, (funcp)execute_583, (funcp)execute_584, (funcp)execute_585, (funcp)execute_586, (funcp)execute_587, (funcp)execute_588, (funcp)execute_589, (funcp)execute_590, (funcp)execute_591, (funcp)execute_592, (funcp)execute_593, (funcp)execute_594, (funcp)execute_595, (funcp)execute_218, (funcp)execute_224, (funcp)execute_665, (funcp)vlog_simple_process_execute_0_fast_for_reg, (funcp)execute_667, (funcp)execute_668, (funcp)execute_671, (funcp)execute_672, (funcp)execute_673, (funcp)execute_674, (funcp)execute_721, (funcp)execute_722, (funcp)execute_723, (funcp)execute_725, (funcp)execute_731, (funcp)execute_744, (funcp)execute_745, (funcp)execute_746, (funcp)execute_747, (funcp)execute_748, (funcp)execute_749, (funcp)execute_750, (funcp)execute_751, (funcp)execute_752, (funcp)execute_753, (funcp)execute_754, (funcp)execute_755, (funcp)execute_756, (funcp)execute_757, (funcp)execute_758, (funcp)execute_759, (funcp)execute_760, (funcp)execute_761, (funcp)execute_762, (funcp)execute_763, (funcp)execute_764, (funcp)execute_765, (funcp)execute_766, (funcp)execute_767, (funcp)execute_768, (funcp)execute_769, (funcp)execute_770, (funcp)execute_771, (funcp)execute_772, (funcp)execute_773, (funcp)execute_774, (funcp)execute_775, (funcp)execute_776, (funcp)execute_777, (funcp)execute_778, (funcp)execute_779, (funcp)execute_780, (funcp)execute_781, (funcp)execute_782, (funcp)execute_783, (funcp)execute_784, (funcp)execute_785, (funcp)execute_786, (funcp)execute_787, (funcp)execute_788, (funcp)execute_789, (funcp)execute_790, (funcp)execute_791, (funcp)execute_792, (funcp)execute_793, (funcp)execute_794, (funcp)execute_795, (funcp)execute_796, (funcp)execute_797, (funcp)execute_798, (funcp)execute_799, (funcp)execute_800, (funcp)execute_801, (funcp)execute_802, (funcp)execute_803, (funcp)execute_804, (funcp)execute_805, (funcp)execute_806, (funcp)execute_807, (funcp)execute_808, (funcp)execute_809, (funcp)execute_810, (funcp)execute_811, (funcp)execute_812, (funcp)execute_813, (funcp)execute_814, (funcp)execute_815, (funcp)execute_816, (funcp)execute_817, (funcp)execute_818, (funcp)execute_819, (funcp)execute_820, (funcp)execute_821, (funcp)execute_822, (funcp)execute_823, (funcp)execute_824, (funcp)execute_825, (funcp)execute_826, (funcp)execute_827, (funcp)execute_828, (funcp)execute_829, (funcp)execute_830, (funcp)execute_831, (funcp)execute_832, (funcp)execute_833, (funcp)execute_834, (funcp)execute_835, (funcp)execute_836, (funcp)execute_837, (funcp)execute_838, (funcp)execute_839, (funcp)execute_840, (funcp)execute_841, (funcp)execute_842, (funcp)execute_843, (funcp)execute_844, (funcp)execute_845, (funcp)execute_846, (funcp)execute_847, (funcp)execute_848, (funcp)execute_849, (funcp)execute_850, (funcp)execute_851, (funcp)execute_852, (funcp)execute_853, (funcp)execute_854, (funcp)execute_855, (funcp)execute_856, (funcp)execute_202, (funcp)execute_669, (funcp)execute_205, (funcp)execute_208, (funcp)execute_210, (funcp)execute_675, (funcp)execute_676, (funcp)execute_677, (funcp)execute_678, (funcp)execute_679, (funcp)execute_680, (funcp)execute_681, (funcp)execute_682, (funcp)execute_683, (funcp)execute_684, (funcp)execute_685, (funcp)execute_686, (funcp)execute_687, (funcp)execute_688, (funcp)execute_689, (funcp)execute_690, (funcp)execute_691, (funcp)execute_692, (funcp)execute_693, (funcp)execute_694, (funcp)execute_695, (funcp)execute_696, (funcp)execute_697, (funcp)execute_698, (funcp)execute_699, (funcp)execute_700, (funcp)execute_701, (funcp)execute_702, (funcp)execute_703, (funcp)execute_704, (funcp)execute_705, (funcp)execute_706, (funcp)execute_707, (funcp)execute_708, (funcp)execute_709, (funcp)execute_710, (funcp)execute_711, (funcp)execute_712, (funcp)execute_713, (funcp)execute_714, (funcp)execute_715, (funcp)execute_716, (funcp)execute_717, (funcp)execute_718, (funcp)execute_719, (funcp)execute_720, (funcp)execute_212, (funcp)execute_213, (funcp)execute_214, (funcp)execute_226, (funcp)execute_228, (funcp)execute_230, (funcp)execute_232, (funcp)execute_234, (funcp)execute_239, (funcp)execute_241, (funcp)execute_733, (funcp)execute_734, (funcp)execute_735, (funcp)execute_736, (funcp)execute_737, (funcp)execute_738, (funcp)execute_739, (funcp)execute_740, (funcp)execute_741, (funcp)execute_742, (funcp)execute_243, (funcp)execute_249, (funcp)execute_250, (funcp)execute_251, (funcp)execute_866, (funcp)execute_867, (funcp)execute_868, (funcp)execute_869, (funcp)execute_870, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_15, (funcp)transaction_17, (funcp)transaction_24, (funcp)transaction_25, (funcp)transaction_26, (funcp)transaction_27, (funcp)transaction_28, (funcp)transaction_30, (funcp)transaction_31, (funcp)transaction_32, (funcp)transaction_33, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_37, (funcp)transaction_38, (funcp)transaction_39, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43, (funcp)transaction_47, (funcp)transaction_51, (funcp)transaction_54, (funcp)transaction_1465, (funcp)transaction_1469, (funcp)transaction_1473, (funcp)transaction_1477, (funcp)transaction_1484, (funcp)transaction_1566, (funcp)transaction_1567, (funcp)transaction_1570, (funcp)transaction_1582, (funcp)transaction_1583, (funcp)transaction_1586, (funcp)transaction_1609, (funcp)transaction_1610, (funcp)transaction_1615, (funcp)transaction_211, (funcp)transaction_212, (funcp)transaction_288, (funcp)transaction_289, (funcp)transaction_290, (funcp)transaction_291, (funcp)transaction_321, (funcp)transaction_1380, (funcp)transaction_1401, (funcp)transaction_1402}; +const int NumRelocateId= 582; void relocate(char *dp) { - iki_relocate(dp, "xsim.dir/MiniMIPS32_SYS_tb_behav/xsim.reloc", (void **)funcTab, 571); + iki_relocate(dp, "xsim.dir/MiniMIPS32_SYS_tb_behav/xsim.reloc", (void **)funcTab, 582); /*Populate the transaction function pointer field in the whole net structure */ } diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/obj/xsim_1.win64.obj b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/obj/xsim_1.win64.obj index cbc930739a8c2c16df2021fd9691de2d62b5b12e..db4c20f4871772f398098805bd7a9b48f365f336 100644 GIT binary patch delta 2162 zcmZXSU1$_n6vyw()DOf}6OxTJN}{QWLO0&IGxyG2TWeICX9;W9@5vd{rhL@w%p42miD9(`t<#Mk;WAoDjeuaMDN;~%yRnYPx6 zcu_Yh+JwwbWWGUW6q#eloMEaCSJuAjG-&lNK+BAgCcQ2%Q7hQ8Edp|nLBO1Y%&2$;-mTp}YkX%l|Wr43Fg zyvub!DxWcI!C^Gt55MKNYYsFPHo!4=u_j=5p*Il@V4D&y6fPRJWx-eO7jWE78aCzd zliLBmxGlOR;4gRM3Omda+?*Rza0cDQv>^nAZ;Ksps+chZb6~pI59^0}b)JUu@P>3*Q#%lS+f1!M`Jokq$!jZ17TWyR;Z~cuO<} zySx^S!=ACE58l&H;O;;VoE>O47-ev()beR0h(>};>i=9?s~ZlZ@Xw(&Uz=etW09YU zMc%P!IH<)U9C_CYcgJiKyfM#k)N{;hHkfU}%-HJ9EV5H6!YnDmMM)9nN)h&y4)uBY zv^K#>r94zRJe03^2TNH~{aa$fvEsss32E00u4bug%GE&i!lAPwJDbZTiF|90%|>t7d=P#8S6h!Q4iHokFx@AUZ0@Atm*do#~|Nq?6m zXXtJ|$*g8CA;FZhLVBF?Rup|NBIKllklxabhonB$eMTxzP1iV9ic=q|cNCWp^5S^v zkH_7f-q}|pX>UAxd*w*eLcOU<%llxY_>EL=HkEvInWNr|Qr=?v=z8> z5mZ&p{1G^sr?4%enr7SkY;@NQB_PpRq-7u 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b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/xsimSettings.ini index 2479757..396d18a 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/xsimSettings.ini +++ b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/xsimSettings.ini @@ -28,7 +28,7 @@ VARIABLE_PROTOINST_FILTER=true SCOPE_NAME_COLUMN_WIDTH=166 SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 -OBJECT_NAME_COLUMN_WIDTH=178 +OBJECT_NAME_COLUMN_WIDTH=75 OBJECT_VALUE_COLUMN_WIDTH=75 OBJECT_DATA_TYPE_COLUMN_WIDTH=75 PROCESS_NAME_COLUMN_WIDTH=75 diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/xsimk.exe b/CPU_core/MiniMIPS32/MiniMIPS32.sim/sim_1/behav/xsim/xsim.dir/MiniMIPS32_SYS_tb_behav/xsimk.exe index 07d37b779d7e716a6bb31695115c0fd09a6ea204..19d3781915e4791ff7df45f7b792e4da540d1a8b 100644 GIT binary patch delta 184852 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a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xci b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xci index de07a1e..d793748 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xci +++ b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xci @@ -172,7 +172,7 @@ false 9 NONE - ../../../../../../TEMU/mips_sc/build/add_inst.coe + c:/Users/13428/Desktop/add_inst.coe ALL inst_rom false diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xml b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xml index 24a63d2..f2c8b22 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xml +++ b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom.xml @@ -1457,11 +1457,11 @@ GENtimestamp - Fri Oct 29 06:29:05 UTC 2021 + Tue Nov 02 15:18:57 UTC 2021 outputProductCRC - 9:a14cffd6 + 9:e022be61 @@ -1477,11 +1477,11 @@ GENtimestamp - Fri Oct 29 06:29:05 UTC 2021 + Tue Nov 02 15:18:57 UTC 2021 outputProductCRC - 9:a14cffd6 + 9:e022be61 @@ -1492,7 +1492,7 @@ outputProductCRC - 9:a14cffd6 + 9:e022be61 @@ -1508,104 +1508,100 @@ GENtimestamp - Fri Oct 29 06:29:05 UTC 2021 + Tue Nov 02 15:18:57 UTC 2021 outputProductCRC - 9:a14cffd6 + 9:e022be61 - xilinx_project_archive - Miscellaneous - :vivado.xilinx.com:misc.files + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + blk_mem_gen_v8_4_4 - xilinx_project_archive_view_fileset + xilinx_anylanguagebehavioralsimulation_view_fileset GENtimestamp - Fri Oct 29 06:29:05 UTC 2021 + Tue Nov 02 15:18:57 UTC 2021 outputProductCRC - 9:a14cffd6 + 9:e0c6f757 - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + inst_rom - xilinx_versioninformation_view_fileset + xilinx_verilogsimulationwrapper_view_fileset GENtimestamp - Fri Oct 29 06:29:05 UTC 2021 + Tue Nov 02 15:18:57 UTC 2021 outputProductCRC - 9:a14cffd6 + 9:e0c6f757 - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files + xilinx_project_archive + Miscellaneous + :vivado.xilinx.com:misc.files - xilinx_externalfiles_view_fileset + xilinx_project_archive_view_fileset GENtimestamp - Fri Oct 29 06:30:24 UTC 2021 + Tue Nov 02 15:18:57 UTC 2021 outputProductCRC - 9:a14cffd6 + 9:e022be61 - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - blk_mem_gen_v8_4_4 + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo - xilinx_anylanguagebehavioralsimulation_view_fileset + xilinx_versioninformation_view_fileset GENtimestamp - Sat Oct 30 13:48:40 UTC 2021 + Tue Nov 02 15:18:57 UTC 2021 outputProductCRC - 9:bf7da351 + 9:e022be61 - xilinx_verilogsimulationwrapper - Verilog Simulation Wrapper - verilogSource:vivado.xilinx.com:simulation.wrapper - verilog - inst_rom + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files - xilinx_verilogsimulationwrapper_view_fileset + xilinx_externalfiles_view_fileset - - GENtimestamp - Sat Oct 30 13:48:40 UTC 2021 - outputProductCRC - 9:bf7da351 + 9:e022be61 @@ -3580,6 +3576,28 @@ xil_defaultlib + + xilinx_anylanguagebehavioralsimulation_view_fileset + + inst_rom.mif + mif + + + simulation/blk_mem_gen_v8_4.v + verilogSource + USED_IN_ipstatic + blk_mem_gen_v8_4_4 + blk_mem_gen_v8_4_4 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/inst_rom.v + verilogSource + xil_defaultlib + + xilinx_project_archive_view_fileset @@ -3622,29 +3640,15 @@ inst_rom_sim_netlist.v verilogSource - USED_IN_synth_blackbox_stub + USED_IN_simulation + USED_IN_single_language xil_defaultlib - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - inst_rom.mif - mif - - simulation/blk_mem_gen_v8_4.v - verilogSource - USED_IN_ipstatic - blk_mem_gen_v8_4_4 - blk_mem_gen_v8_4_4 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/inst_rom.v - verilogSource + inst_rom_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language xil_defaultlib @@ -4137,7 +4141,7 @@ Coe_File - ../../../../../../TEMU/mips_sc/build/add_inst.coe + c:/Users/13428/Desktop/add_inst.coe diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.v b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.v deleted file mode 100644 index 89671fe..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.v +++ /dev/null @@ -1,1148 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 -<<<<<<< HEAD -// Date : Fri Oct 29 14:30:24 2021 -// Host : LAPTOP-M01GHSS7 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.v -======= -// Date : Fri Oct 29 12:20:53 2021 -// Host : DESKTOP-B2469GJ running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.v ->>>>>>> 0267f8d2796d4dcfb8ccf16deb9b3341e76dfafa -// Design : inst_rom -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7k325tffg900-2 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* CHECK_LICENSE_TYPE = "inst_rom,blk_mem_gen_v8_4_4,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2019.2" *) -(* NotValidForBitStream *) -module inst_rom - (clka, - ena, - addra, - douta); - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clka; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [10:0]addra; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [31:0]douta; - - wire [10:0]addra; - wire clka; - wire [31:0]douta; - wire ena; - wire NLW_U0_dbiterr_UNCONNECTED; - wire NLW_U0_rsta_busy_UNCONNECTED; - wire NLW_U0_rstb_busy_UNCONNECTED; - wire NLW_U0_s_axi_arready_UNCONNECTED; - wire NLW_U0_s_axi_awready_UNCONNECTED; - wire NLW_U0_s_axi_bvalid_UNCONNECTED; - wire NLW_U0_s_axi_dbiterr_UNCONNECTED; - wire NLW_U0_s_axi_rlast_UNCONNECTED; - wire NLW_U0_s_axi_rvalid_UNCONNECTED; - wire NLW_U0_s_axi_sbiterr_UNCONNECTED; - wire NLW_U0_s_axi_wready_UNCONNECTED; - wire NLW_U0_sbiterr_UNCONNECTED; - wire [31:0]NLW_U0_doutb_UNCONNECTED; - wire [10:0]NLW_U0_rdaddrecc_UNCONNECTED; - wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED; - wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; - wire [10:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED; - wire [31:0]NLW_U0_s_axi_rdata_UNCONNECTED; - wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED; - wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; - - (* C_ADDRA_WIDTH = "11" *) - (* C_ADDRB_WIDTH = "11" *) - (* C_ALGORITHM = "1" *) - (* C_AXI_ID_WIDTH = "4" *) - (* C_AXI_SLAVE_TYPE = "0" *) - (* C_AXI_TYPE = "1" *) - (* C_BYTE_SIZE = "9" *) - (* C_COMMON_CLK = "0" *) - (* C_COUNT_18K_BRAM = "0" *) - (* C_COUNT_36K_BRAM = "2" *) - (* C_CTRL_ECC_ALGO = "NONE" *) - (* C_DEFAULT_DATA = "0" *) - (* C_DISABLE_WARN_BHV_COLL = "0" *) - (* C_DISABLE_WARN_BHV_RANGE = "0" *) - (* C_ELABORATION_DIR = "./" *) - (* C_ENABLE_32BIT_ADDRESS = "0" *) - (* C_EN_DEEPSLEEP_PIN = "0" *) - (* C_EN_ECC_PIPE = "0" *) - (* C_EN_RDADDRA_CHG = "0" *) - (* C_EN_RDADDRB_CHG = "0" *) - (* C_EN_SAFETY_CKT = "0" *) - (* C_EN_SHUTDOWN_PIN = "0" *) - (* C_EN_SLEEP_PIN = "0" *) - (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 4.8711 mW" *) - (* C_FAMILY = "kintex7" *) - (* C_HAS_AXI_ID = "0" *) - (* C_HAS_ENA = "1" *) - (* C_HAS_ENB = "0" *) - (* C_HAS_INJECTERR = "0" *) - (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) - (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) - (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) - (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) - (* C_HAS_REGCEA = "0" *) - (* C_HAS_REGCEB = "0" *) - (* C_HAS_RSTA = "0" *) - (* C_HAS_RSTB = "0" *) - (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) - (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) - (* C_INITA_VAL = "0" *) - (* C_INITB_VAL = "0" *) - (* C_INIT_FILE = "inst_rom.mem" *) - (* C_INIT_FILE_NAME = "inst_rom.mif" *) - (* C_INTERFACE_TYPE = "0" *) - (* C_LOAD_INIT_FILE = "1" *) - (* C_MEM_TYPE = "3" *) - (* C_MUX_PIPELINE_STAGES = "0" *) - (* C_PRIM_TYPE = "1" *) - (* C_READ_DEPTH_A = "2048" *) - (* C_READ_DEPTH_B = "2048" *) - (* C_READ_LATENCY_A = "1" *) - (* C_READ_LATENCY_B = "1" *) - (* C_READ_WIDTH_A = "32" *) - (* C_READ_WIDTH_B = "32" *) - (* C_RSTRAM_A = "0" *) - (* C_RSTRAM_B = "0" *) - (* C_RST_PRIORITY_A = "CE" *) - (* C_RST_PRIORITY_B = "CE" *) - (* C_SIM_COLLISION_CHECK = "ALL" *) - (* C_USE_BRAM_BLOCK = "0" *) - (* C_USE_BYTE_WEA = "0" *) - (* C_USE_BYTE_WEB = "0" *) - (* C_USE_DEFAULT_DATA = "0" *) - (* C_USE_ECC = "0" *) - (* C_USE_SOFTECC = "0" *) - (* C_USE_URAM = "0" *) - (* C_WEA_WIDTH = "1" *) - (* C_WEB_WIDTH = "1" *) - (* C_WRITE_DEPTH_A = "2048" *) - (* C_WRITE_DEPTH_B = "2048" *) - (* C_WRITE_MODE_A = "WRITE_FIRST" *) - (* C_WRITE_MODE_B = "WRITE_FIRST" *) - (* C_WRITE_WIDTH_A = "32" *) - (* C_WRITE_WIDTH_B = "32" *) - (* C_XDEVICEFAMILY = "kintex7" *) - (* downgradeipidentifiedwarnings = "yes" *) - inst_rom_blk_mem_gen_v8_4_4 U0 - (.addra(addra), - .addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .clka(clka), - .clkb(1'b0), - .dbiterr(NLW_U0_dbiterr_UNCONNECTED), - .deepsleep(1'b0), - .dina({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .douta(douta), - .doutb(NLW_U0_doutb_UNCONNECTED[31:0]), - .eccpipece(1'b0), - .ena(ena), - .enb(1'b0), - .injectdbiterr(1'b0), - .injectsbiterr(1'b0), - .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[10:0]), - .regcea(1'b0), - .regceb(1'b0), - .rsta(1'b0), - .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED), - .rstb(1'b0), - .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED), - .s_aclk(1'b0), - .s_aresetn(1'b0), - .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_arburst({1'b0,1'b0}), - .s_axi_arid({1'b0,1'b0,1'b0,1'b0}), - .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), - .s_axi_arsize({1'b0,1'b0,1'b0}), - .s_axi_arvalid(1'b0), - .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_awburst({1'b0,1'b0}), - .s_axi_awid({1'b0,1'b0,1'b0,1'b0}), - .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), - .s_axi_awsize({1'b0,1'b0,1'b0}), - .s_axi_awvalid(1'b0), - .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]), - .s_axi_bready(1'b0), - .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), - .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), - .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED), - .s_axi_injectdbiterr(1'b0), - .s_axi_injectsbiterr(1'b0), - .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[10:0]), - .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[31:0]), - .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]), - .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), - .s_axi_rready(1'b0), - .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), - .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), - .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED), - .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_wlast(1'b0), - .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), - .s_axi_wstrb(1'b0), - .s_axi_wvalid(1'b0), - .sbiterr(NLW_U0_sbiterr_UNCONNECTED), - .shutdown(1'b0), - .sleep(1'b0), - .wea(1'b0), - .web(1'b0)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) -module inst_rom_blk_mem_gen_generic_cstr - (douta, - clka, - ena, - addra); - output [31:0]douta; - input clka; - input ena; - input [10:0]addra; - - wire [10:0]addra; - wire clka; - wire [31:0]douta; - wire ena; - - inst_rom_blk_mem_gen_prim_width \ramloop[0].ram.r - (.addra(addra), - .clka(clka), - .douta(douta[17:0]), - .ena(ena)); - inst_rom_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r - (.addra(addra), - .clka(clka), - .douta(douta[31:18]), - .ena(ena)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) -module inst_rom_blk_mem_gen_prim_width - (douta, - clka, - ena, - addra); - output [17:0]douta; - input clka; - input ena; - input [10:0]addra; - - wire [10:0]addra; - wire clka; - wire [17:0]douta; - wire ena; - - inst_rom_blk_mem_gen_prim_wrapper_init \prim_init.ram - (.addra(addra), - .clka(clka), - .douta(douta), - .ena(ena)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) -module inst_rom_blk_mem_gen_prim_width__parameterized0 - (douta, - clka, - ena, - addra); - output [13:0]douta; - input clka; - input ena; - input [10:0]addra; - - wire [10:0]addra; - wire clka; - wire [13:0]douta; - wire ena; - - inst_rom_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram - (.addra(addra), - .clka(clka), - .douta(douta), - .ena(ena)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) -module inst_rom_blk_mem_gen_prim_wrapper_init - (douta, - clka, - ena, - addra); - output [17:0]douta; - input clka; - input ena; - input [10:0]addra; - - wire [10:0]addra; - wire clka; - wire [17:0]douta; - wire ena; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; - wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; - wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; - wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; - wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; - wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; - - (* box_type = "PRIMITIVE" *) - RAMB36E1 #( - .DOA_REG(0), - .DOB_REG(0), - .EN_ECC_READ("FALSE"), - .EN_ECC_WRITE("FALSE"), - .INITP_00(256'h00000000000000000000000000000000000000005029580074809780A54801D8), - .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_00(256'hA936093C04019435043C8435043C00000916A936893C04011435043C8435043C), - .INIT_01(256'h04019435843C8435843C000009162936893C04019435043C8435043C00000916), - .INIT_02(256'h04010424042400000916A936093C04019435843C0435043C00000916A936893C), - .INIT_03(256'h000000000000000000000000000000000000000000000000004A000009160924), - .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_A(36'h000000000), - .INIT_B(36'h000000000), - .INIT_FILE("NONE"), - .IS_CLKARDCLK_INVERTED(1'b0), - .IS_CLKBWRCLK_INVERTED(1'b0), - .IS_ENARDEN_INVERTED(1'b0), - .IS_ENBWREN_INVERTED(1'b0), - .IS_RSTRAMARSTRAM_INVERTED(1'b0), - .IS_RSTRAMB_INVERTED(1'b0), - .IS_RSTREGARSTREG_INVERTED(1'b0), - .IS_RSTREGB_INVERTED(1'b0), - .RAM_EXTENSION_A("NONE"), - .RAM_EXTENSION_B("NONE"), - .RAM_MODE("TDP"), - .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), - .READ_WIDTH_A(18), - .READ_WIDTH_B(18), - .RSTREG_PRIORITY_A("REGCE"), - .RSTREG_PRIORITY_B("REGCE"), - .SIM_COLLISION_CHECK("ALL"), - .SIM_DEVICE("7SERIES"), - .SRVAL_A(36'h000000000), - .SRVAL_B(36'h000000000), - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(18), - .WRITE_WIDTH_B(18)) - \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram - (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1}), - .ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .CASCADEINA(1'b0), - .CASCADEINB(1'b0), - .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), - .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), - .CLKARDCLK(clka), - .CLKBWRCLK(clka), - .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIPADIP({1'b0,1'b0,1'b0,1'b0}), - .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), - .DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:16],douta[16:9],douta[7:0]}), - .DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]), - .DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:2],douta[17],douta[8]}), - .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]), - .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(ena), - .ENBWREN(1'b0), - .INJECTDBITERR(1'b0), - .INJECTSBITERR(1'b0), - .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), - .REGCEAREGCE(1'b0), - .REGCEB(1'b0), - .RSTRAMARSTRAM(1'b0), - .RSTRAMB(1'b0), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), - .WEA({1'b0,1'b0,1'b0,1'b0}), - .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) -module inst_rom_blk_mem_gen_prim_wrapper_init__parameterized0 - (douta, - clka, - ena, - addra); - output [13:0]douta; - input clka; - input ena; - input [10:0]addra; - - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_20 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_28 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_70 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71 ; - wire [10:0]addra; - wire clka; - wire [13:0]douta; - wire ena; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; - wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; - wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; - wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; - wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; - wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; - - (* box_type = "PRIMITIVE" *) - RAMB36E1 #( - .DOA_REG(0), - .DOB_REG(0), - .EN_ECC_READ("FALSE"), - .EN_ECC_WRITE("FALSE"), - .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_00(256'h101349741020701C3C6A20370C4A00001600040C0A111020020C4950023F4001), - .INIT_01(256'h10207237373E7109761600000D003E4B077010200E7E5650300C306000001140), - .INIT_02(256'h10200000000000000400003A3C12102000125F7600285C5C0000084063012D55), - .INIT_03(256'h000000000000000000000000000000000000000000001F400000000001000000), - .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_A(36'h000000000), - .INIT_B(36'h000000000), - .INIT_FILE("NONE"), - .IS_CLKARDCLK_INVERTED(1'b0), - .IS_CLKBWRCLK_INVERTED(1'b0), - .IS_ENARDEN_INVERTED(1'b0), - .IS_ENBWREN_INVERTED(1'b0), - .IS_RSTRAMARSTRAM_INVERTED(1'b0), - .IS_RSTRAMB_INVERTED(1'b0), - .IS_RSTREGARSTREG_INVERTED(1'b0), - .IS_RSTREGB_INVERTED(1'b0), - .RAM_EXTENSION_A("NONE"), - .RAM_EXTENSION_B("NONE"), - .RAM_MODE("TDP"), - .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), - .READ_WIDTH_A(18), - .READ_WIDTH_B(18), - .RSTREG_PRIORITY_A("REGCE"), - .RSTREG_PRIORITY_B("REGCE"), - .SIM_COLLISION_CHECK("ALL"), - .SIM_DEVICE("7SERIES"), - .SRVAL_A(36'h000000000), - .SRVAL_B(36'h000000000), - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(18), - .WRITE_WIDTH_B(18)) - \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram - (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1}), - .ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .CASCADEINA(1'b0), - .CASCADEINB(1'b0), - .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), - .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), - .CLKARDCLK(clka), - .CLKBWRCLK(clka), - .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIPADIP({1'b0,1'b0,1'b0,1'b0}), - .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), - .DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:16],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_20 ,douta[13:7],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_28 ,douta[6:0]}), - .DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]), - .DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:2],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_70 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71 }), - .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]), - .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(ena), - .ENBWREN(1'b0), - .INJECTDBITERR(1'b0), - .INJECTSBITERR(1'b0), - .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), - .REGCEAREGCE(1'b0), - .REGCEB(1'b0), - .RSTRAMARSTRAM(1'b0), - .RSTRAMB(1'b0), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), - .WEA({1'b0,1'b0,1'b0,1'b0}), - .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_top" *) -module inst_rom_blk_mem_gen_top - (douta, - clka, - ena, - addra); - output [31:0]douta; - input clka; - input ena; - input [10:0]addra; - - wire [10:0]addra; - wire clka; - wire [31:0]douta; - wire ena; - - inst_rom_blk_mem_gen_generic_cstr \valid.cstr - (.addra(addra), - .clka(clka), - .douta(douta), - .ena(ena)); -endmodule - -(* C_ADDRA_WIDTH = "11" *) (* C_ADDRB_WIDTH = "11" *) (* C_ALGORITHM = "1" *) -(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) -(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *) -(* C_COUNT_36K_BRAM = "2" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *) -(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *) -(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *) -(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) -(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 4.8711 mW" *) -(* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *) -(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) -(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) -(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) -(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) -(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "inst_rom.mem" *) -(* C_INIT_FILE_NAME = "inst_rom.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *) -(* C_MEM_TYPE = "3" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) -(* C_READ_DEPTH_A = "2048" *) (* C_READ_DEPTH_B = "2048" *) (* C_READ_LATENCY_A = "1" *) -(* C_READ_LATENCY_B = "1" *) (* C_READ_WIDTH_A = "32" *) (* C_READ_WIDTH_B = "32" *) -(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *) -(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *) -(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *) -(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *) -(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "2048" *) -(* C_WRITE_DEPTH_B = "2048" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) -(* C_WRITE_WIDTH_A = "32" *) (* C_WRITE_WIDTH_B = "32" *) (* C_XDEVICEFAMILY = "kintex7" *) -(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *) -module inst_rom_blk_mem_gen_v8_4_4 - (clka, - rsta, - ena, - regcea, - wea, - addra, - dina, - douta, - clkb, - rstb, - enb, - regceb, - web, - addrb, - dinb, - doutb, - injectsbiterr, - injectdbiterr, - eccpipece, - sbiterr, - dbiterr, - rdaddrecc, - sleep, - deepsleep, - shutdown, - rsta_busy, - rstb_busy, - s_aclk, - s_aresetn, - s_axi_awid, - s_axi_awaddr, - s_axi_awlen, - s_axi_awsize, - s_axi_awburst, - s_axi_awvalid, - s_axi_awready, - s_axi_wdata, - s_axi_wstrb, - s_axi_wlast, - s_axi_wvalid, - s_axi_wready, - s_axi_bid, - s_axi_bresp, - s_axi_bvalid, - s_axi_bready, - s_axi_arid, - s_axi_araddr, - s_axi_arlen, - s_axi_arsize, - s_axi_arburst, - s_axi_arvalid, - s_axi_arready, - s_axi_rid, - s_axi_rdata, - s_axi_rresp, - s_axi_rlast, - s_axi_rvalid, - s_axi_rready, - s_axi_injectsbiterr, - s_axi_injectdbiterr, - s_axi_sbiterr, - s_axi_dbiterr, - s_axi_rdaddrecc); - input clka; - input rsta; - input ena; - input regcea; - input [0:0]wea; - input [10:0]addra; - input [31:0]dina; - output [31:0]douta; - input clkb; - input rstb; - input enb; - input regceb; - input [0:0]web; - input [10:0]addrb; - input [31:0]dinb; - output [31:0]doutb; - input injectsbiterr; - input injectdbiterr; - input eccpipece; - output sbiterr; - output dbiterr; - output [10:0]rdaddrecc; - input sleep; - input deepsleep; - input shutdown; - output rsta_busy; - output rstb_busy; - input s_aclk; - input s_aresetn; - input [3:0]s_axi_awid; - input [31:0]s_axi_awaddr; - input [7:0]s_axi_awlen; - input [2:0]s_axi_awsize; - input [1:0]s_axi_awburst; - input s_axi_awvalid; - output s_axi_awready; - input [31:0]s_axi_wdata; - input [0:0]s_axi_wstrb; - input s_axi_wlast; - input s_axi_wvalid; - output s_axi_wready; - output [3:0]s_axi_bid; - output [1:0]s_axi_bresp; - output s_axi_bvalid; - input s_axi_bready; - input [3:0]s_axi_arid; - input [31:0]s_axi_araddr; - input [7:0]s_axi_arlen; - input [2:0]s_axi_arsize; - input [1:0]s_axi_arburst; - input s_axi_arvalid; - output s_axi_arready; - output [3:0]s_axi_rid; - output [31:0]s_axi_rdata; - output [1:0]s_axi_rresp; - output s_axi_rlast; - output s_axi_rvalid; - input s_axi_rready; - input s_axi_injectsbiterr; - input s_axi_injectdbiterr; - output s_axi_sbiterr; - output s_axi_dbiterr; - output [10:0]s_axi_rdaddrecc; - - wire \ ; - wire [10:0]addra; - wire clka; - wire [31:0]douta; - wire ena; - - assign dbiterr = \ ; - assign doutb[31] = \ ; - assign doutb[30] = \ ; - assign doutb[29] = \ ; - assign doutb[28] = \ ; - assign doutb[27] = \ ; - assign doutb[26] = \ ; - assign doutb[25] = \ ; - assign doutb[24] = \ ; - assign doutb[23] = \ ; - assign doutb[22] = \ ; - assign doutb[21] = \ ; - assign doutb[20] = \ ; - assign doutb[19] = \ ; - assign doutb[18] = \ ; - assign doutb[17] = \ ; - assign doutb[16] = \ ; - assign doutb[15] = \ ; - assign doutb[14] = \ ; - assign doutb[13] = \ ; - assign doutb[12] = \ ; - assign doutb[11] = \ ; - assign doutb[10] = \ ; - assign doutb[9] = \ ; - assign doutb[8] = \ ; - assign doutb[7] = \ ; - assign doutb[6] = \ ; - assign doutb[5] = \ ; - assign doutb[4] = \ ; - assign doutb[3] = \ ; - assign doutb[2] = \ ; - assign doutb[1] = \ ; - assign doutb[0] = \ ; - assign rdaddrecc[10] = \ ; - assign rdaddrecc[9] = \ ; - assign rdaddrecc[8] = \ ; - assign rdaddrecc[7] = \ ; - assign rdaddrecc[6] = \ ; - assign rdaddrecc[5] = \ ; - assign rdaddrecc[4] = \ ; - assign rdaddrecc[3] = \ ; - assign rdaddrecc[2] = \ ; - assign rdaddrecc[1] = \ ; - assign rdaddrecc[0] = \ ; - assign rsta_busy = \ ; - assign rstb_busy = \ ; - assign s_axi_arready = \ ; - assign s_axi_awready = \ ; - assign s_axi_bid[3] = \ ; - assign s_axi_bid[2] = \ ; - assign s_axi_bid[1] = \ ; - assign s_axi_bid[0] = \ ; - assign s_axi_bresp[1] = \ ; - assign s_axi_bresp[0] = \ ; - assign s_axi_bvalid = \ ; - assign s_axi_dbiterr = \ ; - assign s_axi_rdaddrecc[10] = \ ; - assign s_axi_rdaddrecc[9] = \ ; - assign s_axi_rdaddrecc[8] = \ ; - assign s_axi_rdaddrecc[7] = \ ; - assign s_axi_rdaddrecc[6] = \ ; - assign s_axi_rdaddrecc[5] = \ ; - assign s_axi_rdaddrecc[4] = \ ; - assign s_axi_rdaddrecc[3] = \ ; - assign s_axi_rdaddrecc[2] = \ ; - assign s_axi_rdaddrecc[1] = \ ; - assign s_axi_rdaddrecc[0] = \ ; - assign s_axi_rdata[31] = \ ; - assign s_axi_rdata[30] = \ ; - assign s_axi_rdata[29] = \ ; - assign s_axi_rdata[28] = \ ; - assign s_axi_rdata[27] = \ ; - assign s_axi_rdata[26] = \ ; - assign s_axi_rdata[25] = \ ; - assign s_axi_rdata[24] = \ ; - assign s_axi_rdata[23] = \ ; - assign s_axi_rdata[22] = \ ; - assign s_axi_rdata[21] = \ ; - assign s_axi_rdata[20] = \ ; - assign s_axi_rdata[19] = \ ; - assign s_axi_rdata[18] = \ ; - assign s_axi_rdata[17] = \ ; - assign s_axi_rdata[16] = \ ; - assign s_axi_rdata[15] = \ ; - assign s_axi_rdata[14] = \ ; - assign s_axi_rdata[13] = \ ; - assign s_axi_rdata[12] = \ ; - assign s_axi_rdata[11] = \ ; - assign s_axi_rdata[10] = \ ; - assign s_axi_rdata[9] = \ ; - assign s_axi_rdata[8] = \ ; - assign s_axi_rdata[7] = \ ; - assign s_axi_rdata[6] = \ ; - assign s_axi_rdata[5] = \ ; - assign s_axi_rdata[4] = \ ; - assign s_axi_rdata[3] = \ ; - assign s_axi_rdata[2] = \ ; - assign s_axi_rdata[1] = \ ; - assign s_axi_rdata[0] = \ ; - assign s_axi_rid[3] = \ ; - assign s_axi_rid[2] = \ ; - assign s_axi_rid[1] = \ ; - assign s_axi_rid[0] = \ ; - assign s_axi_rlast = \ ; - assign s_axi_rresp[1] = \ ; - assign s_axi_rresp[0] = \ ; - assign s_axi_rvalid = \ ; - assign s_axi_sbiterr = \ ; - assign s_axi_wready = \ ; - assign sbiterr = \ ; - GND GND - (.G(\ )); - inst_rom_blk_mem_gen_v8_4_4_synth inst_blk_mem_gen - (.addra(addra), - .clka(clka), - .douta(douta), - .ena(ena)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *) -module inst_rom_blk_mem_gen_v8_4_4_synth - (douta, - clka, - ena, - addra); - output [31:0]douta; - input clka; - input ena; - input [10:0]addra; - - wire [10:0]addra; - wire clka; - wire [31:0]douta; - wire ena; - - inst_rom_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen - (.addra(addra), - .clka(clka), - .douta(douta), - .ena(ena)); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.vhdl b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.vhdl deleted file mode 100644 index 8bcad7c..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.vhdl +++ /dev/null @@ -1,1272 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 -<<<<<<< HEAD --- Date : Fri Oct 29 14:30:24 2021 --- Host : LAPTOP-M01GHSS7 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim --- G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.vhdl -======= --- Date : Fri Oct 29 12:20:53 2021 --- Host : DESKTOP-B2469GJ running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim --- F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_sim_netlist.vhdl ->>>>>>> 0267f8d2796d4dcfb8ccf16deb9b3341e76dfafa --- Design : inst_rom --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7k325tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity inst_rom_blk_mem_gen_prim_wrapper_init is - port ( - douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of inst_rom_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; -end inst_rom_blk_mem_gen_prim_wrapper_init; - -architecture STRUCTURE of inst_rom_blk_mem_gen_prim_wrapper_init is - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; - 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INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_A => X"000000000", - INIT_B => X"000000000", - INIT_FILE => "NONE", - IS_CLKARDCLK_INVERTED => '0', - IS_CLKBWRCLK_INVERTED => '0', - IS_ENARDEN_INVERTED => '0', - IS_ENBWREN_INVERTED => '0', - IS_RSTRAMARSTRAM_INVERTED => '0', - IS_RSTRAMB_INVERTED => '0', - IS_RSTREGARSTREG_INVERTED => '0', - IS_RSTREGB_INVERTED => '0', - RAM_EXTENSION_A => "NONE", - RAM_EXTENSION_B => "NONE", - RAM_MODE => "TDP", - RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", - READ_WIDTH_A => 18, - READ_WIDTH_B => 18, - RSTREG_PRIORITY_A => "REGCE", - RSTREG_PRIORITY_B => "REGCE", - SIM_COLLISION_CHECK => "ALL", - SIM_DEVICE => "7SERIES", - SRVAL_A => X"000000000", - SRVAL_B => X"000000000", - WRITE_MODE_A => "WRITE_FIRST", - WRITE_MODE_B => "WRITE_FIRST", - WRITE_WIDTH_A => 18, - WRITE_WIDTH_B => 18 - ) - port map ( - ADDRARDADDR(15) => '1', - ADDRARDADDR(14 downto 4) => addra(10 downto 0), - ADDRARDADDR(3 downto 0) => B"1111", - ADDRBWRADDR(15 downto 0) => B"0000000000000000", - CASCADEINA => '0', - CASCADEINB => '0', - CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, - CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, - CLKARDCLK => clka, - CLKBWRCLK => clka, - DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, - DIADI(31 downto 0) => B"00000000000000000000000000000000", - DIBDI(31 downto 0) => B"00000000000000000000000000000000", - DIPADIP(3 downto 0) => B"0000", - DIPBDIP(3 downto 0) => B"0000", - DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 16), - DOADO(15 downto 8) => douta(16 downto 9), - DOADO(7 downto 0) => douta(7 downto 0), - DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0), - DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 2), - DOPADOP(1) => douta(17), - DOPADOP(0) => douta(8), - DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), - ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), - ENARDEN => ena, - ENBWREN => '0', - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), - REGCEAREGCE => '0', - REGCEB => '0', - RSTRAMARSTRAM => '0', - RSTRAMB => '0', - RSTREGARSTREG => '0', - RSTREGB => '0', - SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, - WEA(3 downto 0) => B"0000", - WEBWE(7 downto 0) => B"00000000" - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \inst_rom_blk_mem_gen_prim_wrapper_init__parameterized0\ is - port ( - douta : out STD_LOGIC_VECTOR ( 13 downto 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \inst_rom_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init"; -end \inst_rom_blk_mem_gen_prim_wrapper_init__parameterized0\; - -architecture STRUCTURE of \inst_rom_blk_mem_gen_prim_wrapper_init__parameterized0\ is - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_20\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_28\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_70\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; - 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INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_A => X"000000000", - INIT_B => X"000000000", - INIT_FILE => "NONE", - IS_CLKARDCLK_INVERTED => '0', - IS_CLKBWRCLK_INVERTED => '0', - IS_ENARDEN_INVERTED => '0', - IS_ENBWREN_INVERTED => '0', - IS_RSTRAMARSTRAM_INVERTED => '0', - IS_RSTRAMB_INVERTED => '0', - IS_RSTREGARSTREG_INVERTED => '0', - IS_RSTREGB_INVERTED => '0', - RAM_EXTENSION_A => "NONE", - RAM_EXTENSION_B => "NONE", - RAM_MODE => "TDP", - RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", - READ_WIDTH_A => 18, - READ_WIDTH_B => 18, - RSTREG_PRIORITY_A => "REGCE", - RSTREG_PRIORITY_B => "REGCE", - SIM_COLLISION_CHECK => "ALL", - SIM_DEVICE => "7SERIES", - SRVAL_A => X"000000000", - SRVAL_B => X"000000000", - WRITE_MODE_A => "WRITE_FIRST", - WRITE_MODE_B => "WRITE_FIRST", - WRITE_WIDTH_A => 18, - WRITE_WIDTH_B => 18 - ) - port map ( - ADDRARDADDR(15) => '1', - ADDRARDADDR(14 downto 4) => addra(10 downto 0), - ADDRARDADDR(3 downto 0) => B"1111", - ADDRBWRADDR(15 downto 0) => B"0000000000000000", - CASCADEINA => '0', - CASCADEINB => '0', - CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, - CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, - CLKARDCLK => clka, - CLKBWRCLK => clka, - DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, - DIADI(31 downto 0) => B"00000000000000000000000000000000", - DIBDI(31 downto 0) => B"00000000000000000000000000000000", - DIPADIP(3 downto 0) => B"0000", - DIPBDIP(3 downto 0) => B"0000", - DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 16), - DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_20\, - DOADO(14 downto 8) => douta(13 downto 7), - DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_28\, - DOADO(6 downto 0) => douta(6 downto 0), - DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0), - DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 2), - DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_70\, - DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\, - DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), - ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), - ENARDEN => ena, - ENBWREN => '0', - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), - REGCEAREGCE => '0', - REGCEB => '0', - RSTRAMARSTRAM => '0', - RSTRAMB => '0', - RSTREGARSTREG => '0', - RSTREGB => '0', - SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, - WEA(3 downto 0) => B"0000", - WEBWE(7 downto 0) => B"00000000" - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity inst_rom_blk_mem_gen_prim_width is - port ( - douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of inst_rom_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; -end inst_rom_blk_mem_gen_prim_width; - -architecture STRUCTURE of inst_rom_blk_mem_gen_prim_width is -begin -\prim_init.ram\: entity work.inst_rom_blk_mem_gen_prim_wrapper_init - port map ( - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - douta(17 downto 0) => douta(17 downto 0), - ena => ena - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \inst_rom_blk_mem_gen_prim_width__parameterized0\ is - port ( - douta : out STD_LOGIC_VECTOR ( 13 downto 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \inst_rom_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width"; -end \inst_rom_blk_mem_gen_prim_width__parameterized0\; - -architecture STRUCTURE of \inst_rom_blk_mem_gen_prim_width__parameterized0\ is -begin -\prim_init.ram\: entity work.\inst_rom_blk_mem_gen_prim_wrapper_init__parameterized0\ - port map ( - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - douta(13 downto 0) => douta(13 downto 0), - ena => ena - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity inst_rom_blk_mem_gen_generic_cstr is - port ( - douta : out STD_LOGIC_VECTOR ( 31 downto 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of inst_rom_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; -end inst_rom_blk_mem_gen_generic_cstr; - -architecture STRUCTURE of inst_rom_blk_mem_gen_generic_cstr is -begin -\ramloop[0].ram.r\: entity work.inst_rom_blk_mem_gen_prim_width - port map ( - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - douta(17 downto 0) => douta(17 downto 0), - ena => ena - ); -\ramloop[1].ram.r\: entity work.\inst_rom_blk_mem_gen_prim_width__parameterized0\ - port map ( - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - douta(13 downto 0) => douta(31 downto 18), - ena => ena - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity inst_rom_blk_mem_gen_top is - port ( - douta : out STD_LOGIC_VECTOR ( 31 downto 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of inst_rom_blk_mem_gen_top : entity is "blk_mem_gen_top"; -end inst_rom_blk_mem_gen_top; - -architecture STRUCTURE of inst_rom_blk_mem_gen_top is -begin -\valid.cstr\: entity work.inst_rom_blk_mem_gen_generic_cstr - port map ( - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - douta(31 downto 0) => douta(31 downto 0), - ena => ena - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity inst_rom_blk_mem_gen_v8_4_4_synth is - port ( - douta : out STD_LOGIC_VECTOR ( 31 downto 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of inst_rom_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth"; -end inst_rom_blk_mem_gen_v8_4_4_synth; - -architecture STRUCTURE of inst_rom_blk_mem_gen_v8_4_4_synth is -begin -\gnbram.gnativebmg.native_blk_mem_gen\: entity work.inst_rom_blk_mem_gen_top - port map ( - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - douta(31 downto 0) => douta(31 downto 0), - ena => ena - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity inst_rom_blk_mem_gen_v8_4_4 is - port ( - clka : in STD_LOGIC; - rsta : in STD_LOGIC; - ena : in STD_LOGIC; - regcea : in STD_LOGIC; - wea : in STD_LOGIC_VECTOR ( 0 to 0 ); - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); - dina : in STD_LOGIC_VECTOR ( 31 downto 0 ); - douta : out STD_LOGIC_VECTOR ( 31 downto 0 ); - clkb : in STD_LOGIC; - rstb : in STD_LOGIC; - enb : in STD_LOGIC; - regceb : in STD_LOGIC; - web : in STD_LOGIC_VECTOR ( 0 to 0 ); - addrb : in STD_LOGIC_VECTOR ( 10 downto 0 ); - dinb : in STD_LOGIC_VECTOR ( 31 downto 0 ); - doutb : out STD_LOGIC_VECTOR ( 31 downto 0 ); - injectsbiterr : in STD_LOGIC; - injectdbiterr : in STD_LOGIC; - eccpipece : in STD_LOGIC; - sbiterr : out STD_LOGIC; - dbiterr : out STD_LOGIC; - rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 ); - sleep : in STD_LOGIC; - deepsleep : in STD_LOGIC; - shutdown : in STD_LOGIC; - rsta_busy : out STD_LOGIC; - rstb_busy : out STD_LOGIC; - s_aclk : in STD_LOGIC; - s_aresetn : in STD_LOGIC; - s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_awvalid : in STD_LOGIC; - s_axi_awready : out STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_wlast : in STD_LOGIC; - s_axi_wvalid : in STD_LOGIC; - s_axi_wready : out STD_LOGIC; - s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_bvalid : out STD_LOGIC; - s_axi_bready : in STD_LOGIC; - s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_arvalid : in STD_LOGIC; - s_axi_arready : out STD_LOGIC; - s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_rlast : out STD_LOGIC; - s_axi_rvalid : out STD_LOGIC; - s_axi_rready : in STD_LOGIC; - s_axi_injectsbiterr : in STD_LOGIC; - s_axi_injectdbiterr : in STD_LOGIC; - s_axi_sbiterr : out STD_LOGIC; - s_axi_dbiterr : out STD_LOGIC; - s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute C_ADDRA_WIDTH : integer; - attribute C_ADDRA_WIDTH of inst_rom_blk_mem_gen_v8_4_4 : entity is 11; - attribute C_ADDRB_WIDTH : integer; - attribute C_ADDRB_WIDTH of inst_rom_blk_mem_gen_v8_4_4 : entity is 11; - attribute C_ALGORITHM : integer; - attribute C_ALGORITHM of inst_rom_blk_mem_gen_v8_4_4 : entity is 1; - attribute C_AXI_ID_WIDTH : integer; - attribute C_AXI_ID_WIDTH of inst_rom_blk_mem_gen_v8_4_4 : entity is 4; - attribute C_AXI_SLAVE_TYPE : integer; - attribute C_AXI_SLAVE_TYPE of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_AXI_TYPE : integer; - attribute C_AXI_TYPE of inst_rom_blk_mem_gen_v8_4_4 : entity is 1; - attribute C_BYTE_SIZE : integer; - attribute C_BYTE_SIZE of inst_rom_blk_mem_gen_v8_4_4 : entity is 9; - attribute C_COMMON_CLK : integer; - attribute C_COMMON_CLK of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_COUNT_18K_BRAM : string; - attribute C_COUNT_18K_BRAM of inst_rom_blk_mem_gen_v8_4_4 : entity is "0"; - attribute C_COUNT_36K_BRAM : string; - attribute C_COUNT_36K_BRAM of inst_rom_blk_mem_gen_v8_4_4 : entity is "2"; - attribute C_CTRL_ECC_ALGO : string; - attribute C_CTRL_ECC_ALGO of inst_rom_blk_mem_gen_v8_4_4 : entity is "NONE"; - attribute C_DEFAULT_DATA : string; - attribute C_DEFAULT_DATA of inst_rom_blk_mem_gen_v8_4_4 : entity is "0"; - attribute C_DISABLE_WARN_BHV_COLL : integer; - attribute C_DISABLE_WARN_BHV_COLL of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_DISABLE_WARN_BHV_RANGE : integer; - attribute C_DISABLE_WARN_BHV_RANGE of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of inst_rom_blk_mem_gen_v8_4_4 : entity is "./"; - attribute C_ENABLE_32BIT_ADDRESS : integer; - attribute C_ENABLE_32BIT_ADDRESS of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_EN_DEEPSLEEP_PIN : integer; - attribute C_EN_DEEPSLEEP_PIN of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_EN_ECC_PIPE : integer; - attribute C_EN_ECC_PIPE of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_EN_RDADDRA_CHG : integer; - attribute C_EN_RDADDRA_CHG of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_EN_RDADDRB_CHG : integer; - attribute C_EN_RDADDRB_CHG of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_EN_SAFETY_CKT : integer; - attribute C_EN_SAFETY_CKT of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_EN_SHUTDOWN_PIN : integer; - attribute C_EN_SHUTDOWN_PIN of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_EN_SLEEP_PIN : integer; - attribute C_EN_SLEEP_PIN of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_EST_POWER_SUMMARY : string; - attribute C_EST_POWER_SUMMARY of inst_rom_blk_mem_gen_v8_4_4 : entity is "Estimated Power for IP : 4.8711 mW"; - attribute C_FAMILY : string; - attribute C_FAMILY of inst_rom_blk_mem_gen_v8_4_4 : entity is "kintex7"; - attribute C_HAS_AXI_ID : integer; - attribute C_HAS_AXI_ID of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_HAS_ENA : integer; - attribute C_HAS_ENA of inst_rom_blk_mem_gen_v8_4_4 : entity is 1; - attribute C_HAS_ENB : integer; - attribute C_HAS_ENB of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_HAS_INJECTERR : integer; - attribute C_HAS_INJECTERR of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_HAS_MEM_OUTPUT_REGS_A : integer; - attribute C_HAS_MEM_OUTPUT_REGS_A of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_HAS_MEM_OUTPUT_REGS_B : integer; - attribute C_HAS_MEM_OUTPUT_REGS_B of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_HAS_MUX_OUTPUT_REGS_A : integer; - attribute C_HAS_MUX_OUTPUT_REGS_A of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_HAS_MUX_OUTPUT_REGS_B : integer; - attribute C_HAS_MUX_OUTPUT_REGS_B of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_HAS_REGCEA : integer; - attribute C_HAS_REGCEA of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_HAS_REGCEB : integer; - attribute C_HAS_REGCEB of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_HAS_RSTA : integer; - attribute C_HAS_RSTA of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_HAS_RSTB : integer; - attribute C_HAS_RSTB of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; - attribute C_HAS_SOFTECC_INPUT_REGS_A of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_INITA_VAL : string; - attribute C_INITA_VAL of inst_rom_blk_mem_gen_v8_4_4 : entity is "0"; - attribute C_INITB_VAL : string; - attribute C_INITB_VAL of inst_rom_blk_mem_gen_v8_4_4 : entity is "0"; - attribute C_INIT_FILE : string; - attribute C_INIT_FILE of inst_rom_blk_mem_gen_v8_4_4 : entity is "inst_rom.mem"; - attribute C_INIT_FILE_NAME : string; - attribute C_INIT_FILE_NAME of inst_rom_blk_mem_gen_v8_4_4 : entity is "inst_rom.mif"; - attribute C_INTERFACE_TYPE : integer; - attribute C_INTERFACE_TYPE of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_LOAD_INIT_FILE : integer; - attribute C_LOAD_INIT_FILE of inst_rom_blk_mem_gen_v8_4_4 : entity is 1; - attribute C_MEM_TYPE : integer; - attribute C_MEM_TYPE of inst_rom_blk_mem_gen_v8_4_4 : entity is 3; - attribute C_MUX_PIPELINE_STAGES : integer; - attribute C_MUX_PIPELINE_STAGES of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_PRIM_TYPE : integer; - attribute C_PRIM_TYPE of inst_rom_blk_mem_gen_v8_4_4 : entity is 1; - attribute C_READ_DEPTH_A : integer; - attribute C_READ_DEPTH_A of inst_rom_blk_mem_gen_v8_4_4 : entity is 2048; - attribute C_READ_DEPTH_B : integer; - attribute C_READ_DEPTH_B of inst_rom_blk_mem_gen_v8_4_4 : entity is 2048; - attribute C_READ_LATENCY_A : integer; - attribute C_READ_LATENCY_A of inst_rom_blk_mem_gen_v8_4_4 : entity is 1; - attribute C_READ_LATENCY_B : integer; - attribute C_READ_LATENCY_B of inst_rom_blk_mem_gen_v8_4_4 : entity is 1; - attribute C_READ_WIDTH_A : integer; - attribute C_READ_WIDTH_A of inst_rom_blk_mem_gen_v8_4_4 : entity is 32; - attribute C_READ_WIDTH_B : integer; - attribute C_READ_WIDTH_B of inst_rom_blk_mem_gen_v8_4_4 : entity is 32; - attribute C_RSTRAM_A : integer; - attribute C_RSTRAM_A of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_RSTRAM_B : integer; - attribute C_RSTRAM_B of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_RST_PRIORITY_A : string; - attribute C_RST_PRIORITY_A of inst_rom_blk_mem_gen_v8_4_4 : entity is "CE"; - attribute C_RST_PRIORITY_B : string; - attribute C_RST_PRIORITY_B of inst_rom_blk_mem_gen_v8_4_4 : entity is "CE"; - attribute C_SIM_COLLISION_CHECK : string; - attribute C_SIM_COLLISION_CHECK of inst_rom_blk_mem_gen_v8_4_4 : entity is "ALL"; - attribute C_USE_BRAM_BLOCK : integer; - attribute C_USE_BRAM_BLOCK of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_USE_BYTE_WEA : integer; - attribute C_USE_BYTE_WEA of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_USE_BYTE_WEB : integer; - attribute C_USE_BYTE_WEB of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_USE_DEFAULT_DATA : integer; - attribute C_USE_DEFAULT_DATA of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_USE_ECC : integer; - attribute C_USE_ECC of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_USE_SOFTECC : integer; - attribute C_USE_SOFTECC of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_USE_URAM : integer; - attribute C_USE_URAM of inst_rom_blk_mem_gen_v8_4_4 : entity is 0; - attribute C_WEA_WIDTH : integer; - attribute C_WEA_WIDTH of inst_rom_blk_mem_gen_v8_4_4 : entity is 1; - attribute C_WEB_WIDTH : integer; - attribute C_WEB_WIDTH of inst_rom_blk_mem_gen_v8_4_4 : entity is 1; - attribute C_WRITE_DEPTH_A : integer; - attribute C_WRITE_DEPTH_A of inst_rom_blk_mem_gen_v8_4_4 : entity is 2048; - attribute C_WRITE_DEPTH_B : integer; - attribute C_WRITE_DEPTH_B of inst_rom_blk_mem_gen_v8_4_4 : entity is 2048; - attribute C_WRITE_MODE_A : string; - attribute C_WRITE_MODE_A of inst_rom_blk_mem_gen_v8_4_4 : entity is "WRITE_FIRST"; - attribute C_WRITE_MODE_B : string; - attribute C_WRITE_MODE_B of inst_rom_blk_mem_gen_v8_4_4 : entity is "WRITE_FIRST"; - attribute C_WRITE_WIDTH_A : integer; - attribute C_WRITE_WIDTH_A of inst_rom_blk_mem_gen_v8_4_4 : entity is 32; - attribute C_WRITE_WIDTH_B : integer; - attribute C_WRITE_WIDTH_B of inst_rom_blk_mem_gen_v8_4_4 : entity is 32; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of inst_rom_blk_mem_gen_v8_4_4 : entity is "kintex7"; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of inst_rom_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of inst_rom_blk_mem_gen_v8_4_4 : entity is "yes"; -end inst_rom_blk_mem_gen_v8_4_4; - -architecture STRUCTURE of inst_rom_blk_mem_gen_v8_4_4 is - signal \\ : STD_LOGIC; -begin - dbiterr <= \\; - doutb(31) <= \\; - doutb(30) <= \\; - doutb(29) <= \\; - doutb(28) <= \\; - doutb(27) <= \\; - doutb(26) <= \\; - doutb(25) <= \\; - doutb(24) <= \\; - doutb(23) <= \\; - doutb(22) <= \\; - doutb(21) <= \\; - doutb(20) <= \\; - doutb(19) <= \\; - doutb(18) <= \\; - doutb(17) <= \\; - doutb(16) <= \\; - doutb(15) <= \\; - doutb(14) <= \\; - doutb(13) <= \\; - doutb(12) <= \\; - doutb(11) <= \\; - doutb(10) <= \\; - doutb(9) <= \\; - doutb(8) <= \\; - doutb(7) <= \\; - doutb(6) <= \\; - doutb(5) <= \\; - doutb(4) <= \\; - doutb(3) <= \\; - doutb(2) <= \\; - doutb(1) <= \\; - doutb(0) <= \\; - rdaddrecc(10) <= \\; - rdaddrecc(9) <= \\; - rdaddrecc(8) <= \\; - rdaddrecc(7) <= \\; - rdaddrecc(6) <= \\; - rdaddrecc(5) <= \\; - rdaddrecc(4) <= \\; - rdaddrecc(3) <= \\; - rdaddrecc(2) <= \\; - rdaddrecc(1) <= \\; - rdaddrecc(0) <= \\; - rsta_busy <= \\; - rstb_busy <= \\; - s_axi_arready <= \\; - s_axi_awready <= \\; - s_axi_bid(3) <= \\; - s_axi_bid(2) <= \\; - s_axi_bid(1) <= \\; - s_axi_bid(0) <= \\; - s_axi_bresp(1) <= \\; - s_axi_bresp(0) <= \\; - s_axi_bvalid <= \\; - s_axi_dbiterr <= \\; - s_axi_rdaddrecc(10) <= \\; - s_axi_rdaddrecc(9) <= \\; - s_axi_rdaddrecc(8) <= \\; - s_axi_rdaddrecc(7) <= \\; - s_axi_rdaddrecc(6) <= \\; - s_axi_rdaddrecc(5) <= \\; - s_axi_rdaddrecc(4) <= \\; - s_axi_rdaddrecc(3) <= \\; - s_axi_rdaddrecc(2) <= \\; - s_axi_rdaddrecc(1) <= \\; - s_axi_rdaddrecc(0) <= \\; - s_axi_rdata(31) <= \\; - s_axi_rdata(30) <= \\; - s_axi_rdata(29) <= \\; - s_axi_rdata(28) <= \\; - s_axi_rdata(27) <= \\; - s_axi_rdata(26) <= \\; - s_axi_rdata(25) <= \\; - s_axi_rdata(24) <= \\; - s_axi_rdata(23) <= \\; - s_axi_rdata(22) <= \\; - s_axi_rdata(21) <= \\; - s_axi_rdata(20) <= \\; - s_axi_rdata(19) <= \\; - s_axi_rdata(18) <= \\; - s_axi_rdata(17) <= \\; - s_axi_rdata(16) <= \\; - s_axi_rdata(15) <= \\; - s_axi_rdata(14) <= \\; - s_axi_rdata(13) <= \\; - s_axi_rdata(12) <= \\; - s_axi_rdata(11) <= \\; - s_axi_rdata(10) <= \\; - s_axi_rdata(9) <= \\; - s_axi_rdata(8) <= \\; - s_axi_rdata(7) <= \\; - s_axi_rdata(6) <= \\; - s_axi_rdata(5) <= \\; - s_axi_rdata(4) <= \\; - s_axi_rdata(3) <= \\; - s_axi_rdata(2) <= \\; - s_axi_rdata(1) <= \\; - s_axi_rdata(0) <= \\; - s_axi_rid(3) <= \\; - s_axi_rid(2) <= \\; - s_axi_rid(1) <= \\; - s_axi_rid(0) <= \\; - s_axi_rlast <= \\; - s_axi_rresp(1) <= \\; - s_axi_rresp(0) <= \\; - s_axi_rvalid <= \\; - s_axi_sbiterr <= \\; - s_axi_wready <= \\; - sbiterr <= \\; -GND: unisim.vcomponents.GND - port map ( - G => \\ - ); -inst_blk_mem_gen: entity work.inst_rom_blk_mem_gen_v8_4_4_synth - port map ( - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - douta(31 downto 0) => douta(31 downto 0), - ena => ena - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity inst_rom is - port ( - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); - douta : out STD_LOGIC_VECTOR ( 31 downto 0 ) - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of inst_rom : entity is true; - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of inst_rom : entity is "inst_rom,blk_mem_gen_v8_4_4,{}"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of inst_rom : entity is "yes"; - attribute x_core_info : string; - attribute x_core_info of inst_rom : entity is "blk_mem_gen_v8_4_4,Vivado 2019.2"; -end inst_rom; - -architecture STRUCTURE of inst_rom is - signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; - signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); - signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); - signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute C_ADDRA_WIDTH : integer; - attribute C_ADDRA_WIDTH of U0 : label is 11; - attribute C_ADDRB_WIDTH : integer; - attribute C_ADDRB_WIDTH of U0 : label is 11; - attribute C_ALGORITHM : integer; - attribute C_ALGORITHM of U0 : label is 1; - attribute C_AXI_ID_WIDTH : integer; - attribute C_AXI_ID_WIDTH of U0 : label is 4; - attribute C_AXI_SLAVE_TYPE : integer; - attribute C_AXI_SLAVE_TYPE of U0 : label is 0; - attribute C_AXI_TYPE : integer; - attribute C_AXI_TYPE of U0 : label is 1; - attribute C_BYTE_SIZE : integer; - attribute C_BYTE_SIZE of U0 : label is 9; - attribute C_COMMON_CLK : integer; - attribute C_COMMON_CLK of U0 : label is 0; - attribute C_COUNT_18K_BRAM : string; - attribute C_COUNT_18K_BRAM of U0 : label is "0"; - attribute C_COUNT_36K_BRAM : string; - attribute C_COUNT_36K_BRAM of U0 : label is "2"; - attribute C_CTRL_ECC_ALGO : string; - attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; - attribute C_DEFAULT_DATA : string; - attribute C_DEFAULT_DATA of U0 : label is "0"; - attribute C_DISABLE_WARN_BHV_COLL : integer; - attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; - attribute C_DISABLE_WARN_BHV_RANGE : integer; - attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of U0 : label is "./"; - attribute C_ENABLE_32BIT_ADDRESS : integer; - attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; - attribute C_EN_DEEPSLEEP_PIN : integer; - attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; - attribute C_EN_ECC_PIPE : integer; - attribute C_EN_ECC_PIPE of U0 : label is 0; - attribute C_EN_RDADDRA_CHG : integer; - attribute C_EN_RDADDRA_CHG of U0 : label is 0; - attribute C_EN_RDADDRB_CHG : integer; - attribute C_EN_RDADDRB_CHG of U0 : label is 0; - attribute C_EN_SAFETY_CKT : integer; - attribute C_EN_SAFETY_CKT of U0 : label is 0; - attribute C_EN_SHUTDOWN_PIN : integer; - attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; - attribute C_EN_SLEEP_PIN : integer; - attribute C_EN_SLEEP_PIN of U0 : label is 0; - attribute C_EST_POWER_SUMMARY : string; - attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 4.8711 mW"; - attribute C_FAMILY : string; - attribute C_FAMILY of U0 : label is "kintex7"; - attribute C_HAS_AXI_ID : integer; - attribute C_HAS_AXI_ID of U0 : label is 0; - attribute C_HAS_ENA : integer; - attribute C_HAS_ENA of U0 : label is 1; - attribute C_HAS_ENB : integer; - attribute C_HAS_ENB of U0 : label is 0; - attribute C_HAS_INJECTERR : integer; - attribute C_HAS_INJECTERR of U0 : label is 0; - attribute C_HAS_MEM_OUTPUT_REGS_A : integer; - attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0; - attribute C_HAS_MEM_OUTPUT_REGS_B : integer; - attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; - attribute C_HAS_MUX_OUTPUT_REGS_A : integer; - attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; - attribute C_HAS_MUX_OUTPUT_REGS_B : integer; - attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; - attribute C_HAS_REGCEA : integer; - attribute C_HAS_REGCEA of U0 : label is 0; - attribute C_HAS_REGCEB : integer; - attribute C_HAS_REGCEB of U0 : label is 0; - attribute C_HAS_RSTA : integer; - attribute C_HAS_RSTA of U0 : label is 0; - attribute C_HAS_RSTB : integer; - attribute C_HAS_RSTB of U0 : label is 0; - attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; - attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; - attribute C_INITA_VAL : string; - attribute C_INITA_VAL of U0 : label is "0"; - attribute C_INITB_VAL : string; - attribute C_INITB_VAL of U0 : label is "0"; - attribute C_INIT_FILE : string; - attribute C_INIT_FILE of U0 : label is "inst_rom.mem"; - attribute C_INIT_FILE_NAME : string; - attribute C_INIT_FILE_NAME of U0 : label is "inst_rom.mif"; - attribute C_INTERFACE_TYPE : integer; - attribute C_INTERFACE_TYPE of U0 : label is 0; - attribute C_LOAD_INIT_FILE : integer; - attribute C_LOAD_INIT_FILE of U0 : label is 1; - attribute C_MEM_TYPE : integer; - attribute C_MEM_TYPE of U0 : label is 3; - attribute C_MUX_PIPELINE_STAGES : integer; - attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; - attribute C_PRIM_TYPE : integer; - attribute C_PRIM_TYPE of U0 : label is 1; - attribute C_READ_DEPTH_A : integer; - attribute C_READ_DEPTH_A of U0 : label is 2048; - attribute C_READ_DEPTH_B : integer; - attribute C_READ_DEPTH_B of U0 : label is 2048; - attribute C_READ_LATENCY_A : integer; - attribute C_READ_LATENCY_A of U0 : label is 1; - attribute C_READ_LATENCY_B : integer; - attribute C_READ_LATENCY_B of U0 : label is 1; - attribute C_READ_WIDTH_A : integer; - attribute C_READ_WIDTH_A of U0 : label is 32; - attribute C_READ_WIDTH_B : integer; - attribute C_READ_WIDTH_B of U0 : label is 32; - attribute C_RSTRAM_A : integer; - attribute C_RSTRAM_A of U0 : label is 0; - attribute C_RSTRAM_B : integer; - attribute C_RSTRAM_B of U0 : label is 0; - attribute C_RST_PRIORITY_A : string; - attribute C_RST_PRIORITY_A of U0 : label is "CE"; - attribute C_RST_PRIORITY_B : string; - attribute C_RST_PRIORITY_B of U0 : label is "CE"; - attribute C_SIM_COLLISION_CHECK : string; - attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; - attribute C_USE_BRAM_BLOCK : integer; - attribute C_USE_BRAM_BLOCK of U0 : label is 0; - attribute C_USE_BYTE_WEA : integer; - attribute C_USE_BYTE_WEA of U0 : label is 0; - attribute C_USE_BYTE_WEB : integer; - attribute C_USE_BYTE_WEB of U0 : label is 0; - attribute C_USE_DEFAULT_DATA : integer; - attribute C_USE_DEFAULT_DATA of U0 : label is 0; - attribute C_USE_ECC : integer; - attribute C_USE_ECC of U0 : label is 0; - attribute C_USE_SOFTECC : integer; - attribute C_USE_SOFTECC of U0 : label is 0; - attribute C_USE_URAM : integer; - attribute C_USE_URAM of U0 : label is 0; - attribute C_WEA_WIDTH : integer; - attribute C_WEA_WIDTH of U0 : label is 1; - attribute C_WEB_WIDTH : integer; - attribute C_WEB_WIDTH of U0 : label is 1; - attribute C_WRITE_DEPTH_A : integer; - attribute C_WRITE_DEPTH_A of U0 : label is 2048; - attribute C_WRITE_DEPTH_B : integer; - attribute C_WRITE_DEPTH_B of U0 : label is 2048; - attribute C_WRITE_MODE_A : string; - attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; - attribute C_WRITE_MODE_B : string; - attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; - attribute C_WRITE_WIDTH_A : integer; - attribute C_WRITE_WIDTH_A of U0 : label is 32; - attribute C_WRITE_WIDTH_B : integer; - attribute C_WRITE_WIDTH_B of U0 : label is 32; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of U0 : label is "kintex7"; - attribute downgradeipidentifiedwarnings of U0 : label is "yes"; - attribute x_interface_info : string; - attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; - attribute x_interface_parameter : string; - attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1"; - attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; - attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; - attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; -begin -U0: entity work.inst_rom_blk_mem_gen_v8_4_4 - port map ( - addra(10 downto 0) => addra(10 downto 0), - addrb(10 downto 0) => B"00000000000", - clka => clka, - clkb => '0', - dbiterr => NLW_U0_dbiterr_UNCONNECTED, - deepsleep => '0', - dina(31 downto 0) => B"00000000000000000000000000000000", - dinb(31 downto 0) => B"00000000000000000000000000000000", - douta(31 downto 0) => douta(31 downto 0), - doutb(31 downto 0) => NLW_U0_doutb_UNCONNECTED(31 downto 0), - eccpipece => '0', - ena => ena, - enb => '0', - injectdbiterr => '0', - injectsbiterr => '0', - rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0), - regcea => '0', - regceb => '0', - rsta => '0', - rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, - rstb => '0', - rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, - s_aclk => '0', - s_aresetn => '0', - s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", - s_axi_arburst(1 downto 0) => B"00", - s_axi_arid(3 downto 0) => B"0000", - s_axi_arlen(7 downto 0) => B"00000000", - s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, - s_axi_arsize(2 downto 0) => B"000", - s_axi_arvalid => '0', - s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", - s_axi_awburst(1 downto 0) => B"00", - s_axi_awid(3 downto 0) => B"0000", - s_axi_awlen(7 downto 0) => B"00000000", - s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, - s_axi_awsize(2 downto 0) => B"000", - s_axi_awvalid => '0', - s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), - s_axi_bready => '0', - s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), - s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, - s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, - s_axi_injectdbiterr => '0', - s_axi_injectsbiterr => '0', - s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0), - s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0), - s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), - s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, - s_axi_rready => '0', - s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), - s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, - s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, - s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000", - s_axi_wlast => '0', - s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, - s_axi_wstrb(0) => '0', - s_axi_wvalid => '0', - sbiterr => NLW_U0_sbiterr_UNCONNECTED, - shutdown => '0', - sleep => '0', - wea(0) => '0', - web(0) => '0' - ); -end STRUCTURE; diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v deleted file mode 100644 index 09e09e3..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v +++ /dev/null @@ -1,30 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 -<<<<<<< HEAD -// Date : Fri Oct 29 14:30:24 2021 -// Host : LAPTOP-M01GHSS7 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v -======= -// Date : Fri Oct 29 12:20:53 2021 -// Host : DESKTOP-B2469GJ running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.v ->>>>>>> 0267f8d2796d4dcfb8ccf16deb9b3341e76dfafa -// Design : inst_rom -// Purpose : Stub declaration of top-level module interface -// Device : xc7k325tffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2019.2" *) -module inst_rom(clka, ena, addra, douta) -/* synthesis syn_black_box black_box_pad_pin="clka,ena,addra[10:0],douta[31:0]" */; - input clka; - input ena; - input [10:0]addra; - output [31:0]douta; -endmodule diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl b/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl deleted file mode 100644 index dc36558..0000000 --- a/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl +++ /dev/null @@ -1,40 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 -<<<<<<< HEAD --- Date : Fri Oct 29 14:30:24 2021 --- Host : LAPTOP-M01GHSS7 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub --- G:/123/share/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl -======= --- Date : Fri Oct 29 12:20:53 2021 --- Host : DESKTOP-B2469GJ running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub --- F:/gitee/Architecture_work/CPU_core/MiniMIPS32/MiniMIPS32.srcs/sources_1/ip/inst_rom/inst_rom_stub.vhdl ->>>>>>> 0267f8d2796d4dcfb8ccf16deb9b3341e76dfafa --- Design : inst_rom --- Purpose : Stub declaration of top-level module interface --- Device : xc7k325tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity inst_rom is - Port ( - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); - douta : out STD_LOGIC_VECTOR ( 31 downto 0 ) - ); - -end inst_rom; - -architecture stub of inst_rom is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clka,ena,addra[10:0],douta[31:0]"; -attribute x_core_info : string; -attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2019.2"; -begin -end; diff --git a/CPU_core/MiniMIPS32/MiniMIPS32.xpr b/CPU_core/MiniMIPS32/MiniMIPS32.xpr index 0c589ca..b05b6dc 100644 --- a/CPU_core/MiniMIPS32/MiniMIPS32.xpr +++ b/CPU_core/MiniMIPS32/MiniMIPS32.xpr @@ -3,7 +3,7 @@ - +

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