#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Tue Jan 26 00:15:18 2021
# Process ID: 9280
# Current directory: D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent9640 D:\workspace\FPGA\Zynq7020\VivadoPro\Zynq7020_PL\Zynq7020.xpr
# Log file: D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL/vivado.log
# Journal file: D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL/Zynq7020.xpr
update_compile_order -fileset sources_1
set_property -dict [list CONFIG.CLKOUT3_USED {false} CONFIG.MMCM_DIVCLK_DIVIDE {4} CONFIG.MMCM_CLKFBOUT_MULT_F {59.375} CONFIG.MMCM_CLKOUT0_DIVIDE_F {10.000} CONFIG.MMCM_CLKOUT1_DIVIDE {2} CONFIG.MMCM_CLKOUT2_DIVIDE {1} CONFIG.NUM_OUT_CLKS {2} CONFIG.CLKOUT1_JITTER {462.435} CONFIG.CLKOUT1_PHASE_ERROR {610.813} CONFIG.CLKOUT2_JITTER {372.733} CONFIG.CLKOUT2_PHASE_ERROR {610.813}] [get_ips clk_wiz_0]
generate_target all [get_files  D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL/Zynq7020.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci]
catch { config_ip_cache -export [get_ips -all clk_wiz_0] }
export_ip_user_files -of_objects [get_files D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL/Zynq7020.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci] -no_script -sync -force -quiet
reset_run clk_wiz_0_synth_1
launch_runs -jobs 6 clk_wiz_0_synth_1
export_simulation -of_objects [get_files D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL/Zynq7020.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci] -directory D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL/Zynq7020.ip_user_files/sim_scripts -ip_user_files_dir D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL/Zynq7020.ip_user_files -ipstatic_source_dir D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL/Zynq7020.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL/Zynq7020.cache/compile_simlib/modelsim} {questa=D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL/Zynq7020.cache/compile_simlib/questa} {riviera=D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL/Zynq7020.cache/compile_simlib/riviera} {activehdl=D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL/Zynq7020.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 6
wait_on_run impl_1
open_hw
connect_hw_server
open_hw_target
set_property PROGRAM.FILE {D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL/Zynq7020.runs/impl_1/stephen_pl_top.bit} [get_hw_devices xc7z020_1]
current_hw_device [get_hw_devices xc7z020_1]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z020_1] 0]
set_property PROBES.FILE {} [get_hw_devices xc7z020_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z020_1]
set_property PROGRAM.FILE {D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL/Zynq7020.runs/impl_1/stephen_pl_top.bit} [get_hw_devices xc7z020_1]
program_hw_devices [get_hw_devices xc7z020_1]
refresh_hw_device [lindex [get_hw_devices xc7z020_1] 0]
synth_design -rtl -name rtl_1
refresh_design
refresh_design
refresh_design
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 6
wait_on_run impl_1
reset_run impl_1
refresh_design
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 6
wait_on_run impl_1
set_property PROBES.FILE {} [get_hw_devices xc7z020_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z020_1]
set_property PROGRAM.FILE {D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL/Zynq7020.runs/impl_1/stephen_pl_top.bit} [get_hw_devices xc7z020_1]
program_hw_devices [get_hw_devices xc7z020_1]
refresh_hw_device [lindex [get_hw_devices xc7z020_1] 0]
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 6
wait_on_run impl_1
set_property PROBES.FILE {} [get_hw_devices xc7z020_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z020_1]
set_property PROGRAM.FILE {D:/workspace/FPGA/Zynq7020/VivadoPro/Zynq7020_PL/Zynq7020.runs/impl_1/stephen_pl_top.bit} [get_hw_devices xc7z020_1]
program_hw_devices [get_hw_devices xc7z020_1]
refresh_hw_device [lindex [get_hw_devices xc7z020_1] 0]