From eeac0a8a611016f7db163e90340f61caa3f19e98 Mon Sep 17 00:00:00 2001
From: peng-langyuan <peng_langyuan@hoperun.com>
Date: Fri, 8 Nov 2024 05:35:35 +0000
Subject: [PATCH] =?UTF-8?q?bsp=E7=9B=B8=E5=85=B3?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
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---
 demos/raspi4/bsp/mmu.c               | 21 ++++++++++++---
 demos/raspi4/bsp/pl011.h             | 38 ++++++++++++++++++++++++++++
 demos/raspi4/bsp/print.c             |  9 +++++--
 demos/raspi4/bsp/raspi4/cpu_config.h | 19 +++++++++-----
 src/arch/include/prt_gic_external.h  |  4 +--
 5 files changed, 77 insertions(+), 14 deletions(-)
 create mode 100644 demos/raspi4/bsp/pl011.h

diff --git a/demos/raspi4/bsp/mmu.c b/demos/raspi4/bsp/mmu.c
index ffa3249c..e11dffc4 100644
--- a/demos/raspi4/bsp/mmu.c
+++ b/demos/raspi4/bsp/mmu.c
@@ -11,13 +11,26 @@
 extern U64 g_mmu_page_begin;
 extern U64 g_mmu_page_end;
 
+// mmu bug, ivshmem rw 分两映射
 static mmu_mmap_region_s g_mem_map_info[] = {
     {
-        .virt      = MMU_OPENAMP_ADDR,
-        .phys      = MMU_OPENAMP_ADDR,
-        .size      = OPENAMP_SHM_SIZE,
+        .virt      = IVSHMEM_STATUS_ADDR,
+        .phys      = IVSHMEM_STATUS_ADDR,
+        .size      = IVSHMEM_STATUS_SIZE,
         .max_level = 0x2,
         .attrs     = MMU_ATTR_DEVICE_NGNRNE | MMU_ACCESS_RWX,
+    }, {
+        .virt      = IVSHMEM_RW_ADDR,
+        .phys      = IVSHMEM_RW_ADDR,
+        .size      = 0x1000,
+        .max_level = 0x2,
+        .attrs     = MMU_ATTR_CACHE_SHARE | MMU_ACCESS_RWX,
+    }, {
+        .virt      = (IVSHMEM_RW_ADDR + 0x1000),
+        .phys      = (IVSHMEM_RW_ADDR + 0x1000),
+        .size      = ((IVSHMEM_RW_SIZE - 0x1000)),
+        .max_level = 0x2,
+        .attrs     = MMU_ATTR_CACHE_SHARE | MMU_ACCESS_RWX,
     }, {
         .virt      = MMU_IMAGE_ADDR,
         .phys      = MMU_IMAGE_ADDR,
@@ -33,7 +46,7 @@ static mmu_mmap_region_s g_mem_map_info[] = {
     }, {    
         .virt      = MMU_UART_ADDR,
         .phys      = MMU_UART_ADDR,
-        .size      = 0x2000,
+        .size      = 0x1000,
         .max_level = 0x2,
         .attrs     = MMU_ATTR_DEVICE_NGNRNE | MMU_ACCESS_RWX,
     }
diff --git a/demos/raspi4/bsp/pl011.h b/demos/raspi4/bsp/pl011.h
new file mode 100644
index 00000000..e88d380a
--- /dev/null
+++ b/demos/raspi4/bsp/pl011.h
@@ -0,0 +1,38 @@
+#ifndef PL011_H
+#define PL011_H
+
+#include "prt_typedef.h"
+
+#define UART_DR                     0x00
+#define UART_FR                     0x18
+#define UART_ILPR                   0x20
+#define UART_IBRD                   0x24
+#define UART_FBRD                   0x28
+#define UART_LCR_H                  0x2C
+#define UART_CR                     0x30
+#define UART_IFLS                   0x34
+#define UART_IMSC                   0x38
+#define UART_MIS                    0x40
+#define UART_ICR                    0x44
+
+#define UART_CR_RX_EN               (0x01 << 9)
+#define UART_CR_TX_EN               (0x01 << 8)
+#define UART_CR_EN                  (0x01 << 0)
+#define UART_LCR_H_FIFO_EN          (0x01 << 4)
+#define UART_LCR_H_8_BIT            (0x03 << 5)
+#define UART_INT_HALF               (0x02 << 3)
+#define UART_RXRIS                  (0x01 << 4)
+#define UART_RTRIS                  (0x01 << 6)
+
+#define UART_TXFF                   0x20
+#define UART_RXFE                   0x10
+
+#define PL011_CLK_DIV               16U
+#define PL011_NUM_8                 8U
+#define CONSOLE_UART_BAUDRATE       115200U
+
+#define UART_REG(x) (*(volatile U32 *)(UART_BASE_ADDR + (x)))
+#define UART_QUEUE_SIZE             1024
+
+#endif
+
diff --git a/demos/raspi4/bsp/print.c b/demos/raspi4/bsp/print.c
index f4379d1a..a98d9191 100644
--- a/demos/raspi4/bsp/print.c
+++ b/demos/raspi4/bsp/print.c
@@ -2,14 +2,19 @@
 #include "prt_typedef.h"
 #include "cpu_config.h"
 #include "securec.h"
+#include "pl011.h"
 
 typedef U32 (*PrintFunc)(const char *format, va_list vaList);
 #define OS_MAX_SHOW_LEN 0x200
 
 void uart_poll_send(unsigned char ch)
 {
-    volatile int time = 100000;
+    volatile int time = 10000;
+#if defined(CONFIG_CONFIG_UART_PL011)
+    *(unsigned long long int *)(UART_BASE_ADDR + UART_DR) = ch;
+#else
     *(unsigned int *)UART_BASE_ADDR = ch;
+#endif
     while (time--);
 }
 
@@ -62,4 +67,4 @@ int printf(const char *format, ...)
     va_end(vaList);
 
     return (int)count;
-}
\ No newline at end of file
+}
diff --git a/demos/raspi4/bsp/raspi4/cpu_config.h b/demos/raspi4/bsp/raspi4/cpu_config.h
index 59db7ab8..394a347b 100644
--- a/demos/raspi4/bsp/raspi4/cpu_config.h
+++ b/demos/raspi4/bsp/raspi4/cpu_config.h
@@ -3,21 +3,28 @@
 
 #include "cache_asm.h"
 
+#define IVSHMEM_STATUS_ADDR	   0x6fffe000ULL
+#define IVSHMEM_STATUS_SIZE	   0x1000
+#define IVSHMEM_RW_ADDR           0x6ffff000ULL
+#define IVSHMEM_RW_SIZE           0x100000
+
+#define UART_BASE_ADDR             0x9000000ULL
 #define MMU_IMAGE_ADDR             0x7B000000ULL
-#define MMU_GIC_ADDR               0xFF800000ULL
-#define MMU_UART_ADDR              0xFE200000ULL
+#define MMU_GIC_ADDR               0x8000000ULL
+#define MMU_UART_ADDR              UART_BASE_ADDR
 #define MMU_OPENAMP_ADDR           0x70000000ULL
 #define OPENAMP_SHM_SIZE           0x100000
-#define UART_BASE_ADDR             0xFE215040ULL
 
-#define TEST_CLK_INT               30
+// kvm virtual timer INTID(27)
+// physical timer INTID(30)
+#define TEST_CLK_INT               27
 
 #define OS_GIC_VER                 2
 #define SICR_ADDR_OFFSET_PER_CORE  0x200U
-#define GIC_REG_BASE_ADDR          0xFF841000ULL
+#define GIC_REG_BASE_ADDR          MMU_GIC_ADDR
 
 #define GIC_DIST_BASE              GIC_REG_BASE_ADDR
-#define GIC_CPU_BASE               (GIC_DIST_BASE + 0x1000U)
+#define GIC_CPU_BASE               (GIC_DIST_BASE + 0x10000U)
 
 #define GICD_CTLR                  (GIC_DIST_BASE + 0x0000U)
 #define GICD_TYPER                 (GIC_DIST_BASE + 0x0004U)
diff --git a/src/arch/include/prt_gic_external.h b/src/arch/include/prt_gic_external.h
index 4df0f251..fdc03528 100644
--- a/src/arch/include/prt_gic_external.h
+++ b/src/arch/include/prt_gic_external.h
@@ -24,8 +24,8 @@
 #define GIC_IPRIORITY_HIGH_BIT    4
 
 #if (OS_GIC_VER == 2)
-#define GIC_DIST_BASE   0xff841000
-#define GIC_CPU_BASE    0xff842000
+#define GIC_DIST_BASE   0x8000000ULL
+#define GIC_CPU_BASE    0x8010000ULL
 #define IAR_MASK        0x3FFU
 #define GICC_IAR		(GIC_CPU_BASE + 0xc)
 #define GICC_EOIR		(GIC_CPU_BASE + 0x10)
-- 
2.33.0