diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 30adc3e3b71cbefb8c5f884f55679307591328be..3bab8617fbcf32dbc94a837450005a5ada994732 100755
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -45,5 +45,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += OK3399-C.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi-4-lts.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-8897-ddr4-v1-linux-base.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-8897-ddr4-v1-linux-hdmi.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += roc-rk3588s-pc.dtb
 
  
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi-4-lts.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi-4-lts.dts
new file mode 100644
index 0000000000000000000000000000000000000000..4e6bd4a961ce5b447b66ae178248c00ffa6b448d
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi-4-lts.dts
@@ -0,0 +1,4056 @@
+/dts-v1/;
+
+/ {
+	compatible = "rockchip,rk3399-orangepi-4-lts\0rockchip,rk3399";
+	interrupt-parent = <0x01>;
+	#address-cells = <0x02>;
+	#size-cells = <0x02>;
+	model = "Orange Pi 4 LTS";
+
+	aliases {
+		ethernet0 = "/ethernet@fe300000";
+		i2c0 = "/i2c@ff3c0000";
+		i2c1 = "/i2c@ff110000";
+		i2c2 = "/i2c@ff120000";
+		i2c3 = "/i2c@ff130000";
+		i2c4 = "/i2c@ff3d0000";
+		i2c5 = "/i2c@ff140000";
+		i2c6 = "/i2c@ff150000";
+		i2c7 = "/i2c@ff160000";
+		i2c8 = "/i2c@ff3e0000";
+		serial0 = "/serial@ff180000";
+		serial1 = "/serial@ff190000";
+		serial2 = "/serial@ff1a0000";
+		serial3 = "/serial@ff1b0000";
+		serial4 = "/serial@ff370000";
+		mmc0 = "/mmc@fe320000";
+		mmc1 = "/mmc@fe330000";
+	};
+
+	cpus {
+		#address-cells = <0x02>;
+		#size-cells = <0x00>;
+
+		cpu-map {
+
+			cluster0 {
+
+				core0 {
+					cpu = <0x02>;
+				};
+
+				core1 {
+					cpu = <0x03>;
+				};
+
+				core2 {
+					cpu = <0x04>;
+				};
+
+				core3 {
+					cpu = <0x05>;
+				};
+			};
+
+			cluster1 {
+
+				core0 {
+					cpu = <0x06>;
+				};
+
+				core1 {
+					cpu = <0x07>;
+				};
+			};
+		};
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x00 0x00>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x1e5>;
+			clocks = <0x08 0x08>;
+			#cooling-cells = <0x02>;
+			dynamic-power-coefficient = <0x64>;
+			cpu-idle-states = <0x09 0x0a>;
+			operating-points-v2 = <0x0b>;
+			cpu-supply = <0x0c>;
+			phandle = <0x02>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x00 0x01>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x1e5>;
+			clocks = <0x08 0x08>;
+			#cooling-cells = <0x02>;
+			dynamic-power-coefficient = <0x64>;
+			cpu-idle-states = <0x09 0x0a>;
+			operating-points-v2 = <0x0b>;
+			cpu-supply = <0x0c>;
+			phandle = <0x03>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x00 0x02>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x1e5>;
+			clocks = <0x08 0x08>;
+			#cooling-cells = <0x02>;
+			dynamic-power-coefficient = <0x64>;
+			cpu-idle-states = <0x09 0x0a>;
+			operating-points-v2 = <0x0b>;
+			cpu-supply = <0x0c>;
+			phandle = <0x04>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x00 0x03>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x1e5>;
+			clocks = <0x08 0x08>;
+			#cooling-cells = <0x02>;
+			dynamic-power-coefficient = <0x64>;
+			cpu-idle-states = <0x09 0x0a>;
+			operating-points-v2 = <0x0b>;
+			cpu-supply = <0x0c>;
+			phandle = <0x05>;
+		};
+
+		cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x00 0x100>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x400>;
+			clocks = <0x08 0x09>;
+			#cooling-cells = <0x02>;
+			dynamic-power-coefficient = <0x1b4>;
+			cpu-idle-states = <0x09 0x0a>;
+			operating-points-v2 = <0x0d>;
+			cpu-supply = <0x0e>;
+			phandle = <0x06>;
+
+			thermal-idle {
+				#cooling-cells = <0x02>;
+				duration-us = <0x2710>;
+				exit-latency-us = <0x1f4>;
+			};
+		};
+
+		cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x00 0x101>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x400>;
+			clocks = <0x08 0x09>;
+			#cooling-cells = <0x02>;
+			dynamic-power-coefficient = <0x1b4>;
+			cpu-idle-states = <0x09 0x0a>;
+			operating-points-v2 = <0x0d>;
+			cpu-supply = <0x0e>;
+			phandle = <0x07>;
+
+			thermal-idle {
+				#cooling-cells = <0x02>;
+				duration-us = <0x2710>;
+				exit-latency-us = <0x1f4>;
+			};
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			cpu-sleep {
+				compatible = "arm,idle-state";
+				local-timer-stop;
+				arm,psci-suspend-param = <0x10000>;
+				entry-latency-us = <0x78>;
+				exit-latency-us = <0xfa>;
+				min-residency-us = <0x384>;
+				phandle = <0x09>;
+			};
+
+			cluster-sleep {
+				compatible = "arm,idle-state";
+				local-timer-stop;
+				arm,psci-suspend-param = <0x1010000>;
+				entry-latency-us = <0x190>;
+				exit-latency-us = <0x1f4>;
+				min-residency-us = <0x7d0>;
+				phandle = <0x0a>;
+			};
+		};
+	};
+
+	display-subsystem {
+		compatible = "rockchip,display-subsystem";
+		ports = <0x0f 0x10>;
+	};
+
+	memory-controller {
+		compatible = "rockchip,rk3399-dmc";
+		rockchip,pmu = <0x11>;
+		devfreq-events = <0x12>;
+		clocks = <0x08 0xa8>;
+		clock-names = "dmc_clk";
+		status = "disabled";
+		phandle = <0xc6>;
+	};
+
+	pmu_a53 {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <0x01 0x07 0x08 0x13>;
+	};
+
+	pmu_a72 {
+		compatible = "arm,cortex-a72-pmu";
+		interrupts = <0x01 0x07 0x08 0x14>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <0x01 0x0d 0x08 0x00 0x01 0x0e 0x08 0x00 0x01 0x0b 0x08 0x00 0x01 0x0a 0x08 0x00>;
+		arm,no-tick-in-suspend;
+	};
+
+	xin24m {
+		compatible = "fixed-clock";
+		clock-frequency = <0x16e3600>;
+		clock-output-names = "xin24m";
+		#clock-cells = <0x00>;
+		phandle = <0x8f>;
+	};
+
+	pcie@f8000000 {
+		compatible = "rockchip,rk3399-pcie";
+		reg = <0x00 0xf8000000 0x00 0x2000000 0x00 0xfd000000 0x00 0x1000000>;
+		reg-names = "axi-base\0apb-base";
+		device_type = "pci";
+		#address-cells = <0x03>;
+		#size-cells = <0x02>;
+		#interrupt-cells = <0x01>;
+		aspm-no-l0s;
+		bus-range = <0x00 0x1f>;
+		clocks = <0x08 0xc5 0x08 0xc4 0x08 0x147 0x08 0xa0>;
+		clock-names = "aclk\0aclk-perf\0hclk\0pm";
+		interrupts = <0x00 0x31 0x04 0x00 0x00 0x32 0x04 0x00 0x00 0x33 0x04 0x00>;
+		interrupt-names = "sys\0legacy\0client";
+		interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+		interrupt-map = <0x00 0x00 0x00 0x01 0x15 0x00 0x00 0x00 0x00 0x02 0x15 0x01 0x00 0x00 0x00 0x03 0x15 0x02 0x00 0x00 0x00 0x04 0x15 0x03>;
+		max-link-speed = <0x01>;
+		msi-map = <0x00 0x16 0x00 0x1000>;
+		phys = <0x17 0x00 0x17 0x01 0x17 0x02 0x17 0x03>;
+		phy-names = "pcie-phy-0\0pcie-phy-1\0pcie-phy-2\0pcie-phy-3";
+		ranges = <0x82000000 0x00 0xfa000000 0x00 0xfa000000 0x00 0x1e00000 0x81000000 0x00 0xfbe00000 0x00 0xfbe00000 0x00 0x100000>;
+		resets = <0x08 0x82 0x08 0x83 0x08 0x84 0x08 0x85 0x08 0x86 0x08 0x81 0x08 0x80>;
+		reset-names = "core\0mgmt\0mgmt-sticky\0pipe\0pm\0pclk\0aclk";
+		status = "okay";
+		ep-gpios = <0x18 0x04 0x00>;
+		num-lanes = <0x04>;
+		phandle = <0xc7>;
+
+		interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0x00>;
+			#interrupt-cells = <0x01>;
+			phandle = <0x15>;
+		};
+	};
+
+	ethernet@fe300000 {
+		compatible = "rockchip,rk3399-gmac";
+		reg = <0x00 0xfe300000 0x00 0x10000>;
+		interrupts = <0x00 0x0c 0x04 0x00>;
+		interrupt-names = "macirq";
+		clocks = <0x08 0x69 0x08 0x67 0x08 0x68 0x08 0x66 0x08 0x6a 0x08 0xd5 0x08 0x166>;
+		clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_ref\0clk_mac_refout\0aclk_mac\0pclk_mac";
+		power-domains = <0x19 0x16>;
+		resets = <0x08 0x89>;
+		reset-names = "stmmaceth";
+		rockchip,grf = <0x1a>;
+		snps,txpbl = <0x04>;
+		status = "okay";
+		assigned-clocks = <0x08 0xa6>;
+		assigned-clock-parents = <0x1b>;
+		clock_in_out = "input";
+		phy-supply = <0x1c>;
+		phy-mode = "rgmii";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x1d>;
+		snps,reset-gpio = <0x1e 0x0f 0x01>;
+		snps,reset-active-low;
+		snps,reset-delays-us = <0x00 0x2710 0xc350>;
+		tx_delay = <0x28>;
+		rx_delay = <0x11>;
+		phandle = <0xc8>;
+	};
+
+	mmc@fe310000 {
+		compatible = "rockchip,rk3399-dw-mshc\0rockchip,rk3288-dw-mshc";
+		reg = <0x00 0xfe310000 0x00 0x4000>;
+		interrupts = <0x00 0x40 0x04 0x00>;
+		max-frequency = <0x8f0d180>;
+		clocks = <0x08 0x1ee 0x08 0x4d 0x08 0x9c 0x08 0x9d>;
+		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
+		fifo-depth = <0x100>;
+		power-domains = <0x19 0x1c>;
+		resets = <0x08 0x79>;
+		reset-names = "reset";
+		status = "okay";
+		clock-frequency = <0x8f0d180>;
+		clock-freq-min-max = <0x30d40 0x2faf080>;
+		supports-sdio;
+		bus-width = <0x04>;
+		disable-wp;
+		cap-sd-highspeed;
+		cap-sdio-irq;
+		keep-power-in-suspend;
+		mmc-pwrseq = <0x1f>;
+		non-removable;
+		num-slots = <0x01>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x20 0x21 0x22>;
+		sd-uhs-sdr104;
+		phandle = <0xc9>;
+	};
+
+	mmc@fe320000 {
+		compatible = "rockchip,rk3399-dw-mshc\0rockchip,rk3288-dw-mshc";
+		reg = <0x00 0xfe320000 0x00 0x4000>;
+		interrupts = <0x00 0x41 0x04 0x00>;
+		max-frequency = <0x8f0d180>;
+		assigned-clocks = <0x08 0x1cd>;
+		assigned-clock-rates = <0xbebc200>;
+		clocks = <0x08 0x1ce 0x08 0x4c 0x08 0x9a 0x08 0x9b>;
+		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
+		fifo-depth = <0x100>;
+		power-domains = <0x19 0x1b>;
+		resets = <0x08 0x7a>;
+		reset-names = "reset";
+		status = "okay";
+		bus-width = <0x04>;
+		cap-sd-highspeed;
+		cap-mmc-highspeed;
+		cd-gpios = <0x23 0x07 0x01>;
+		disable-wp;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x24 0x25 0x26>;
+		vmmc-supply = <0x27>;
+		vqmmc-supply = <0x28>;
+		phandle = <0xca>;
+	};
+
+	mmc@fe330000 {
+		compatible = "rockchip,rk3399-sdhci-5.1\0arasan,sdhci-5.1";
+		reg = <0x00 0xfe330000 0x00 0x10000>;
+		interrupts = <0x00 0x0b 0x04 0x00>;
+		arasan,soc-ctl-syscon = <0x1a>;
+		assigned-clocks = <0x08 0x4e>;
+		assigned-clock-rates = <0xbebc200>;
+		clocks = <0x08 0x4e 0x08 0xf0>;
+		clock-names = "clk_xin\0clk_ahb";
+		clock-output-names = "emmc_cardclock";
+		#clock-cells = <0x00>;
+		phys = <0x29>;
+		phy-names = "phy_arasan";
+		power-domains = <0x19 0x17>;
+		disable-cqe-dcmd;
+		status = "okay";
+		bus-width = <0x08>;
+		mmc-hs400-1_8v;
+		supports-emmc;
+		non-removable;
+		keep-power-in-suspend;
+		mmc-hs400-enhanced-strobe;
+		phandle = <0x94>;
+	};
+
+	usb@fe380000 {
+		compatible = "generic-ehci";
+		reg = <0x00 0xfe380000 0x00 0x20000>;
+		interrupts = <0x00 0x1a 0x04 0x00>;
+		clocks = <0x08 0x1c8 0x08 0x1c9 0x2a>;
+		phys = <0x2b>;
+		phy-names = "usb";
+		status = "okay";
+		phandle = <0xcb>;
+	};
+
+	usb@fe3a0000 {
+		compatible = "generic-ohci";
+		reg = <0x00 0xfe3a0000 0x00 0x20000>;
+		interrupts = <0x00 0x1c 0x04 0x00>;
+		clocks = <0x08 0x1c8 0x08 0x1c9 0x2a>;
+		phys = <0x2b>;
+		phy-names = "usb";
+		status = "okay";
+		phandle = <0xcc>;
+	};
+
+	usb@fe3c0000 {
+		compatible = "generic-ehci";
+		reg = <0x00 0xfe3c0000 0x00 0x20000>;
+		interrupts = <0x00 0x1e 0x04 0x00>;
+		clocks = <0x08 0x1ca 0x08 0x1cb 0x2c>;
+		phys = <0x2d>;
+		phy-names = "usb";
+		status = "okay";
+		phandle = <0xcd>;
+	};
+
+	usb@fe3e0000 {
+		compatible = "generic-ohci";
+		reg = <0x00 0xfe3e0000 0x00 0x20000>;
+		interrupts = <0x00 0x20 0x04 0x00>;
+		clocks = <0x08 0x1ca 0x08 0x1cb 0x2c>;
+		phys = <0x2d>;
+		phy-names = "usb";
+		status = "okay";
+		phandle = <0xce>;
+	};
+
+	debug@fe430000 {
+		compatible = "arm,coresight-cpu-debug\0arm,primecell";
+		reg = <0x00 0xfe430000 0x00 0x1000>;
+		clocks = <0x08 0x14d>;
+		clock-names = "apb_pclk";
+		cpu = <0x02>;
+	};
+
+	debug@fe432000 {
+		compatible = "arm,coresight-cpu-debug\0arm,primecell";
+		reg = <0x00 0xfe432000 0x00 0x1000>;
+		clocks = <0x08 0x14d>;
+		clock-names = "apb_pclk";
+		cpu = <0x03>;
+	};
+
+	debug@fe434000 {
+		compatible = "arm,coresight-cpu-debug\0arm,primecell";
+		reg = <0x00 0xfe434000 0x00 0x1000>;
+		clocks = <0x08 0x14d>;
+		clock-names = "apb_pclk";
+		cpu = <0x04>;
+	};
+
+	debug@fe436000 {
+		compatible = "arm,coresight-cpu-debug\0arm,primecell";
+		reg = <0x00 0xfe436000 0x00 0x1000>;
+		clocks = <0x08 0x14d>;
+		clock-names = "apb_pclk";
+		cpu = <0x05>;
+	};
+
+	debug@fe610000 {
+		compatible = "arm,coresight-cpu-debug\0arm,primecell";
+		reg = <0x00 0xfe610000 0x00 0x1000>;
+		clocks = <0x08 0x14c>;
+		clock-names = "apb_pclk";
+		cpu = <0x06>;
+	};
+
+	debug@fe710000 {
+		compatible = "arm,coresight-cpu-debug\0arm,primecell";
+		reg = <0x00 0xfe710000 0x00 0x1000>;
+		clocks = <0x08 0x14c>;
+		clock-names = "apb_pclk";
+		cpu = <0x07>;
+	};
+
+	usb@fe800000 {
+		compatible = "rockchip,rk3399-dwc3";
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+		clocks = <0x08 0x81 0x08 0x83 0x08 0xf6 0x08 0xf8 0x08 0xf4 0x08 0xf9>;
+		clock-names = "ref_clk\0suspend_clk\0bus_clk\0aclk_usb3_rksoc_axi_perf\0aclk_usb3\0grf_clk";
+		resets = <0x08 0x125>;
+		reset-names = "usb3-otg";
+		status = "okay";
+		phandle = <0xcf>;
+
+		usb@fe800000 {
+			compatible = "snps,dwc3";
+			reg = <0x00 0xfe800000 0x00 0x100000>;
+			interrupts = <0x00 0x69 0x04 0x00>;
+			clocks = <0x08 0x81 0x08 0xf6 0x08 0x83>;
+			clock-names = "ref\0bus_early\0suspend";
+			dr_mode = "otg";
+			phys = <0x2e 0x2f>;
+			phy-names = "usb2-phy\0usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			power-domains = <0x19 0x18>;
+			status = "okay";
+			phandle = <0xd0>;
+		};
+	};
+
+	usb@fe900000 {
+		compatible = "rockchip,rk3399-dwc3";
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+		clocks = <0x08 0x82 0x08 0x84 0x08 0xf7 0x08 0xf8 0x08 0xf4 0x08 0xf9>;
+		clock-names = "ref_clk\0suspend_clk\0bus_clk\0aclk_usb3_rksoc_axi_perf\0aclk_usb3\0grf_clk";
+		resets = <0x08 0x126>;
+		reset-names = "usb3-otg";
+		status = "okay";
+		phandle = <0xd1>;
+
+		usb@fe900000 {
+			compatible = "snps,dwc3";
+			reg = <0x00 0xfe900000 0x00 0x100000>;
+			interrupts = <0x00 0x6e 0x04 0x00>;
+			clocks = <0x08 0x82 0x08 0xf7 0x08 0x84>;
+			clock-names = "ref\0bus_early\0suspend";
+			dr_mode = "host";
+			phys = <0x30 0x31>;
+			phy-names = "usb2-phy\0usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			power-domains = <0x19 0x18>;
+			status = "okay";
+			phandle = <0xd2>;
+		};
+	};
+
+	dp@fec00000 {
+		compatible = "rockchip,rk3399-cdn-dp";
+		reg = <0x00 0xfec00000 0x00 0x100000>;
+		interrupts = <0x00 0x09 0x04 0x00>;
+		assigned-clocks = <0x08 0x72 0x08 0xa1>;
+		assigned-clock-rates = <0x5f5e100 0xbebc200>;
+		clocks = <0x08 0x72 0x08 0x175 0x08 0xa1 0x08 0x16f>;
+		clock-names = "core-clk\0pclk\0spdif\0grf";
+		phys = <0x32 0x33>;
+		power-domains = <0x19 0x15>;
+		resets = <0x08 0x103 0x08 0x148 0x08 0x14a 0x08 0xfd>;
+		reset-names = "spdif\0dptx\0apb\0core";
+		rockchip,grf = <0x1a>;
+		#sound-dai-cells = <0x01>;
+		status = "disabled";
+		phandle = <0xd3>;
+
+		ports {
+
+			port {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				phandle = <0xd4>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0x34>;
+					phandle = <0xa4>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0x35>;
+					phandle = <0x9e>;
+				};
+			};
+		};
+	};
+
+	interrupt-controller@fee00000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <0x04>;
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+		interrupt-controller;
+		reg = <0x00 0xfee00000 0x00 0x10000 0x00 0xfef00000 0x00 0xc0000 0x00 0xfff00000 0x00 0x10000 0x00 0xfff10000 0x00 0x10000 0x00 0xfff20000 0x00 0x10000>;
+		interrupts = <0x01 0x09 0x04 0x00>;
+		phandle = <0x01>;
+
+		interrupt-controller@fee20000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <0x01>;
+			reg = <0x00 0xfee20000 0x00 0x20000>;
+			phandle = <0x16>;
+		};
+
+		ppi-partitions {
+
+			interrupt-partition-0 {
+				affinity = <0x02 0x03 0x04 0x05>;
+				phandle = <0x13>;
+			};
+
+			interrupt-partition-1 {
+				affinity = <0x06 0x07>;
+				phandle = <0x14>;
+			};
+		};
+	};
+
+	saradc@ff100000 {
+		compatible = "rockchip,rk3399-saradc";
+		reg = <0x00 0xff100000 0x00 0x100>;
+		interrupts = <0x00 0x3e 0x04 0x00>;
+		#io-channel-cells = <0x01>;
+		clocks = <0x08 0x50 0x08 0x165>;
+		clock-names = "saradc\0apb_pclk";
+		resets = <0x08 0xd4>;
+		reset-names = "saradc-apb";
+		status = "okay";
+		vref-supply = <0x36>;
+		phandle = <0xd5>;
+	};
+
+	i2c@ff110000 {
+		compatible = "rockchip,rk3399-i2c";
+		reg = <0x00 0xff110000 0x00 0x1000>;
+		assigned-clocks = <0x08 0x41>;
+		assigned-clock-rates = <0xbebc200>;
+		clocks = <0x08 0x41 0x08 0x155>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x3b 0x04 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x37>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+		i2c-scl-rising-time-ns = <0x12c>;
+		i2c-scl-falling-time-ns = <0x0f>;
+		phandle = <0xd6>;
+
+		codec@11 {
+			compatible = "everest,es8316";
+			reg = <0x11>;
+			clocks = <0x08 0x59>;
+			clock-names = "mclk";
+			#sound-dai-cells = <0x00>;
+			phandle = <0xd7>;
+
+			port {
+
+				endpoint {
+					remote-endpoint = <0x38>;
+					phandle = <0x98>;
+				};
+			};
+		};
+
+		rtc@32 {
+			compatible = "ricoh,rs5c372a";
+			reg = <0x32>;
+		};
+	};
+
+	i2c@ff120000 {
+		compatible = "rockchip,rk3399-i2c";
+		reg = <0x00 0xff120000 0x00 0x1000>;
+		assigned-clocks = <0x08 0x42>;
+		assigned-clock-rates = <0xbebc200>;
+		clocks = <0x08 0x42 0x08 0x156>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x23 0x04 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x39>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0xd8>;
+	};
+
+	i2c@ff130000 {
+		compatible = "rockchip,rk3399-i2c";
+		reg = <0x00 0xff130000 0x00 0x1000>;
+		assigned-clocks = <0x08 0x43>;
+		assigned-clock-rates = <0xbebc200>;
+		clocks = <0x08 0x43 0x08 0x157>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x22 0x04 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x3a>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+		phandle = <0xd9>;
+	};
+
+	i2c@ff140000 {
+		compatible = "rockchip,rk3399-i2c";
+		reg = <0x00 0xff140000 0x00 0x1000>;
+		assigned-clocks = <0x08 0x44>;
+		assigned-clock-rates = <0xbebc200>;
+		clocks = <0x08 0x44 0x08 0x158>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x26 0x04 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x3b>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0xda>;
+	};
+
+	i2c@ff150000 {
+		compatible = "rockchip,rk3399-i2c";
+		reg = <0x00 0xff150000 0x00 0x1000>;
+		assigned-clocks = <0x08 0x45>;
+		assigned-clock-rates = <0xbebc200>;
+		clocks = <0x08 0x45 0x08 0x159>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x25 0x04 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x3c>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0xdb>;
+	};
+
+	i2c@ff160000 {
+		compatible = "rockchip,rk3399-i2c";
+		reg = <0x00 0xff160000 0x00 0x1000>;
+		assigned-clocks = <0x08 0x46>;
+		assigned-clock-rates = <0xbebc200>;
+		clocks = <0x08 0x46 0x08 0x15a>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x24 0x04 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x3d>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+		i2c-scl-rising-time-ns = <0xa0>;
+		i2c-scl-falling-time-ns = <0x1e>;
+		phandle = <0xab>;
+	};
+
+	serial@ff180000 {
+		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xff180000 0x00 0x100>;
+		clocks = <0x08 0x51 0x08 0x160>;
+		clock-names = "baudclk\0apb_pclk";
+		interrupts = <0x00 0x63 0x04 0x00>;
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x3e 0x3f 0x40>;
+		status = "okay";
+		phandle = <0xdc>;
+
+		bluetooth {
+			compatible = "brcm,bcm4345c5";
+			clocks = <0x41 0x01>;
+			clock-names = "lpo";
+			device-wakeup-gpios = <0x18 0x1a 0x00>;
+			host-wakeup-gpios = <0x23 0x04 0x00>;
+			shutdown-gpios = <0x23 0x09 0x00>;
+			max-speed = <0x16e360>;
+			pinctrl-names = "default";
+			pinctrl-0 = <0x42 0x43 0x44>;
+		};
+	};
+
+	serial@ff190000 {
+		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xff190000 0x00 0x100>;
+		clocks = <0x08 0x52 0x08 0x161>;
+		clock-names = "baudclk\0apb_pclk";
+		interrupts = <0x00 0x62 0x04 0x00>;
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x45>;
+		status = "disabled";
+		phandle = <0xdd>;
+	};
+
+	serial@ff1a0000 {
+		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xff1a0000 0x00 0x100>;
+		clocks = <0x08 0x53 0x08 0x162>;
+		clock-names = "baudclk\0apb_pclk";
+		interrupts = <0x00 0x64 0x04 0x00>;
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x46>;
+		status = "okay";
+		phandle = <0xde>;
+	};
+
+	serial@ff1b0000 {
+		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xff1b0000 0x00 0x100>;
+		clocks = <0x08 0x54 0x08 0x163>;
+		clock-names = "baudclk\0apb_pclk";
+		interrupts = <0x00 0x65 0x04 0x00>;
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x47>;
+		status = "disabled";
+		phandle = <0xdf>;
+	};
+
+	spi@ff1c0000 {
+		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
+		reg = <0x00 0xff1c0000 0x00 0x1000>;
+		clocks = <0x08 0x47 0x08 0x15b>;
+		clock-names = "spiclk\0apb_pclk";
+		interrupts = <0x00 0x44 0x04 0x00>;
+		dmas = <0x48 0x0a 0x48 0x0b>;
+		dma-names = "tx\0rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x49 0x4a 0x4b 0x4c>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0xe0>;
+	};
+
+	spi@ff1d0000 {
+		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
+		reg = <0x00 0xff1d0000 0x00 0x1000>;
+		clocks = <0x08 0x48 0x08 0x15c>;
+		clock-names = "spiclk\0apb_pclk";
+		interrupts = <0x00 0x35 0x04 0x00>;
+		dmas = <0x48 0x0c 0x48 0x0d>;
+		dma-names = "tx\0rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x4d 0x4e 0x4f 0x50>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0xe1>;
+	};
+
+	spi@ff1e0000 {
+		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
+		reg = <0x00 0xff1e0000 0x00 0x1000>;
+		clocks = <0x08 0x49 0x08 0x15d>;
+		clock-names = "spiclk\0apb_pclk";
+		interrupts = <0x00 0x34 0x04 0x00>;
+		dmas = <0x48 0x0e 0x48 0x0f>;
+		dma-names = "tx\0rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x51 0x52 0x53 0x54>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0xe2>;
+	};
+
+	spi@ff1f0000 {
+		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
+		reg = <0x00 0xff1f0000 0x00 0x1000>;
+		clocks = <0x08 0x4a 0x08 0x15e>;
+		clock-names = "spiclk\0apb_pclk";
+		interrupts = <0x00 0x43 0x04 0x00>;
+		dmas = <0x48 0x12 0x48 0x13>;
+		dma-names = "tx\0rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x55 0x56 0x57 0x58>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0xe3>;
+	};
+
+	spi@ff200000 {
+		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
+		reg = <0x00 0xff200000 0x00 0x1000>;
+		clocks = <0x08 0x4b 0x08 0x15f>;
+		clock-names = "spiclk\0apb_pclk";
+		interrupts = <0x00 0x84 0x04 0x00>;
+		dmas = <0x59 0x08 0x59 0x09>;
+		dma-names = "tx\0rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x5a 0x5b 0x5c 0x5d>;
+		power-domains = <0x19 0x1c>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0xe4>;
+	};
+
+	thermal-zones {
+		phandle = <0xe5>;
+
+		cpu-thermal {
+			polling-delay-passive = <0x64>;
+			polling-delay = <0x3e8>;
+			thermal-sensors = <0x5e 0x00>;
+			phandle = <0xe6>;
+
+			trips {
+
+				cpu_alert0 {
+					temperature = <0x11170>;
+					hysteresis = <0x7d0>;
+					type = "passive";
+					phandle = <0x5f>;
+				};
+
+				cpu_alert1 {
+					temperature = <0x124f8>;
+					hysteresis = <0x7d0>;
+					type = "passive";
+					phandle = <0x60>;
+				};
+
+				cpu_crit {
+					temperature = <0x17318>;
+					hysteresis = <0x7d0>;
+					type = "critical";
+					phandle = <0xe7>;
+				};
+			};
+
+			cooling-maps {
+
+				map0 {
+					trip = <0x5f>;
+					cooling-device = <0x06 0xffffffff 0xffffffff 0x07 0xffffffff 0xffffffff>;
+				};
+
+				map1 {
+					trip = <0x60>;
+					cooling-device = <0x02 0xffffffff 0xffffffff 0x03 0xffffffff 0xffffffff 0x04 0xffffffff 0xffffffff 0x05 0xffffffff 0xffffffff 0x06 0xffffffff 0xffffffff 0x07 0xffffffff 0xffffffff>;
+				};
+			};
+		};
+
+		gpu-thermal {
+			polling-delay-passive = <0x64>;
+			polling-delay = <0x3e8>;
+			thermal-sensors = <0x5e 0x01>;
+			phandle = <0xe8>;
+
+			trips {
+
+				gpu_alert0 {
+					temperature = <0x124f8>;
+					hysteresis = <0x7d0>;
+					type = "passive";
+					phandle = <0x61>;
+				};
+
+				gpu_crit {
+					temperature = <0x17318>;
+					hysteresis = <0x7d0>;
+					type = "critical";
+					phandle = <0xe9>;
+				};
+			};
+
+			cooling-maps {
+
+				map0 {
+					trip = <0x61>;
+					cooling-device = <0x62 0xffffffff 0xffffffff>;
+				};
+			};
+		};
+	};
+
+	tsadc@ff260000 {
+		compatible = "rockchip,rk3399-tsadc";
+		reg = <0x00 0xff260000 0x00 0x100>;
+		interrupts = <0x00 0x61 0x04 0x00>;
+		assigned-clocks = <0x08 0x4f>;
+		assigned-clock-rates = <0xb71b0>;
+		clocks = <0x08 0x4f 0x08 0x164>;
+		clock-names = "tsadc\0apb_pclk";
+		resets = <0x08 0xe8>;
+		reset-names = "tsadc-apb";
+		rockchip,grf = <0x1a>;
+		rockchip,hw-tshut-temp = <0x17318>;
+		pinctrl-names = "init\0default\0sleep";
+		pinctrl-0 = <0x63>;
+		pinctrl-1 = <0x64>;
+		pinctrl-2 = <0x63>;
+		#thermal-sensor-cells = <0x01>;
+		status = "okay";
+		rockchip,hw-tshut-mode = <0x01>;
+		rockchip,hw-tshut-polarity = <0x01>;
+		phandle = <0x5e>;
+	};
+
+	qos@ffa58000 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffa58000 0x00 0x20>;
+		phandle = <0x6c>;
+	};
+
+	qos@ffa5c000 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffa5c000 0x00 0x20>;
+		phandle = <0x6d>;
+	};
+
+	qos@ffa60080 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffa60080 0x00 0x20>;
+		phandle = <0xea>;
+	};
+
+	qos@ffa60100 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffa60100 0x00 0x20>;
+		phandle = <0xeb>;
+	};
+
+	qos@ffa60180 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffa60180 0x00 0x20>;
+		phandle = <0xec>;
+	};
+
+	qos@ffa70000 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffa70000 0x00 0x20>;
+		phandle = <0x70>;
+	};
+
+	qos@ffa70080 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffa70080 0x00 0x20>;
+		phandle = <0x71>;
+	};
+
+	qos@ffa74000 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffa74000 0x00 0x20>;
+		phandle = <0x6e>;
+	};
+
+	qos@ffa76000 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffa76000 0x00 0x20>;
+		phandle = <0x6f>;
+	};
+
+	qos@ffa90000 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffa90000 0x00 0x20>;
+		phandle = <0x72>;
+	};
+
+	qos@ffa98000 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffa98000 0x00 0x20>;
+		phandle = <0x65>;
+	};
+
+	qos@ffaa0000 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffaa0000 0x00 0x20>;
+		phandle = <0x73>;
+	};
+
+	qos@ffaa0080 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffaa0080 0x00 0x20>;
+		phandle = <0x74>;
+	};
+
+	qos@ffaa8000 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffaa8000 0x00 0x20>;
+		phandle = <0x75>;
+	};
+
+	qos@ffaa8080 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffaa8080 0x00 0x20>;
+		phandle = <0x76>;
+	};
+
+	qos@ffab0000 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffab0000 0x00 0x20>;
+		phandle = <0x66>;
+	};
+
+	qos@ffab0080 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffab0080 0x00 0x20>;
+		phandle = <0x67>;
+	};
+
+	qos@ffab8000 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffab8000 0x00 0x20>;
+		phandle = <0x68>;
+	};
+
+	qos@ffac0000 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffac0000 0x00 0x20>;
+		phandle = <0x69>;
+	};
+
+	qos@ffac0080 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffac0080 0x00 0x20>;
+		phandle = <0x6a>;
+	};
+
+	qos@ffac8000 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffac8000 0x00 0x20>;
+		phandle = <0x77>;
+	};
+
+	qos@ffac8080 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffac8080 0x00 0x20>;
+		phandle = <0x78>;
+	};
+
+	qos@ffad0000 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffad0000 0x00 0x20>;
+		phandle = <0x79>;
+	};
+
+	qos@ffad8080 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffad8080 0x00 0x20>;
+		phandle = <0xed>;
+	};
+
+	qos@ffae0000 {
+		compatible = "rockchip,rk3399-qos\0syscon";
+		reg = <0x00 0xffae0000 0x00 0x20>;
+		phandle = <0x6b>;
+	};
+
+	power-management@ff310000 {
+		compatible = "rockchip,rk3399-pmu\0syscon\0simple-mfd";
+		reg = <0x00 0xff310000 0x00 0x1000>;
+		phandle = <0xee>;
+
+		power-controller {
+			compatible = "rockchip,rk3399-power-controller";
+			#power-domain-cells = <0x01>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			phandle = <0x19>;
+
+			power-domain@34 {
+				reg = <0x22>;
+				clocks = <0x08 0xe1 0x08 0x1dd>;
+				pm_qos = <0x65>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@33 {
+				reg = <0x21>;
+				clocks = <0x08 0xdc 0x08 0x1e5>;
+				pm_qos = <0x66 0x67>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@31 {
+				reg = <0x1f>;
+				clocks = <0x08 0xeb 0x08 0x1ea>;
+				pm_qos = <0x68>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@32 {
+				reg = <0x20>;
+				clocks = <0x08 0xed 0x08 0x1ec 0x08 0x9f 0x08 0x9e>;
+				pm_qos = <0x69 0x6a>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@35 {
+				reg = <0x23>;
+				clocks = <0x08 0xd0>;
+				pm_qos = <0x6b>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@25 {
+				reg = <0x19>;
+				clocks = <0x08 0x16c>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@23 {
+				reg = <0x17>;
+				clocks = <0x08 0xf0>;
+				pm_qos = <0x6c>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@22 {
+				reg = <0x16>;
+				clocks = <0x08 0xd5 0x08 0x166>;
+				pm_qos = <0x6d>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@27 {
+				reg = <0x1b>;
+				clocks = <0x08 0x1ce 0x08 0x4c>;
+				pm_qos = <0x6e>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@28 {
+				reg = <0x1c>;
+				clocks = <0x08 0x1ee>;
+				pm_qos = <0x6f>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@8 {
+				reg = <0x08>;
+				clocks = <0x08 0x7e 0x08 0x7d>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@9 {
+				reg = <0x09>;
+				clocks = <0x08 0x80 0x08 0x7f>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@24 {
+				reg = <0x18>;
+				clocks = <0x08 0xf4>;
+				pm_qos = <0x70 0x71>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@15 {
+				reg = <0x0f>;
+				#power-domain-cells = <0x01>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				power-domain@21 {
+					reg = <0x15>;
+					clocks = <0x08 0xde 0x08 0x1e7 0x08 0x172>;
+					pm_qos = <0x72>;
+					#power-domain-cells = <0x00>;
+				};
+
+				power-domain@19 {
+					reg = <0x13>;
+					clocks = <0x08 0xe5 0x08 0x1df>;
+					pm_qos = <0x73 0x74>;
+					#power-domain-cells = <0x00>;
+				};
+
+				power-domain@20 {
+					reg = <0x14>;
+					clocks = <0x08 0xe6 0x08 0x1e0>;
+					pm_qos = <0x75 0x76>;
+					#power-domain-cells = <0x00>;
+				};
+
+				power-domain@16 {
+					reg = <0x10>;
+					#power-domain-cells = <0x01>;
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+
+					power-domain@17 {
+						reg = <0x11>;
+						clocks = <0x08 0xd9 0x08 0x1d9>;
+						pm_qos = <0x77 0x78>;
+						#power-domain-cells = <0x00>;
+					};
+
+					power-domain@18 {
+						reg = <0x12>;
+						clocks = <0x08 0xdb 0x08 0x1db>;
+						pm_qos = <0x79>;
+						#power-domain-cells = <0x00>;
+					};
+				};
+			};
+		};
+	};
+
+	syscon@ff320000 {
+		compatible = "rockchip,rk3399-pmugrf\0syscon\0simple-mfd";
+		reg = <0x00 0xff320000 0x00 0x1000>;
+		phandle = <0x11>;
+
+		io-domains {
+			compatible = "rockchip,rk3399-pmu-io-voltage-domain";
+			status = "okay";
+			pmu1830-supply = <0x7a>;
+			phandle = <0xef>;
+		};
+	};
+
+	spi@ff350000 {
+		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
+		reg = <0x00 0xff350000 0x00 0x1000>;
+		clocks = <0x7b 0x03 0x7b 0x1f>;
+		clock-names = "spiclk\0apb_pclk";
+		interrupts = <0x00 0x3c 0x04 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x7c 0x7d 0x7e 0x7f>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0xf0>;
+	};
+
+	serial@ff370000 {
+		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xff370000 0x00 0x100>;
+		clocks = <0x7b 0x06 0x7b 0x22>;
+		clock-names = "baudclk\0apb_pclk";
+		interrupts = <0x00 0x66 0x04 0x00>;
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x80>;
+		status = "disabled";
+		phandle = <0xf1>;
+	};
+
+	i2c@ff3c0000 {
+		compatible = "rockchip,rk3399-i2c";
+		reg = <0x00 0xff3c0000 0x00 0x1000>;
+		assigned-clocks = <0x7b 0x09>;
+		assigned-clock-rates = <0xbebc200>;
+		clocks = <0x7b 0x09 0x7b 0x1b>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x39 0x04 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x81>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+		clock-frequency = <0x61a80>;
+		i2c-scl-rising-time-ns = <0xa0>;
+		i2c-scl-falling-time-ns = <0x1e>;
+		phandle = <0xf2>;
+
+		pmic@1b {
+			compatible = "rockchip,rk808";
+			reg = <0x1b>;
+			interrupt-parent = <0x18>;
+			interrupts = <0x0a 0x08>;
+			#clock-cells = <0x01>;
+			clock-output-names = "xin32k\0rk808-clkout2";
+			pinctrl-names = "default";
+			pinctrl-0 = <0x82>;
+			rockchip,system-power-controller;
+			wakeup-source;
+			vcc1-supply = <0x83>;
+			vcc2-supply = <0x83>;
+			vcc3-supply = <0x83>;
+			vcc4-supply = <0x83>;
+			vcc6-supply = <0x83>;
+			vcc7-supply = <0x83>;
+			vcc8-supply = <0x83>;
+			vcc9-supply = <0x83>;
+			vcc10-supply = <0x83>;
+			vcc11-supply = <0x83>;
+			vcc12-supply = <0x83>;
+			vcc13-supply = <0x83>;
+			vcc14-supply = <0x83>;
+			vddio-supply = <0x7a>;
+			phandle = <0x41>;
+
+			regulators {
+
+				DCDC_REG1 {
+					regulator-name = "vdd_center";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xaae60>;
+					regulator-max-microvolt = <0x149970>;
+					regulator-ramp-delay = <0x1771>;
+					phandle = <0xf3>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				DCDC_REG2 {
+					regulator-name = "vdd_cpu_l";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xaae60>;
+					regulator-max-microvolt = <0x149970>;
+					regulator-ramp-delay = <0x1771>;
+					phandle = <0x0c>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				DCDC_REG3 {
+					regulator-name = "vcc_ddr";
+					regulator-always-on;
+					regulator-boot-on;
+					phandle = <0xf4>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+					};
+				};
+
+				DCDC_REG4 {
+					regulator-name = "vcc_1v8";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x1b7740>;
+					phandle = <0x36>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0x1b7740>;
+					};
+				};
+
+				LDO_REG1 {
+					regulator-name = "vcc1v8_dvp";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x1b7740>;
+					phandle = <0x90>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				LDO_REG2 {
+					regulator-name = "vcc3v0_tp";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x2dc6c0>;
+					regulator-max-microvolt = <0x2dc6c0>;
+					phandle = <0xf5>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				LDO_REG3 {
+					regulator-name = "vcc1v8_pmu";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x1b7740>;
+					phandle = <0xf6>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0x1b7740>;
+					};
+				};
+
+				LDO_REG4 {
+					regulator-name = "vcc_sdio";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x2dc6c0>;
+					regulator-init-microvolt = <0x2dc6c0>;
+					phandle = <0x28>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0x2dc6c0>;
+					};
+				};
+
+				LDO_REG5 {
+					regulator-name = "vcca3v0_codec";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x2dc6c0>;
+					regulator-max-microvolt = <0x2dc6c0>;
+					phandle = <0xf7>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				LDO_REG6 {
+					regulator-name = "vcc_1v5";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x16e360>;
+					regulator-max-microvolt = <0x16e360>;
+					phandle = <0xf8>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0x16e360>;
+					};
+				};
+
+				LDO_REG7 {
+					regulator-name = "vcca1v8_codec";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x1b7740>;
+					phandle = <0x91>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				LDO_REG8 {
+					regulator-name = "vcc_3v0";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x2dc6c0>;
+					regulator-max-microvolt = <0x2dc6c0>;
+					phandle = <0x7a>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0x2dc6c0>;
+					};
+				};
+
+				SWITCH_REG1 {
+					regulator-name = "vcc3v3_s3";
+					regulator-always-on;
+					regulator-boot-on;
+					phandle = <0x1c>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				SWITCH_REG2 {
+					regulator-name = "vcc3v3_s0";
+					regulator-always-on;
+					regulator-boot-on;
+					phandle = <0xf9>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+			};
+		};
+
+		regulator@40 {
+			compatible = "silergy,syr827";
+			reg = <0x40>;
+			fcs,suspend-voltage-selector = <0x01>;
+			pinctrl-names = "default";
+			pinctrl-0 = <0x84>;
+			regulator-name = "vdd_cpu_b";
+			regulator-min-microvolt = <0xadf34>;
+			regulator-max-microvolt = <0x16e360>;
+			regulator-ramp-delay = <0x3e8>;
+			regulator-always-on;
+			regulator-boot-on;
+			vin-supply = <0x83>;
+			phandle = <0x0e>;
+
+			regulator-state-mem {
+				regulator-off-in-suspend;
+			};
+		};
+
+		regulator@41 {
+			compatible = "silergy,syr828";
+			reg = <0x41>;
+			fcs,suspend-voltage-selector = <0x01>;
+			pinctrl-names = "default";
+			pinctrl-0 = <0x85>;
+			regulator-name = "vdd_gpu";
+			regulator-min-microvolt = <0xadf34>;
+			regulator-max-microvolt = <0x16e360>;
+			regulator-ramp-delay = <0x3e8>;
+			regulator-always-on;
+			regulator-boot-on;
+			vin-supply = <0x83>;
+			phandle = <0xb6>;
+
+			regulator-state-mem {
+				regulator-off-in-suspend;
+			};
+		};
+	};
+
+	i2c@ff3d0000 {
+		compatible = "rockchip,rk3399-i2c";
+		reg = <0x00 0xff3d0000 0x00 0x1000>;
+		assigned-clocks = <0x7b 0x0a>;
+		assigned-clock-rates = <0xbebc200>;
+		clocks = <0x7b 0x0a 0x7b 0x1c>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x38 0x04 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x86>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+		clock-frequency = <0x61a80>;
+		i2c-scl-rising-time-ns = <0xa0>;
+		i2c-scl-falling-time-ns = <0x1e>;
+		phandle = <0xfa>;
+	};
+
+	i2c@ff3e0000 {
+		compatible = "rockchip,rk3399-i2c";
+		reg = <0x00 0xff3e0000 0x00 0x1000>;
+		assigned-clocks = <0x7b 0x0b>;
+		assigned-clock-rates = <0xbebc200>;
+		clocks = <0x7b 0x0b 0x7b 0x1d>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x3a 0x04 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x87>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0xfb>;
+	};
+
+	pwm@ff420000 {
+		compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm";
+		reg = <0x00 0xff420000 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x88>;
+		clocks = <0x7b 0x1e>;
+		status = "okay";
+		phandle = <0xfc>;
+	};
+
+	pwm@ff420010 {
+		compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm";
+		reg = <0x00 0xff420010 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x89>;
+		clocks = <0x7b 0x1e>;
+		status = "okay";
+		phandle = <0xfd>;
+	};
+
+	pwm@ff420020 {
+		compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm";
+		reg = <0x00 0xff420020 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x8a>;
+		clocks = <0x7b 0x1e>;
+		status = "disabled";
+		phandle = <0xc3>;
+	};
+
+	pwm@ff420030 {
+		compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm";
+		reg = <0x00 0xff420030 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x8b>;
+		clocks = <0x7b 0x1e>;
+		status = "disabled";
+		phandle = <0xfe>;
+	};
+
+	dfi@ff630000 {
+		reg = <0x00 0xff630000 0x00 0x4000>;
+		compatible = "rockchip,rk3399-dfi";
+		rockchip,pmu = <0x11>;
+		interrupts = <0x00 0x83 0x04 0x00>;
+		clocks = <0x08 0x179>;
+		clock-names = "pclk_ddr_mon";
+		status = "disabled";
+		phandle = <0x12>;
+	};
+
+	video-codec@ff650000 {
+		compatible = "rockchip,rk3399-vpu";
+		reg = <0x00 0xff650000 0x00 0x800>;
+		interrupts = <0x00 0x72 0x04 0x00 0x00 0x71 0x04 0x00>;
+		interrupt-names = "vepu\0vdpu";
+		clocks = <0x08 0xeb 0x08 0x1ea>;
+		clock-names = "aclk\0hclk";
+		iommus = <0x8c>;
+		power-domains = <0x19 0x1f>;
+		phandle = <0xff>;
+	};
+
+	iommu@ff650800 {
+		compatible = "rockchip,iommu";
+		reg = <0x00 0xff650800 0x00 0x40>;
+		interrupts = <0x00 0x73 0x04 0x00>;
+		clocks = <0x08 0xeb 0x08 0x1ea>;
+		clock-names = "aclk\0iface";
+		#iommu-cells = <0x00>;
+		power-domains = <0x19 0x1f>;
+		phandle = <0x8c>;
+	};
+
+	video-codec@ff660000 {
+		compatible = "rockchip,rk3399-vdec";
+		reg = <0x00 0xff660000 0x00 0x480>;
+		interrupts = <0x00 0x74 0x04 0x00>;
+		clocks = <0x08 0xed 0x08 0x1ec 0x08 0x9f 0x08 0x9e>;
+		clock-names = "axi\0ahb\0cabac\0core";
+		iommus = <0x8d>;
+		power-domains = <0x19 0x20>;
+		resets = <0x08 0x5b 0x08 0x59 0x08 0x5c 0x08 0x5d 0x08 0x58 0x08 0x5a>;
+		reset-names = "video_h\0video_a\0video_core\0video_cabac\0niu_a\0niu_h";
+		phandle = <0x100>;
+	};
+
+	iommu@ff660480 {
+		compatible = "rockchip,iommu";
+		reg = <0x00 0xff660480 0x00 0x40 0x00 0xff6604c0 0x00 0x40>;
+		interrupts = <0x00 0x75 0x04 0x00>;
+		clocks = <0x08 0xed 0x08 0x1ec>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x19 0x20>;
+		#iommu-cells = <0x00>;
+		phandle = <0x8d>;
+	};
+
+	iep@ff670000 {
+		compatible = "rockchip,rk3399-iep\0rockchip,rk3228-iep";
+		reg = <0x00 0xff670000 0x00 0x800>;
+		interrupts = <0x00 0x2a 0x04 0x00>;
+		interrupt-names = "iep";
+		clocks = <0x08 0xe1 0x08 0x1dd>;
+		clock-names = "axi\0ahb";
+		power-domains = <0x19 0x22>;
+		iommus = <0x8e>;
+		phandle = <0x101>;
+	};
+
+	iommu@ff670800 {
+		compatible = "rockchip,iommu";
+		reg = <0x00 0xff670800 0x00 0x40>;
+		interrupts = <0x00 0x2a 0x04 0x00>;
+		clocks = <0x08 0xe1 0x08 0x1dd>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x19 0x22>;
+		#iommu-cells = <0x00>;
+		phandle = <0x8e>;
+	};
+
+	rga@ff680000 {
+		compatible = "rockchip,rk3399-rga";
+		reg = <0x00 0xff680000 0x00 0x10000>;
+		interrupts = <0x00 0x37 0x04 0x00>;
+		clocks = <0x08 0xdc 0x08 0x1e5 0x08 0x6d>;
+		clock-names = "aclk\0hclk\0sclk";
+		resets = <0x08 0x6a 0x08 0x67 0x08 0x69>;
+		reset-names = "core\0axi\0ahb";
+		power-domains = <0x19 0x21>;
+		phandle = <0x102>;
+	};
+
+	efuse@ff690000 {
+		compatible = "rockchip,rk3399-efuse";
+		reg = <0x00 0xff690000 0x00 0x80>;
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+		clocks = <0x08 0x17d>;
+		clock-names = "pclk_efuse";
+		phandle = <0x103>;
+
+		cpu-id@7 {
+			reg = <0x07 0x10>;
+			phandle = <0x104>;
+		};
+
+		cpu-leakage@17 {
+			reg = <0x17 0x01>;
+			phandle = <0x105>;
+		};
+
+		gpu-leakage@18 {
+			reg = <0x18 0x01>;
+			phandle = <0x106>;
+		};
+
+		center-leakage@19 {
+			reg = <0x19 0x01>;
+			phandle = <0x107>;
+		};
+
+		cpu-leakage@1a {
+			reg = <0x1a 0x01>;
+			phandle = <0x108>;
+		};
+
+		logic-leakage@1b {
+			reg = <0x1b 0x01>;
+			phandle = <0x109>;
+		};
+
+		wafer-info@1c {
+			reg = <0x1c 0x01>;
+			phandle = <0x10a>;
+		};
+	};
+
+	dma-controller@ff6d0000 {
+		compatible = "arm,pl330\0arm,primecell";
+		reg = <0x00 0xff6d0000 0x00 0x4000>;
+		interrupts = <0x00 0x05 0x04 0x00 0x00 0x06 0x04 0x00>;
+		#dma-cells = <0x01>;
+		arm,pl330-periph-burst;
+		clocks = <0x08 0xd3>;
+		clock-names = "apb_pclk";
+		phandle = <0x59>;
+	};
+
+	dma-controller@ff6e0000 {
+		compatible = "arm,pl330\0arm,primecell";
+		reg = <0x00 0xff6e0000 0x00 0x4000>;
+		interrupts = <0x00 0x07 0x04 0x00 0x00 0x08 0x04 0x00>;
+		#dma-cells = <0x01>;
+		arm,pl330-periph-burst;
+		clocks = <0x08 0xd4>;
+		clock-names = "apb_pclk";
+		phandle = <0x48>;
+	};
+
+	clock-controller@ff750000 {
+		compatible = "rockchip,rk3399-pmucru";
+		reg = <0x00 0xff750000 0x00 0x1000>;
+		clocks = <0x8f>;
+		clock-names = "xin24m";
+		rockchip,grf = <0x11>;
+		#clock-cells = <0x01>;
+		#reset-cells = <0x01>;
+		assigned-clocks = <0x7b 0x01>;
+		assigned-clock-rates = <0x284af100>;
+		phandle = <0x7b>;
+	};
+
+	clock-controller@ff760000 {
+		compatible = "rockchip,rk3399-cru";
+		reg = <0x00 0xff760000 0x00 0x1000>;
+		clocks = <0x8f>;
+		clock-names = "xin24m";
+		rockchip,grf = <0x1a>;
+		#clock-cells = <0x01>;
+		#reset-cells = <0x01>;
+		assigned-clocks = <0x08 0x05 0x08 0x04 0x08 0x06 0x08 0xc0 0x08 0x1c0 0x08 0x140 0x08 0xc2 0x08 0x1c1 0x08 0x142 0x08 0xc9 0x08 0x1c2 0x08 0x143 0x08 0xe3 0x08 0xde 0x08 0x106 0x08 0x178 0x08 0xed>;
+		assigned-clock-rates = <0x2367b880 0x2faf0800 0x3b9aca00 0x8f0d180 0x47868c0 0x23c3460 0x11e1a300 0x5f5e100 0x2faf080 0x23c34600 0x5f5e100 0x2faf080 0x17d78400 0x17d78400 0xbebc200 0xbebc200 0x17d78400>;
+		phandle = <0x08>;
+	};
+
+	syscon@ff770000 {
+		compatible = "rockchip,rk3399-grf\0syscon\0simple-mfd";
+		reg = <0x00 0xff770000 0x00 0x10000>;
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+		phandle = <0x1a>;
+
+		io-domains {
+			compatible = "rockchip,rk3399-io-voltage-domain";
+			status = "okay";
+			bt656-supply = <0x90>;
+			audio-supply = <0x91>;
+			sdmmc-supply = <0x28>;
+			gpio1830-supply = <0x7a>;
+			phandle = <0x10b>;
+		};
+
+		mipi-dphy-rx0 {
+			compatible = "rockchip,rk3399-mipi-dphy-rx0";
+			clocks = <0x08 0x77 0x08 0xa5 0x08 0x16f>;
+			clock-names = "dphy-ref\0dphy-cfg\0grf";
+			power-domains = <0x19 0x0f>;
+			#phy-cells = <0x00>;
+			status = "disabled";
+			phandle = <0xa6>;
+		};
+
+		usb2phy@e450 {
+			compatible = "rockchip,rk3399-usb2phy";
+			reg = <0xe450 0x10>;
+			clocks = <0x08 0x7b>;
+			clock-names = "phyclk";
+			#clock-cells = <0x00>;
+			clock-output-names = "clk_usbphy0_480m";
+			status = "okay";
+			phandle = <0x2a>;
+
+			host-port {
+				#phy-cells = <0x00>;
+				interrupts = <0x00 0x1b 0x04 0x00>;
+				interrupt-names = "linestate";
+				status = "okay";
+				phy-supply = <0x92>;
+				phandle = <0x2b>;
+			};
+
+			otg-port {
+				#phy-cells = <0x00>;
+				interrupts = <0x00 0x67 0x04 0x00 0x00 0x68 0x04 0x00 0x00 0x6a 0x04 0x00>;
+				interrupt-names = "otg-bvalid\0otg-id\0linestate";
+				status = "disabled";
+				phandle = <0x2e>;
+			};
+		};
+
+		usb2phy@e460 {
+			compatible = "rockchip,rk3399-usb2phy";
+			reg = <0xe460 0x10>;
+			clocks = <0x08 0x7c>;
+			clock-names = "phyclk";
+			#clock-cells = <0x00>;
+			clock-output-names = "clk_usbphy1_480m";
+			status = "okay";
+			phandle = <0x2c>;
+
+			host-port {
+				#phy-cells = <0x00>;
+				interrupts = <0x00 0x1f 0x04 0x00>;
+				interrupt-names = "linestate";
+				status = "okay";
+				phy-supply = <0x93>;
+				phandle = <0x2d>;
+			};
+
+			otg-port {
+				#phy-cells = <0x00>;
+				interrupts = <0x00 0x6c 0x04 0x00 0x00 0x6d 0x04 0x00 0x00 0x6f 0x04 0x00>;
+				interrupt-names = "otg-bvalid\0otg-id\0linestate";
+				status = "disabled";
+				phandle = <0x30>;
+			};
+		};
+
+		phy@f780 {
+			compatible = "rockchip,rk3399-emmc-phy";
+			reg = <0xf780 0x24>;
+			clocks = <0x94>;
+			clock-names = "emmcclk";
+			drive-impedance-ohm = <0x32>;
+			#phy-cells = <0x00>;
+			status = "okay";
+			phandle = <0x29>;
+		};
+
+		pcie-phy {
+			compatible = "rockchip,rk3399-pcie-phy";
+			clocks = <0x08 0x8a>;
+			clock-names = "refclk";
+			#phy-cells = <0x01>;
+			resets = <0x08 0x87>;
+			reset-names = "phy";
+			status = "okay";
+			assigned-clocks = <0x08 0x8a>;
+			assigned-clock-parents = <0x08 0xa7>;
+			assigned-clock-rates = <0x5f5e100>;
+			phandle = <0x17>;
+		};
+	};
+
+	phy@ff7c0000 {
+		compatible = "rockchip,rk3399-typec-phy";
+		reg = <0x00 0xff7c0000 0x00 0x40000>;
+		clocks = <0x08 0x7e 0x08 0x7d>;
+		clock-names = "tcpdcore\0tcpdphy-ref";
+		assigned-clocks = <0x08 0x7e>;
+		assigned-clock-rates = <0x2faf080>;
+		power-domains = <0x19 0x08>;
+		resets = <0x08 0x95 0x08 0x94 0x08 0x14c>;
+		reset-names = "uphy\0uphy-pipe\0uphy-tcphy";
+		rockchip,grf = <0x1a>;
+		status = "disabled";
+		phandle = <0x10c>;
+
+		dp-port {
+			#phy-cells = <0x00>;
+			phandle = <0x32>;
+		};
+
+		usb3-port {
+			#phy-cells = <0x00>;
+			phandle = <0x2f>;
+		};
+	};
+
+	phy@ff800000 {
+		compatible = "rockchip,rk3399-typec-phy";
+		reg = <0x00 0xff800000 0x00 0x40000>;
+		clocks = <0x08 0x80 0x08 0x7f>;
+		clock-names = "tcpdcore\0tcpdphy-ref";
+		assigned-clocks = <0x08 0x80>;
+		assigned-clock-rates = <0x2faf080>;
+		power-domains = <0x19 0x09>;
+		resets = <0x08 0x9d 0x08 0x9c 0x08 0x14d>;
+		reset-names = "uphy\0uphy-pipe\0uphy-tcphy";
+		rockchip,grf = <0x1a>;
+		status = "disabled";
+		phandle = <0x10d>;
+
+		dp-port {
+			#phy-cells = <0x00>;
+			phandle = <0x33>;
+		};
+
+		usb3-port {
+			#phy-cells = <0x00>;
+			phandle = <0x31>;
+		};
+	};
+
+	watchdog@ff848000 {
+		compatible = "rockchip,rk3399-wdt\0snps,dw-wdt";
+		reg = <0x00 0xff848000 0x00 0x100>;
+		clocks = <0x08 0x17c>;
+		interrupts = <0x00 0x78 0x04 0x00>;
+	};
+
+	rktimer@ff850000 {
+		compatible = "rockchip,rk3399-timer";
+		reg = <0x00 0xff850000 0x00 0x1000>;
+		interrupts = <0x00 0x51 0x04 0x00>;
+		clocks = <0x08 0x168 0x08 0x5a>;
+		clock-names = "pclk\0timer";
+		phandle = <0x10e>;
+	};
+
+	spdif@ff870000 {
+		compatible = "rockchip,rk3399-spdif";
+		reg = <0x00 0xff870000 0x00 0x1000>;
+		interrupts = <0x00 0x42 0x04 0x00>;
+		dmas = <0x59 0x07>;
+		dma-names = "tx";
+		clock-names = "mclk\0hclk";
+		clocks = <0x08 0x55 0x08 0x1d7>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x95>;
+		power-domains = <0x19 0x1c>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x10f>;
+	};
+
+	i2s@ff880000 {
+		compatible = "rockchip,rk3399-i2s\0rockchip,rk3066-i2s";
+		reg = <0x00 0xff880000 0x00 0x1000>;
+		rockchip,grf = <0x1a>;
+		interrupts = <0x00 0x27 0x04 0x00>;
+		dmas = <0x59 0x00 0x59 0x01>;
+		dma-names = "tx\0rx";
+		clock-names = "i2s_clk\0i2s_hclk";
+		clocks = <0x08 0x56 0x08 0x1d4>;
+		pinctrl-names = "bclk_on\0bclk_off";
+		pinctrl-0 = <0x96>;
+		pinctrl-1 = <0x97>;
+		power-domains = <0x19 0x1c>;
+		#sound-dai-cells = <0x00>;
+		status = "okay";
+		rockchip,playback-channels = <0x02>;
+		rockchip,capture-channels = <0x02>;
+		phandle = <0x110>;
+
+		port {
+			phandle = <0xbd>;
+
+			endpoint {
+				dai-format = "i2s";
+				mclk-fs = <0x100>;
+				remote-endpoint = <0x98>;
+				phandle = <0x38>;
+			};
+		};
+	};
+
+	i2s@ff890000 {
+		compatible = "rockchip,rk3399-i2s\0rockchip,rk3066-i2s";
+		reg = <0x00 0xff890000 0x00 0x1000>;
+		interrupts = <0x00 0x28 0x04 0x00>;
+		dmas = <0x59 0x02 0x59 0x03>;
+		dma-names = "tx\0rx";
+		clock-names = "i2s_clk\0i2s_hclk";
+		clocks = <0x08 0x57 0x08 0x1d5>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x99>;
+		power-domains = <0x19 0x1c>;
+		#sound-dai-cells = <0x00>;
+		status = "okay";
+		rockchip,playback-channels = <0x02>;
+		rockchip,capture-channels = <0x02>;
+		phandle = <0x111>;
+	};
+
+	i2s@ff8a0000 {
+		compatible = "rockchip,rk3399-i2s\0rockchip,rk3066-i2s";
+		reg = <0x00 0xff8a0000 0x00 0x1000>;
+		interrupts = <0x00 0x29 0x04 0x00>;
+		dmas = <0x59 0x04 0x59 0x05>;
+		dma-names = "tx\0rx";
+		clock-names = "i2s_clk\0i2s_hclk";
+		clocks = <0x08 0x58 0x08 0x1d6>;
+		power-domains = <0x19 0x1c>;
+		#sound-dai-cells = <0x00>;
+		status = "okay";
+		phandle = <0xa9>;
+	};
+
+	vop@ff8f0000 {
+		compatible = "rockchip,rk3399-vop-lit";
+		reg = <0x00 0xff8f0000 0x00 0x2000 0x00 0xff8f2000 0x00 0x400>;
+		interrupts = <0x00 0x77 0x04 0x00>;
+		assigned-clocks = <0x08 0xdb 0x08 0x1db>;
+		assigned-clock-rates = <0x17d78400 0x5f5e100>;
+		clocks = <0x08 0xdb 0x08 0xb5 0x08 0x1db>;
+		clock-names = "aclk_vop\0dclk_vop\0hclk_vop";
+		iommus = <0x9a>;
+		power-domains = <0x19 0x12>;
+		resets = <0x08 0x113 0x08 0x117 0x08 0x119>;
+		reset-names = "axi\0ahb\0dclk";
+		status = "okay";
+		phandle = <0x112>;
+
+		port {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			phandle = <0x0f>;
+
+			endpoint@0 {
+				reg = <0x00>;
+				remote-endpoint = <0x9b>;
+				phandle = <0xaf>;
+			};
+
+			endpoint@1 {
+				reg = <0x01>;
+				remote-endpoint = <0x9c>;
+				phandle = <0xb4>;
+			};
+
+			endpoint@3 {
+				reg = <0x03>;
+				remote-endpoint = <0x9d>;
+				phandle = <0xb1>;
+			};
+
+			endpoint@4 {
+				reg = <0x04>;
+				remote-endpoint = <0x9e>;
+				phandle = <0x35>;
+			};
+		};
+	};
+
+	iommu@ff8f3f00 {
+		compatible = "rockchip,iommu";
+		reg = <0x00 0xff8f3f00 0x00 0x100>;
+		interrupts = <0x00 0x77 0x04 0x00>;
+		clocks = <0x08 0xdb 0x08 0x1db>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x19 0x12>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0x9a>;
+	};
+
+	vop@ff900000 {
+		compatible = "rockchip,rk3399-vop-big";
+		reg = <0x00 0xff900000 0x00 0x2000 0x00 0xff902000 0x00 0x1000>;
+		interrupts = <0x00 0x76 0x04 0x00>;
+		assigned-clocks = <0x08 0xd9 0x08 0x1d9>;
+		assigned-clock-rates = <0x17d78400 0x5f5e100>;
+		clocks = <0x08 0xd9 0x08 0xb4 0x08 0x1d9>;
+		clock-names = "aclk_vop\0dclk_vop\0hclk_vop";
+		iommus = <0x9f>;
+		power-domains = <0x19 0x11>;
+		resets = <0x08 0x112 0x08 0x116 0x08 0x118>;
+		reset-names = "axi\0ahb\0dclk";
+		status = "okay";
+		phandle = <0x113>;
+
+		port {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			phandle = <0x10>;
+
+			endpoint@0 {
+				reg = <0x00>;
+				remote-endpoint = <0xa0>;
+				phandle = <0xb3>;
+			};
+
+			endpoint@1 {
+				reg = <0x01>;
+				remote-endpoint = <0xa1>;
+				phandle = <0xae>;
+			};
+
+			endpoint@2 {
+				reg = <0x02>;
+				remote-endpoint = <0xa2>;
+				phandle = <0xad>;
+			};
+
+			endpoint@3 {
+				reg = <0x03>;
+				remote-endpoint = <0xa3>;
+				phandle = <0xb0>;
+			};
+
+			endpoint@4 {
+				reg = <0x04>;
+				remote-endpoint = <0xa4>;
+				phandle = <0x34>;
+			};
+		};
+	};
+
+	iommu@ff903f00 {
+		compatible = "rockchip,iommu";
+		reg = <0x00 0xff903f00 0x00 0x100>;
+		interrupts = <0x00 0x76 0x04 0x00>;
+		clocks = <0x08 0xd9 0x08 0x1d9>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x19 0x11>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0x9f>;
+	};
+
+	isp0@ff910000 {
+		compatible = "rockchip,rk3399-cif-isp";
+		reg = <0x00 0xff910000 0x00 0x4000>;
+		interrupts = <0x00 0x2b 0x04 0x00>;
+		clocks = <0x08 0x6e 0x08 0xe9 0x08 0x1e3>;
+		clock-names = "isp\0aclk\0hclk";
+		iommus = <0xa5>;
+		phys = <0xa6>;
+		phy-names = "dphy";
+		power-domains = <0x19 0x13>;
+		status = "disabled";
+		phandle = <0x114>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+			};
+		};
+	};
+
+	iommu@ff914000 {
+		compatible = "rockchip,iommu";
+		reg = <0x00 0xff914000 0x00 0x100 0x00 0xff915000 0x00 0x100>;
+		interrupts = <0x00 0x2b 0x04 0x00>;
+		clocks = <0x08 0xe9 0x08 0x1e3>;
+		clock-names = "aclk\0iface";
+		#iommu-cells = <0x00>;
+		power-domains = <0x19 0x13>;
+		rockchip,disable-mmu-reset;
+		phandle = <0xa5>;
+	};
+
+	isp1@ff920000 {
+		compatible = "rockchip,rk3399-cif-isp";
+		reg = <0x00 0xff920000 0x00 0x4000>;
+		interrupts = <0x00 0x2c 0x04 0x00>;
+		clocks = <0x08 0x6f 0x08 0xea 0x08 0x1e4>;
+		clock-names = "isp\0aclk\0hclk";
+		iommus = <0xa7>;
+		phys = <0xa8>;
+		phy-names = "dphy";
+		power-domains = <0x19 0x14>;
+		status = "disabled";
+		phandle = <0x115>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+			};
+		};
+	};
+
+	iommu@ff924000 {
+		compatible = "rockchip,iommu";
+		reg = <0x00 0xff924000 0x00 0x100 0x00 0xff925000 0x00 0x100>;
+		interrupts = <0x00 0x2c 0x04 0x00>;
+		clocks = <0x08 0xea 0x08 0x1e4>;
+		clock-names = "aclk\0iface";
+		#iommu-cells = <0x00>;
+		power-domains = <0x19 0x14>;
+		rockchip,disable-mmu-reset;
+		phandle = <0xa7>;
+	};
+
+	hdmi-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <0x100>;
+		simple-audio-card,name = "HDMI";
+		status = "okay";
+		phandle = <0x116>;
+
+		simple-audio-card,cpu {
+			sound-dai = <0xa9>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <0xaa>;
+		};
+	};
+
+	hdmi@ff940000 {
+		compatible = "rockchip,rk3399-dw-hdmi";
+		reg = <0x00 0xff940000 0x00 0x20000>;
+		interrupts = <0x00 0x17 0x04 0x00>;
+		clocks = <0x08 0x174 0x08 0x71 0x08 0x70 0x08 0x16f 0x08 0x07>;
+		clock-names = "iahb\0isfr\0cec\0grf\0ref";
+		power-domains = <0x19 0x15>;
+		reg-io-width = <0x04>;
+		rockchip,grf = <0x1a>;
+		#sound-dai-cells = <0x00>;
+		status = "okay";
+		ddc-i2c-bus = <0xab>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0xac>;
+		phandle = <0xaa>;
+
+		ports {
+
+			port {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				phandle = <0x117>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xad>;
+					phandle = <0xa2>;
+				};
+			};
+		};
+	};
+
+	mipi@ff960000 {
+		compatible = "rockchip,rk3399-mipi-dsi\0snps,dw-mipi-dsi";
+		reg = <0x00 0xff960000 0x00 0x8000>;
+		interrupts = <0x00 0x2d 0x04 0x00>;
+		clocks = <0x08 0xa2 0x08 0x170 0x08 0xa3 0x08 0x16f>;
+		clock-names = "ref\0pclk\0phy_cfg\0grf";
+		power-domains = <0x19 0x0f>;
+		resets = <0x08 0xfb>;
+		reset-names = "apb";
+		rockchip,grf = <0x1a>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x118>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				phandle = <0x119>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xae>;
+					phandle = <0xa1>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xaf>;
+					phandle = <0x9b>;
+				};
+			};
+		};
+	};
+
+	mipi@ff968000 {
+		compatible = "rockchip,rk3399-mipi-dsi\0snps,dw-mipi-dsi";
+		reg = <0x00 0xff968000 0x00 0x8000>;
+		interrupts = <0x00 0x2e 0x04 0x00>;
+		clocks = <0x08 0xa2 0x08 0x171 0x08 0xa4 0x08 0x16f>;
+		clock-names = "ref\0pclk\0phy_cfg\0grf";
+		power-domains = <0x19 0x0f>;
+		resets = <0x08 0xfc>;
+		reset-names = "apb";
+		rockchip,grf = <0x1a>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		#phy-cells = <0x00>;
+		status = "disabled";
+		phandle = <0xa8>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				phandle = <0x11a>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xb0>;
+					phandle = <0xa3>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xb1>;
+					phandle = <0x9d>;
+				};
+			};
+		};
+	};
+
+	edp@ff970000 {
+		compatible = "rockchip,rk3399-edp";
+		reg = <0x00 0xff970000 0x00 0x8000>;
+		interrupts = <0x00 0x0a 0x04 0x00>;
+		clocks = <0x08 0x16a 0x08 0x16c 0x08 0x16f>;
+		clock-names = "dp\0pclk\0grf";
+		pinctrl-names = "default";
+		pinctrl-0 = <0xb2>;
+		power-domains = <0x19 0x19>;
+		resets = <0x08 0x11d>;
+		reset-names = "dp";
+		rockchip,grf = <0x1a>;
+		status = "disabled";
+		phandle = <0x11b>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				phandle = <0x11c>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xb3>;
+					phandle = <0xa0>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xb4>;
+					phandle = <0x9c>;
+				};
+			};
+		};
+	};
+
+	gpu@ff9a0000 {
+		compatible = "rockchip,rk3399-mali\0arm,mali-t860";
+		reg = <0x00 0xff9a0000 0x00 0x10000>;
+		interrupts = <0x00 0x14 0x04 0x00 0x00 0x15 0x04 0x00 0x00 0x13 0x04 0x00>;
+		interrupt-names = "job\0mmu\0gpu";
+		clocks = <0x08 0xd0>;
+		#cooling-cells = <0x02>;
+		power-domains = <0x19 0x23>;
+		status = "okay";
+		operating-points-v2 = <0xb5>;
+		mali-supply = <0xb6>;
+		phandle = <0x62>;
+	};
+
+	pinctrl {
+		compatible = "rockchip,rk3399-pinctrl";
+		rockchip,grf = <0x1a>;
+		rockchip,pmu = <0x11>;
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+		phandle = <0x11d>;
+
+		gpio@ff720000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xff720000 0x00 0x100>;
+			clocks = <0x7b 0x17>;
+			interrupts = <0x00 0x0e 0x04 0x00>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0x23>;
+		};
+
+		gpio@ff730000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xff730000 0x00 0x100>;
+			clocks = <0x7b 0x18>;
+			interrupts = <0x00 0x0f 0x04 0x00>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0xc4>;
+		};
+
+		gpio@ff780000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xff780000 0x00 0x100>;
+			clocks = <0x08 0x150>;
+			interrupts = <0x00 0x10 0x04 0x00>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0x18>;
+		};
+
+		gpio@ff788000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xff788000 0x00 0x100>;
+			clocks = <0x08 0x151>;
+			interrupts = <0x00 0x11 0x04 0x00>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0x1e>;
+		};
+
+		gpio@ff790000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xff790000 0x00 0x100>;
+			clocks = <0x08 0x152>;
+			interrupts = <0x00 0x12 0x04 0x00>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0xbe>;
+		};
+
+		pcfg-pull-up {
+			bias-pull-up;
+			phandle = <0xb9>;
+		};
+
+		pcfg-pull-down {
+			bias-pull-down;
+			phandle = <0xbb>;
+		};
+
+		pcfg-pull-none {
+			bias-disable;
+			phandle = <0xb7>;
+		};
+
+		pcfg-pull-none-12ma {
+			bias-disable;
+			drive-strength = <0x0c>;
+			phandle = <0xba>;
+		};
+
+		pcfg-pull-none-13ma {
+			bias-disable;
+			drive-strength = <0x0d>;
+			phandle = <0xb8>;
+		};
+
+		pcfg-pull-none-18ma {
+			bias-disable;
+			drive-strength = <0x12>;
+			phandle = <0x11e>;
+		};
+
+		pcfg-pull-none-20ma {
+			bias-disable;
+			drive-strength = <0x14>;
+			phandle = <0x11f>;
+		};
+
+		pcfg-pull-up-2ma {
+			bias-pull-up;
+			drive-strength = <0x02>;
+			phandle = <0x120>;
+		};
+
+		pcfg-pull-up-8ma {
+			bias-pull-up;
+			drive-strength = <0x08>;
+			phandle = <0x121>;
+		};
+
+		pcfg-pull-up-18ma {
+			bias-pull-up;
+			drive-strength = <0x12>;
+			phandle = <0x122>;
+		};
+
+		pcfg-pull-up-20ma {
+			bias-pull-up;
+			drive-strength = <0x14>;
+			phandle = <0x123>;
+		};
+
+		pcfg-pull-down-4ma {
+			bias-pull-down;
+			drive-strength = <0x04>;
+			phandle = <0x124>;
+		};
+
+		pcfg-pull-down-8ma {
+			bias-pull-down;
+			drive-strength = <0x08>;
+			phandle = <0x125>;
+		};
+
+		pcfg-pull-down-12ma {
+			bias-pull-down;
+			drive-strength = <0x0c>;
+			phandle = <0x126>;
+		};
+
+		pcfg-pull-down-18ma {
+			bias-pull-down;
+			drive-strength = <0x12>;
+			phandle = <0x127>;
+		};
+
+		pcfg-pull-down-20ma {
+			bias-pull-down;
+			drive-strength = <0x14>;
+			phandle = <0x128>;
+		};
+
+		pcfg-output-high {
+			output-high;
+			phandle = <0x129>;
+		};
+
+		pcfg-output-low {
+			output-low;
+			phandle = <0x12a>;
+		};
+
+		pcfg-input-enable {
+			input-enable;
+			phandle = <0x12b>;
+		};
+
+		pcfg-input-pull-up {
+			input-enable;
+			bias-pull-up;
+			phandle = <0x12c>;
+		};
+
+		pcfg-input-pull-down {
+			input-enable;
+			bias-pull-down;
+			phandle = <0x12d>;
+		};
+
+		clock {
+
+			clk-32k {
+				rockchip,pins = <0x00 0x00 0x02 0xb7>;
+				phandle = <0x12e>;
+			};
+		};
+
+		cif {
+
+			cif-clkin {
+				rockchip,pins = <0x02 0x0a 0x03 0xb7>;
+				phandle = <0x12f>;
+			};
+
+			cif-clkouta {
+				rockchip,pins = <0x02 0x0b 0x03 0xb7>;
+				phandle = <0x130>;
+			};
+		};
+
+		edp {
+
+			edp-hpd {
+				rockchip,pins = <0x04 0x17 0x02 0xb7>;
+				phandle = <0xb2>;
+			};
+		};
+
+		gmac {
+
+			rgmii-pins {
+				rockchip,pins = <0x03 0x11 0x01 0xb8 0x03 0x0e 0x01 0xb7 0x03 0x0d 0x01 0xb7 0x03 0x0c 0x01 0xb8 0x03 0x0b 0x01 0xb7 0x03 0x09 0x01 0xb7 0x03 0x08 0x01 0xb7 0x03 0x07 0x01 0xb7 0x03 0x06 0x01 0xb7 0x03 0x05 0x01 0xb8 0x03 0x04 0x01 0xb8 0x03 0x03 0x01 0xb7 0x03 0x02 0x01 0xb7 0x03 0x01 0x01 0xb8 0x03 0x00 0x01 0xb8>;
+				phandle = <0x1d>;
+			};
+
+			rmii-pins {
+				rockchip,pins = <0x03 0x0d 0x01 0xb7 0x03 0x0c 0x01 0xb8 0x03 0x0b 0x01 0xb7 0x03 0x0a 0x01 0xb7 0x03 0x09 0x01 0xb7 0x03 0x08 0x01 0xb7 0x03 0x07 0x01 0xb7 0x03 0x06 0x01 0xb7 0x03 0x05 0x01 0xb8 0x03 0x04 0x01 0xb8>;
+				phandle = <0x131>;
+			};
+
+			phy-intb {
+				rockchip,pins = <0x03 0x0a 0x00 0xb9>;
+				phandle = <0x132>;
+			};
+
+			phy-rstb {
+				rockchip,pins = <0x03 0x0f 0x00 0xb7>;
+				phandle = <0x133>;
+			};
+		};
+
+		i2c0 {
+
+			i2c0-xfer {
+				rockchip,pins = <0x01 0x0f 0x02 0xb7 0x01 0x10 0x02 0xb7>;
+				phandle = <0x81>;
+			};
+		};
+
+		i2c1 {
+
+			i2c1-xfer {
+				rockchip,pins = <0x04 0x02 0x01 0xb7 0x04 0x01 0x01 0xb7>;
+				phandle = <0x37>;
+			};
+		};
+
+		i2c2 {
+
+			i2c2-xfer {
+				rockchip,pins = <0x02 0x01 0x02 0xba 0x02 0x00 0x02 0xba>;
+				phandle = <0x39>;
+			};
+		};
+
+		i2c3 {
+
+			i2c3-xfer {
+				rockchip,pins = <0x04 0x11 0x01 0xb7 0x04 0x10 0x01 0xb7>;
+				phandle = <0x3a>;
+			};
+		};
+
+		i2c4 {
+
+			i2c4-xfer {
+				rockchip,pins = <0x01 0x0c 0x01 0xb7 0x01 0x0b 0x01 0xb7>;
+				phandle = <0x86>;
+			};
+		};
+
+		i2c5 {
+
+			i2c5-xfer {
+				rockchip,pins = <0x03 0x0b 0x02 0xb7 0x03 0x0a 0x02 0xb7>;
+				phandle = <0x3b>;
+			};
+		};
+
+		i2c6 {
+
+			i2c6-xfer {
+				rockchip,pins = <0x02 0x0a 0x02 0xb7 0x02 0x09 0x02 0xb7>;
+				phandle = <0x3c>;
+			};
+		};
+
+		i2c7 {
+
+			i2c7-xfer {
+				rockchip,pins = <0x02 0x08 0x02 0xb7 0x02 0x07 0x02 0xb7>;
+				phandle = <0x3d>;
+			};
+		};
+
+		i2c8 {
+
+			i2c8-xfer {
+				rockchip,pins = <0x01 0x15 0x01 0xb7 0x01 0x14 0x01 0xb7>;
+				phandle = <0x87>;
+			};
+		};
+
+		i2s0 {
+
+			i2s0-2ch-bus {
+				rockchip,pins = <0x03 0x18 0x01 0xb7 0x03 0x19 0x01 0xb7 0x03 0x1a 0x01 0xb7 0x03 0x1b 0x01 0xb7 0x03 0x1f 0x01 0xb7 0x04 0x00 0x01 0xb7>;
+				phandle = <0x96>;
+			};
+
+			i2s0-8ch-bus {
+				rockchip,pins = <0x03 0x18 0x01 0xb7 0x03 0x19 0x01 0xb7 0x03 0x1a 0x01 0xb7 0x03 0x1b 0x01 0xb7 0x03 0x1c 0x01 0xb7 0x03 0x1d 0x01 0xb7 0x03 0x1e 0x01 0xb7 0x03 0x1f 0x01 0xb7 0x04 0x00 0x01 0xb7>;
+				phandle = <0x134>;
+			};
+
+			i2s0-8ch-bus-bclk-off {
+				rockchip,pins = <0x03 0x18 0x00 0xb7 0x03 0x19 0x01 0xb7 0x03 0x1a 0x01 0xb7 0x03 0x1b 0x01 0xb7 0x03 0x1c 0x01 0xb7 0x03 0x1d 0x01 0xb7 0x03 0x1e 0x01 0xb7 0x03 0x1f 0x01 0xb7 0x04 0x00 0x01 0xb7>;
+				phandle = <0x97>;
+			};
+		};
+
+		i2s1 {
+
+			i2s1-2ch-bus {
+				rockchip,pins = <0x04 0x03 0x01 0xb7 0x04 0x04 0x01 0xb7 0x04 0x05 0x01 0xb7 0x04 0x06 0x01 0xb7 0x04 0x07 0x01 0xb7>;
+				phandle = <0x99>;
+			};
+
+			i2s1-2ch-bus-bclk-off {
+				rockchip,pins = <0x04 0x03 0x00 0xb7 0x04 0x04 0x01 0xb7 0x04 0x05 0x01 0xb7 0x04 0x06 0x01 0xb7 0x04 0x07 0x01 0xb7>;
+				phandle = <0x135>;
+			};
+
+			i2s-8ch-mclk {
+				rockchip,pins = <0x04 0x00 0x01 0xb7>;
+				phandle = <0x136>;
+			};
+		};
+
+		sdio0 {
+
+			sdio0-bus1 {
+				rockchip,pins = <0x02 0x14 0x01 0xb9>;
+				phandle = <0x137>;
+			};
+
+			sdio0-bus4 {
+				rockchip,pins = <0x02 0x14 0x01 0xb9 0x02 0x15 0x01 0xb9 0x02 0x16 0x01 0xb9 0x02 0x17 0x01 0xb9>;
+				phandle = <0x20>;
+			};
+
+			sdio0-cmd {
+				rockchip,pins = <0x02 0x18 0x01 0xb9>;
+				phandle = <0x21>;
+			};
+
+			sdio0-clk {
+				rockchip,pins = <0x02 0x19 0x01 0xb7>;
+				phandle = <0x22>;
+			};
+
+			sdio0-cd {
+				rockchip,pins = <0x02 0x1a 0x01 0xb9>;
+				phandle = <0x138>;
+			};
+
+			sdio0-pwr {
+				rockchip,pins = <0x02 0x1b 0x01 0xb9>;
+				phandle = <0x139>;
+			};
+
+			sdio0-bkpwr {
+				rockchip,pins = <0x02 0x1c 0x01 0xb9>;
+				phandle = <0x13a>;
+			};
+
+			sdio0-wp {
+				rockchip,pins = <0x00 0x03 0x01 0xb9>;
+				phandle = <0x13b>;
+			};
+
+			sdio0-int {
+				rockchip,pins = <0x00 0x04 0x01 0xb9>;
+				phandle = <0x13c>;
+			};
+		};
+
+		sdmmc {
+
+			sdmmc-bus1 {
+				rockchip,pins = <0x04 0x08 0x01 0xb9>;
+				phandle = <0x13d>;
+			};
+
+			sdmmc-bus4 {
+				rockchip,pins = <0x04 0x08 0x01 0xb9 0x04 0x09 0x01 0xb9 0x04 0x0a 0x01 0xb9 0x04 0x0b 0x01 0xb9>;
+				phandle = <0x24>;
+			};
+
+			sdmmc-clk {
+				rockchip,pins = <0x04 0x0c 0x01 0xb7>;
+				phandle = <0x25>;
+			};
+
+			sdmmc-cmd {
+				rockchip,pins = <0x04 0x0d 0x01 0xb9>;
+				phandle = <0x26>;
+			};
+
+			sdmmc-cd {
+				rockchip,pins = <0x00 0x07 0x01 0xb9>;
+				phandle = <0x13e>;
+			};
+
+			sdmmc-wp {
+				rockchip,pins = <0x00 0x08 0x01 0xb9>;
+				phandle = <0x13f>;
+			};
+		};
+
+		suspend {
+
+			ap-pwroff {
+				rockchip,pins = <0x01 0x05 0x01 0xb7>;
+				phandle = <0x140>;
+			};
+
+			ddrio-pwroff {
+				rockchip,pins = <0x00 0x01 0x01 0xb7>;
+				phandle = <0x141>;
+			};
+		};
+
+		spdif {
+
+			spdif-bus {
+				rockchip,pins = <0x04 0x15 0x01 0xb7>;
+				phandle = <0x95>;
+			};
+
+			spdif-bus-1 {
+				rockchip,pins = <0x03 0x10 0x03 0xb7>;
+				phandle = <0x142>;
+			};
+		};
+
+		spi0 {
+
+			spi0-clk {
+				rockchip,pins = <0x03 0x06 0x02 0xb9>;
+				phandle = <0x49>;
+			};
+
+			spi0-cs0 {
+				rockchip,pins = <0x03 0x07 0x02 0xb9>;
+				phandle = <0x4c>;
+			};
+
+			spi0-cs1 {
+				rockchip,pins = <0x03 0x08 0x02 0xb9>;
+				phandle = <0x143>;
+			};
+
+			spi0-tx {
+				rockchip,pins = <0x03 0x05 0x02 0xb9>;
+				phandle = <0x4a>;
+			};
+
+			spi0-rx {
+				rockchip,pins = <0x03 0x04 0x02 0xb9>;
+				phandle = <0x4b>;
+			};
+		};
+
+		spi1 {
+
+			spi1-clk {
+				rockchip,pins = <0x01 0x09 0x02 0xb9>;
+				phandle = <0x4d>;
+			};
+
+			spi1-cs0 {
+				rockchip,pins = <0x01 0x0a 0x02 0xb9>;
+				phandle = <0x50>;
+			};
+
+			spi1-rx {
+				rockchip,pins = <0x01 0x07 0x02 0xb9>;
+				phandle = <0x4f>;
+			};
+
+			spi1-tx {
+				rockchip,pins = <0x01 0x08 0x02 0xb9>;
+				phandle = <0x4e>;
+			};
+		};
+
+		spi2 {
+
+			spi2-clk {
+				rockchip,pins = <0x02 0x0b 0x01 0xb9>;
+				phandle = <0x51>;
+			};
+
+			spi2-cs0 {
+				rockchip,pins = <0x02 0x0c 0x01 0xb9>;
+				phandle = <0x54>;
+			};
+
+			spi2-rx {
+				rockchip,pins = <0x02 0x09 0x01 0xb9>;
+				phandle = <0x53>;
+			};
+
+			spi2-tx {
+				rockchip,pins = <0x02 0x0a 0x01 0xb9>;
+				phandle = <0x52>;
+			};
+		};
+
+		spi3 {
+
+			spi3-clk {
+				rockchip,pins = <0x01 0x11 0x01 0xb9>;
+				phandle = <0x7c>;
+			};
+
+			spi3-cs0 {
+				rockchip,pins = <0x01 0x12 0x01 0xb9>;
+				phandle = <0x7f>;
+			};
+
+			spi3-rx {
+				rockchip,pins = <0x01 0x0f 0x01 0xb9>;
+				phandle = <0x7e>;
+			};
+
+			spi3-tx {
+				rockchip,pins = <0x01 0x10 0x01 0xb9>;
+				phandle = <0x7d>;
+			};
+		};
+
+		spi4 {
+
+			spi4-clk {
+				rockchip,pins = <0x03 0x02 0x02 0xb9>;
+				phandle = <0x55>;
+			};
+
+			spi4-cs0 {
+				rockchip,pins = <0x03 0x03 0x02 0xb9>;
+				phandle = <0x58>;
+			};
+
+			spi4-rx {
+				rockchip,pins = <0x03 0x00 0x02 0xb9>;
+				phandle = <0x57>;
+			};
+
+			spi4-tx {
+				rockchip,pins = <0x03 0x01 0x02 0xb9>;
+				phandle = <0x56>;
+			};
+		};
+
+		spi5 {
+
+			spi5-clk {
+				rockchip,pins = <0x02 0x16 0x02 0xb9>;
+				phandle = <0x5a>;
+			};
+
+			spi5-cs0 {
+				rockchip,pins = <0x02 0x17 0x02 0xb9>;
+				phandle = <0x5d>;
+			};
+
+			spi5-rx {
+				rockchip,pins = <0x02 0x14 0x02 0xb9>;
+				phandle = <0x5c>;
+			};
+
+			spi5-tx {
+				rockchip,pins = <0x02 0x15 0x02 0xb9>;
+				phandle = <0x5b>;
+			};
+		};
+
+		testclk {
+
+			test-clkout0 {
+				rockchip,pins = <0x00 0x00 0x01 0xb7>;
+				phandle = <0x144>;
+			};
+
+			test-clkout1 {
+				rockchip,pins = <0x02 0x19 0x02 0xb7>;
+				phandle = <0x145>;
+			};
+
+			test-clkout2 {
+				rockchip,pins = <0x00 0x08 0x03 0xb7>;
+				phandle = <0x146>;
+			};
+		};
+
+		tsadc {
+
+			otp-pin {
+				rockchip,pins = <0x01 0x06 0x00 0xb7>;
+				phandle = <0x63>;
+			};
+
+			otp-out {
+				rockchip,pins = <0x01 0x06 0x01 0xb7>;
+				phandle = <0x64>;
+			};
+		};
+
+		uart0 {
+
+			uart0-xfer {
+				rockchip,pins = <0x02 0x10 0x01 0xb9 0x02 0x11 0x01 0xb7>;
+				phandle = <0x3e>;
+			};
+
+			uart0-cts {
+				rockchip,pins = <0x02 0x12 0x01 0xb7>;
+				phandle = <0x3f>;
+			};
+
+			uart0-rts {
+				rockchip,pins = <0x02 0x13 0x01 0xb7>;
+				phandle = <0x40>;
+			};
+		};
+
+		uart1 {
+
+			uart1-xfer {
+				rockchip,pins = <0x03 0x0c 0x02 0xb9 0x03 0x0d 0x02 0xb7>;
+				phandle = <0x45>;
+			};
+		};
+
+		uart2a {
+
+			uart2a-xfer {
+				rockchip,pins = <0x04 0x08 0x02 0xb9 0x04 0x09 0x02 0xb7>;
+				phandle = <0x147>;
+			};
+		};
+
+		uart2b {
+
+			uart2b-xfer {
+				rockchip,pins = <0x04 0x10 0x02 0xb9 0x04 0x11 0x02 0xb7>;
+				phandle = <0x148>;
+			};
+		};
+
+		uart2c {
+
+			uart2c-xfer {
+				rockchip,pins = <0x04 0x13 0x01 0xb9 0x04 0x14 0x01 0xb7>;
+				phandle = <0x46>;
+			};
+		};
+
+		uart3 {
+
+			uart3-xfer {
+				rockchip,pins = <0x03 0x0e 0x02 0xb9 0x03 0x0f 0x02 0xb7>;
+				phandle = <0x47>;
+			};
+
+			uart3-cts {
+				rockchip,pins = <0x03 0x10 0x02 0xb7>;
+				phandle = <0x149>;
+			};
+
+			uart3-rts {
+				rockchip,pins = <0x03 0x11 0x02 0xb7>;
+				phandle = <0x14a>;
+			};
+		};
+
+		uart4 {
+
+			uart4-xfer {
+				rockchip,pins = <0x01 0x07 0x01 0xb9 0x01 0x08 0x01 0xb7>;
+				phandle = <0x80>;
+			};
+		};
+
+		uarthdcp {
+
+			uarthdcp-xfer {
+				rockchip,pins = <0x04 0x15 0x02 0xb9 0x04 0x16 0x02 0xb7>;
+				phandle = <0x14b>;
+			};
+		};
+
+		pwm0 {
+
+			pwm0-pin {
+				rockchip,pins = <0x04 0x12 0x01 0xb7>;
+				phandle = <0x88>;
+			};
+
+			pwm0-pin-pull-down {
+				rockchip,pins = <0x04 0x12 0x01 0xbb>;
+				phandle = <0x14c>;
+			};
+
+			vop0-pwm-pin {
+				rockchip,pins = <0x04 0x12 0x02 0xb7>;
+				phandle = <0x14d>;
+			};
+
+			vop1-pwm-pin {
+				rockchip,pins = <0x04 0x12 0x03 0xb7>;
+				phandle = <0x14e>;
+			};
+		};
+
+		pwm1 {
+
+			pwm1-pin {
+				rockchip,pins = <0x04 0x16 0x01 0xb7>;
+				phandle = <0x89>;
+			};
+
+			pwm1-pin-pull-down {
+				rockchip,pins = <0x04 0x16 0x01 0xbb>;
+				phandle = <0x14f>;
+			};
+		};
+
+		pwm2 {
+
+			pwm2-pin {
+				rockchip,pins = <0x01 0x13 0x01 0xb7>;
+				phandle = <0x8a>;
+			};
+
+			pwm2-pin-pull-down {
+				rockchip,pins = <0x01 0x13 0x01 0xbb>;
+				phandle = <0x150>;
+			};
+		};
+
+		pwm3a {
+
+			pwm3a-pin {
+				rockchip,pins = <0x00 0x06 0x01 0xb7>;
+				phandle = <0x8b>;
+			};
+		};
+
+		pwm3b {
+
+			pwm3b-pin {
+				rockchip,pins = <0x01 0x0e 0x01 0xb7>;
+				phandle = <0x151>;
+			};
+		};
+
+		hdmi {
+
+			hdmi-i2c-xfer {
+				rockchip,pins = <0x04 0x11 0x03 0xb7 0x04 0x10 0x03 0xb7>;
+				phandle = <0x152>;
+			};
+
+			hdmi-cec {
+				rockchip,pins = <0x04 0x17 0x01 0xb7>;
+				phandle = <0xac>;
+			};
+		};
+
+		pcie {
+
+			pci-clkreqn-cpm {
+				rockchip,pins = <0x02 0x1a 0x00 0xb7>;
+				phandle = <0x153>;
+			};
+
+			pci-clkreqnb-cpm {
+				rockchip,pins = <0x04 0x18 0x00 0xb7>;
+				phandle = <0x154>;
+			};
+
+			pcie-pwr-en {
+				rockchip,pins = <0x01 0x00 0x00 0xb7>;
+				phandle = <0xc5>;
+			};
+		};
+
+		pmic {
+
+			cpu-b-sleep {
+				rockchip,pins = <0x01 0x11 0x00 0xbb>;
+				phandle = <0x84>;
+			};
+
+			gpu-sleep {
+				rockchip,pins = <0x01 0x0e 0x00 0xbb>;
+				phandle = <0x85>;
+			};
+
+			pmic-int-l {
+				rockchip,pins = <0x01 0x15 0x00 0xb9>;
+				phandle = <0x82>;
+			};
+		};
+
+		sd {
+
+			sdmmc0-pwr-h {
+				rockchip,pins = <0x00 0x01 0x00 0xb9>;
+				phandle = <0xc1>;
+			};
+		};
+
+		usb2 {
+
+			vcc5v0-host-en {
+				rockchip,pins = <0x04 0x19 0x00 0xb7>;
+				phandle = <0x155>;
+			};
+
+			vcc5v0-typec-en {
+				rockchip,pins = <0x01 0x03 0x00 0xb7>;
+				phandle = <0xc0>;
+			};
+		};
+
+		sdio-pwrseq {
+
+			wifi-reg-on-h {
+				rockchip,pins = <0x00 0x0a 0x00 0xb7>;
+				phandle = <0xbc>;
+			};
+		};
+
+		bluetooth {
+
+			bt-enable-h {
+				rockchip,pins = <0x00 0x09 0x00 0xb7>;
+				phandle = <0x44>;
+			};
+
+			bt-host-wake-l {
+				rockchip,pins = <0x00 0x04 0x00 0xb7>;
+				phandle = <0x42>;
+			};
+
+			bt-wake-l {
+				rockchip,pins = <0x02 0x1a 0x00 0xb7>;
+				phandle = <0x43>;
+			};
+		};
+
+		fusb302 {
+
+			chg-cc-int-l {
+				rockchip,pins = <0x01 0x02 0x00 0xb9>;
+				phandle = <0x156>;
+			};
+		};
+	};
+
+	opp-table-0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		phandle = <0x0b>;
+
+		opp00 {
+			opp-hz = <0x00 0x18519600>;
+			opp-microvolt = <0xc96a8 0xc96a8 0x1312d0>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp01 {
+			opp-hz = <0x00 0x23c34600>;
+			opp-microvolt = <0xc96a8 0xc96a8 0x1312d0>;
+		};
+
+		opp02 {
+			opp-hz = <0x00 0x30a32c00>;
+			opp-microvolt = <0xcf850 0xcf850 0x1312d0>;
+		};
+
+		opp03 {
+			opp-hz = <0x00 0x3c14dc00>;
+			opp-microvolt = <0xe1d48 0xe1d48 0x1312d0>;
+		};
+
+		opp04 {
+			opp-hz = <0x00 0x47868c00>;
+			opp-microvolt = <0xf4240 0xf4240 0x1312d0>;
+		};
+
+		opp05 {
+			opp-hz = <0x00 0x54667200>;
+			opp-microvolt = <0x112a88 0x112a88 0x1312d0>;
+		};
+	};
+
+	opp-table-1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		phandle = <0x0d>;
+
+		opp00 {
+			opp-hz = <0x00 0x18519600>;
+			opp-microvolt = <0xc96a8 0xc96a8 0x1312d0>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp01 {
+			opp-hz = <0x00 0x23c34600>;
+			opp-microvolt = <0xc96a8 0xc96a8 0x1312d0>;
+		};
+
+		opp02 {
+			opp-hz = <0x00 0x30a32c00>;
+			opp-microvolt = <0xc96a8 0xc96a8 0x1312d0>;
+		};
+
+		opp03 {
+			opp-hz = <0x00 0x3c14dc00>;
+			opp-microvolt = <0xd59f8 0xd59f8 0x1312d0>;
+		};
+
+		opp04 {
+			opp-hz = <0x00 0x47868c00>;
+			opp-microvolt = <0xe7ef0 0xe7ef0 0x1312d0>;
+		};
+
+		opp05 {
+			opp-hz = <0x00 0x54667200>;
+			opp-microvolt = <0xfa3e8 0xfa3e8 0x1312d0>;
+		};
+
+		opp06 {
+			opp-hz = <0x00 0x5fd82200>;
+			opp-microvolt = <0x10c8e0 0x10c8e0 0x1312d0>;
+		};
+
+		opp07 {
+			opp-hz = <0x00 0x6b49d200>;
+			opp-microvolt = <0x124f80 0x124f80 0x1312d0>;
+		};
+	};
+
+	opp-table-2 {
+		compatible = "operating-points-v2";
+		phandle = <0xb5>;
+
+		opp00 {
+			opp-hz = <0x00 0xbebc200>;
+			opp-microvolt = <0xc96a8 0xc96a8 0x118c30>;
+		};
+
+		opp01 {
+			opp-hz = <0x00 0x11b3dc40>;
+			opp-microvolt = <0xc96a8 0xc96a8 0x118c30>;
+		};
+
+		opp02 {
+			opp-hz = <0x00 0x17d78400>;
+			opp-microvolt = <0xc96a8 0xc96a8 0x118c30>;
+		};
+
+		opp03 {
+			opp-hz = <0x00 0x1dcd6500>;
+			opp-microvolt = <0xd59f8 0xd59f8 0x118c30>;
+		};
+
+		opp04 {
+			opp-hz = <0x00 0x23c34600>;
+			opp-microvolt = <0xe1d48 0xe1d48 0x118c30>;
+		};
+
+		opp05 {
+			opp-hz = <0x00 0x2faf0800>;
+			opp-microvolt = <0x10c8e0 0x10c8e0 0x118c30>;
+		};
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <0x7735940>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0x00>;
+		phandle = <0x1b>;
+	};
+
+	sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <0x41 0x01>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <0xbc>;
+		reset-gpios = <0x23 0x0a 0x01>;
+		phandle = <0x1f>;
+	};
+
+	sound {
+		compatible = "audio-graph-card";
+		label = "Analog";
+		dais = <0xbd>;
+		hp-det-gpio = <0xbe 0x1c 0x01>;
+	};
+
+	usb-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x4c4b40>;
+		regulator-max-microvolt = <0x4c4b40>;
+		vin-supply = <0xbf>;
+		phandle = <0x93>;
+
+		regulator-state-mem {
+			regulator-on-in-suspend;
+		};
+	};
+
+	usb3-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb3_vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x4c4b40>;
+		regulator-max-microvolt = <0x4c4b40>;
+		vin-supply = <0xbf>;
+		phandle = <0x92>;
+
+		regulator-state-mem {
+			regulator-on-in-suspend;
+		};
+	};
+
+	vbus-typec {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <0x18 0x0c 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0xc0>;
+		regulator-name = "vbus_typec";
+		regulator-always-on;
+		regulator-min-microvolt = <0x4c4b40>;
+		regulator-max-microvolt = <0x4c4b40>;
+		vin-supply = <0xbf>;
+		phandle = <0x157>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vcc-0v9 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0xdbba0>;
+		regulator-max-microvolt = <0xdbba0>;
+		vin-supply = <0x83>;
+		phandle = <0x158>;
+	};
+
+	vcc3v0-sd {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <0x23 0x01 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0xc1>;
+		regulator-name = "vcc3v0_sd";
+		regulator-always-on;
+		regulator-min-microvolt = <0x2dc6c0>;
+		regulator-max-microvolt = <0x2dc6c0>;
+		vin-supply = <0x83>;
+		phandle = <0x27>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x325aa0>;
+		regulator-max-microvolt = <0x325aa0>;
+		vin-supply = <0xc2>;
+		phandle = <0x83>;
+
+		regulator-state-mem {
+			regulator-on-in-suspend;
+		};
+	};
+
+	vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x4c4b40>;
+		regulator-max-microvolt = <0x4c4b40>;
+		vin-supply = <0xc2>;
+		phandle = <0xbf>;
+
+		regulator-state-mem {
+			regulator-on-in-suspend;
+		};
+	};
+
+	vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		phandle = <0xc2>;
+	};
+
+	vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <0xc3 0x00 0x61a8 0x01>;
+		regulator-name = "vdd_log";
+		regulator-min-microvolt = "\0\f5";
+		regulator-max-microvolt = <0x155cc0>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <0x83>;
+		phandle = <0x159>;
+	};
+
+	vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <0xc4 0x00 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0xc5>;
+		regulator-name = "vcc3v3_pcie";
+		regulator-always-on;
+		regulator-boot-on;
+		phandle = <0x15a>;
+	};
+
+	uwe-bsp {
+		compatible = "unisoc,uwe_bsp";
+		wl-reg-on = <0x23 0x0a 0x00>;
+		bt-reg-on = <0x23 0x09 0x00>;
+		wl-wake-host-gpio = <0x23 0x03 0x00>;
+		bt-wake-host-gpio = <0x23 0x04 0x00>;
+		sdio-ext-int-gpio = <0x18 0x1c 0x00>;
+		unisoc,btwf-file-name = "/lib/firmware/wcnmodem.bin";
+		data-irq;
+		blksz-512;
+		keep-power-on;
+		status = "okay";
+		phandle = <0x15b>;
+	};
+
+	sprd-mtty {
+		compatible = "sprd,mtty";
+		sprd,name = "ttyBT";
+		status = "okay";
+	};
+
+	__symbols__ {
+		cpu_l0 = "/cpus/cpu@0";
+		cpu_l1 = "/cpus/cpu@1";
+		cpu_l2 = "/cpus/cpu@2";
+		cpu_l3 = "/cpus/cpu@3";
+		cpu_b0 = "/cpus/cpu@100";
+		cpu_b1 = "/cpus/cpu@101";
+		CPU_SLEEP = "/cpus/idle-states/cpu-sleep";
+		CLUSTER_SLEEP = "/cpus/idle-states/cluster-sleep";
+		dmc = "/memory-controller";
+		xin24m = "/xin24m";
+		pcie0 = "/pcie@f8000000";
+		pcie0_intc = "/pcie@f8000000/interrupt-controller";
+		gmac = "/ethernet@fe300000";
+		sdio0 = "/mmc@fe310000";
+		sdmmc = "/mmc@fe320000";
+		sdhci = "/mmc@fe330000";
+		usb_host0_ehci = "/usb@fe380000";
+		usb_host0_ohci = "/usb@fe3a0000";
+		usb_host1_ehci = "/usb@fe3c0000";
+		usb_host1_ohci = "/usb@fe3e0000";
+		usbdrd3_0 = "/usb@fe800000";
+		usbdrd_dwc3_0 = "/usb@fe800000/usb@fe800000";
+		usbdrd3_1 = "/usb@fe900000";
+		usbdrd_dwc3_1 = "/usb@fe900000/usb@fe900000";
+		cdn_dp = "/dp@fec00000";
+		dp_in = "/dp@fec00000/ports/port";
+		dp_in_vopb = "/dp@fec00000/ports/port/endpoint@0";
+		dp_in_vopl = "/dp@fec00000/ports/port/endpoint@1";
+		gic = "/interrupt-controller@fee00000";
+		its = "/interrupt-controller@fee00000/interrupt-controller@fee20000";
+		ppi_cluster0 = "/interrupt-controller@fee00000/ppi-partitions/interrupt-partition-0";
+		ppi_cluster1 = "/interrupt-controller@fee00000/ppi-partitions/interrupt-partition-1";
+		saradc = "/saradc@ff100000";
+		i2c1 = "/i2c@ff110000";
+		es8316 = "/i2c@ff110000/codec@11";
+		es8316_p0_0 = "/i2c@ff110000/codec@11/port/endpoint";
+		i2c2 = "/i2c@ff120000";
+		i2c3 = "/i2c@ff130000";
+		i2c5 = "/i2c@ff140000";
+		i2c6 = "/i2c@ff150000";
+		i2c7 = "/i2c@ff160000";
+		uart0 = "/serial@ff180000";
+		uart1 = "/serial@ff190000";
+		uart2 = "/serial@ff1a0000";
+		uart3 = "/serial@ff1b0000";
+		spi0 = "/spi@ff1c0000";
+		spi1 = "/spi@ff1d0000";
+		spi2 = "/spi@ff1e0000";
+		spi4 = "/spi@ff1f0000";
+		spi5 = "/spi@ff200000";
+		thermal_zones = "/thermal-zones";
+		cpu_thermal = "/thermal-zones/cpu-thermal";
+		cpu_alert0 = "/thermal-zones/cpu-thermal/trips/cpu_alert0";
+		cpu_alert1 = "/thermal-zones/cpu-thermal/trips/cpu_alert1";
+		cpu_crit = "/thermal-zones/cpu-thermal/trips/cpu_crit";
+		gpu_thermal = "/thermal-zones/gpu-thermal";
+		gpu_alert0 = "/thermal-zones/gpu-thermal/trips/gpu_alert0";
+		gpu_crit = "/thermal-zones/gpu-thermal/trips/gpu_crit";
+		tsadc = "/tsadc@ff260000";
+		qos_emmc = "/qos@ffa58000";
+		qos_gmac = "/qos@ffa5c000";
+		qos_pcie = "/qos@ffa60080";
+		qos_usb_host0 = "/qos@ffa60100";
+		qos_usb_host1 = "/qos@ffa60180";
+		qos_usb_otg0 = "/qos@ffa70000";
+		qos_usb_otg1 = "/qos@ffa70080";
+		qos_sd = "/qos@ffa74000";
+		qos_sdioaudio = "/qos@ffa76000";
+		qos_hdcp = "/qos@ffa90000";
+		qos_iep = "/qos@ffa98000";
+		qos_isp0_m0 = "/qos@ffaa0000";
+		qos_isp0_m1 = "/qos@ffaa0080";
+		qos_isp1_m0 = "/qos@ffaa8000";
+		qos_isp1_m1 = "/qos@ffaa8080";
+		qos_rga_r = "/qos@ffab0000";
+		qos_rga_w = "/qos@ffab0080";
+		qos_video_m0 = "/qos@ffab8000";
+		qos_video_m1_r = "/qos@ffac0000";
+		qos_video_m1_w = "/qos@ffac0080";
+		qos_vop_big_r = "/qos@ffac8000";
+		qos_vop_big_w = "/qos@ffac8080";
+		qos_vop_little = "/qos@ffad0000";
+		qos_perihp = "/qos@ffad8080";
+		qos_gpu = "/qos@ffae0000";
+		pmu = "/power-management@ff310000";
+		power = "/power-management@ff310000/power-controller";
+		pmugrf = "/syscon@ff320000";
+		pmu_io_domains = "/syscon@ff320000/io-domains";
+		spi3 = "/spi@ff350000";
+		uart4 = "/serial@ff370000";
+		i2c0 = "/i2c@ff3c0000";
+		rk808 = "/i2c@ff3c0000/pmic@1b";
+		vdd_center = "/i2c@ff3c0000/pmic@1b/regulators/DCDC_REG1";
+		vdd_cpu_l = "/i2c@ff3c0000/pmic@1b/regulators/DCDC_REG2";
+		vcc_ddr = "/i2c@ff3c0000/pmic@1b/regulators/DCDC_REG3";
+		vcc_1v8 = "/i2c@ff3c0000/pmic@1b/regulators/DCDC_REG4";
+		vcc1v8_dvp = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG1";
+		vcc3v0_tp = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG2";
+		vcc1v8_pmu = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG3";
+		vcc_sdio = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG4";
+		vcca3v0_codec = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG5";
+		vcc_1v5 = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG6";
+		vcca1v8_codec = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG7";
+		vcc_3v0 = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG8";
+		vcc3v3_s3 = "/i2c@ff3c0000/pmic@1b/regulators/SWITCH_REG1";
+		vcc3v3_s0 = "/i2c@ff3c0000/pmic@1b/regulators/SWITCH_REG2";
+		vdd_cpu_b = "/i2c@ff3c0000/regulator@40";
+		vdd_gpu = "/i2c@ff3c0000/regulator@41";
+		i2c4 = "/i2c@ff3d0000";
+		i2c8 = "/i2c@ff3e0000";
+		pwm0 = "/pwm@ff420000";
+		pwm1 = "/pwm@ff420010";
+		pwm2 = "/pwm@ff420020";
+		pwm3 = "/pwm@ff420030";
+		dfi = "/dfi@ff630000";
+		vpu = "/video-codec@ff650000";
+		vpu_mmu = "/iommu@ff650800";
+		vdec = "/video-codec@ff660000";
+		vdec_mmu = "/iommu@ff660480";
+		iep = "/iep@ff670000";
+		iep_mmu = "/iommu@ff670800";
+		rga = "/rga@ff680000";
+		efuse0 = "/efuse@ff690000";
+		cpu_id = "/efuse@ff690000/cpu-id@7";
+		cpub_leakage = "/efuse@ff690000/cpu-leakage@17";
+		gpu_leakage = "/efuse@ff690000/gpu-leakage@18";
+		center_leakage = "/efuse@ff690000/center-leakage@19";
+		cpul_leakage = "/efuse@ff690000/cpu-leakage@1a";
+		logic_leakage = "/efuse@ff690000/logic-leakage@1b";
+		wafer_info = "/efuse@ff690000/wafer-info@1c";
+		dmac_bus = "/dma-controller@ff6d0000";
+		dmac_peri = "/dma-controller@ff6e0000";
+		pmucru = "/clock-controller@ff750000";
+		cru = "/clock-controller@ff760000";
+		grf = "/syscon@ff770000";
+		io_domains = "/syscon@ff770000/io-domains";
+		mipi_dphy_rx0 = "/syscon@ff770000/mipi-dphy-rx0";
+		u2phy0 = "/syscon@ff770000/usb2phy@e450";
+		u2phy0_host = "/syscon@ff770000/usb2phy@e450/host-port";
+		u2phy0_otg = "/syscon@ff770000/usb2phy@e450/otg-port";
+		u2phy1 = "/syscon@ff770000/usb2phy@e460";
+		u2phy1_host = "/syscon@ff770000/usb2phy@e460/host-port";
+		u2phy1_otg = "/syscon@ff770000/usb2phy@e460/otg-port";
+		emmc_phy = "/syscon@ff770000/phy@f780";
+		pcie_phy = "/syscon@ff770000/pcie-phy";
+		tcphy0 = "/phy@ff7c0000";
+		tcphy0_dp = "/phy@ff7c0000/dp-port";
+		tcphy0_usb3 = "/phy@ff7c0000/usb3-port";
+		tcphy1 = "/phy@ff800000";
+		tcphy1_dp = "/phy@ff800000/dp-port";
+		tcphy1_usb3 = "/phy@ff800000/usb3-port";
+		rktimer = "/rktimer@ff850000";
+		spdif = "/spdif@ff870000";
+		i2s0 = "/i2s@ff880000";
+		i2s0_p0 = "/i2s@ff880000/port";
+		i2s0_p0_0 = "/i2s@ff880000/port/endpoint";
+		i2s1 = "/i2s@ff890000";
+		i2s2 = "/i2s@ff8a0000";
+		vopl = "/vop@ff8f0000";
+		vopl_out = "/vop@ff8f0000/port";
+		vopl_out_mipi = "/vop@ff8f0000/port/endpoint@0";
+		vopl_out_edp = "/vop@ff8f0000/port/endpoint@1";
+		vopl_out_mipi1 = "/vop@ff8f0000/port/endpoint@3";
+		vopl_out_dp = "/vop@ff8f0000/port/endpoint@4";
+		vopl_mmu = "/iommu@ff8f3f00";
+		vopb = "/vop@ff900000";
+		vopb_out = "/vop@ff900000/port";
+		vopb_out_edp = "/vop@ff900000/port/endpoint@0";
+		vopb_out_mipi = "/vop@ff900000/port/endpoint@1";
+		vopb_out_hdmi = "/vop@ff900000/port/endpoint@2";
+		vopb_out_mipi1 = "/vop@ff900000/port/endpoint@3";
+		vopb_out_dp = "/vop@ff900000/port/endpoint@4";
+		vopb_mmu = "/iommu@ff903f00";
+		isp0 = "/isp0@ff910000";
+		isp0_mmu = "/iommu@ff914000";
+		isp1 = "/isp1@ff920000";
+		isp1_mmu = "/iommu@ff924000";
+		hdmi_sound = "/hdmi-sound";
+		hdmi = "/hdmi@ff940000";
+		hdmi_in = "/hdmi@ff940000/ports/port";
+		hdmi_in_vopb = "/hdmi@ff940000/ports/port/endpoint@0";
+		mipi_dsi = "/mipi@ff960000";
+		mipi_in = "/mipi@ff960000/ports/port@0";
+		mipi_in_vopb = "/mipi@ff960000/ports/port@0/endpoint@0";
+		mipi_in_vopl = "/mipi@ff960000/ports/port@0/endpoint@1";
+		mipi_dsi1 = "/mipi@ff968000";
+		mipi1_in = "/mipi@ff968000/ports/port@0";
+		mipi1_in_vopb = "/mipi@ff968000/ports/port@0/endpoint@0";
+		mipi1_in_vopl = "/mipi@ff968000/ports/port@0/endpoint@1";
+		edp = "/edp@ff970000";
+		edp_in = "/edp@ff970000/ports/port@0";
+		edp_in_vopb = "/edp@ff970000/ports/port@0/endpoint@0";
+		edp_in_vopl = "/edp@ff970000/ports/port@0/endpoint@1";
+		gpu = "/gpu@ff9a0000";
+		pinctrl = "/pinctrl";
+		gpio0 = "/pinctrl/gpio@ff720000";
+		gpio1 = "/pinctrl/gpio@ff730000";
+		gpio2 = "/pinctrl/gpio@ff780000";
+		gpio3 = "/pinctrl/gpio@ff788000";
+		gpio4 = "/pinctrl/gpio@ff790000";
+		pcfg_pull_up = "/pinctrl/pcfg-pull-up";
+		pcfg_pull_down = "/pinctrl/pcfg-pull-down";
+		pcfg_pull_none = "/pinctrl/pcfg-pull-none";
+		pcfg_pull_none_12ma = "/pinctrl/pcfg-pull-none-12ma";
+		pcfg_pull_none_13ma = "/pinctrl/pcfg-pull-none-13ma";
+		pcfg_pull_none_18ma = "/pinctrl/pcfg-pull-none-18ma";
+		pcfg_pull_none_20ma = "/pinctrl/pcfg-pull-none-20ma";
+		pcfg_pull_up_2ma = "/pinctrl/pcfg-pull-up-2ma";
+		pcfg_pull_up_8ma = "/pinctrl/pcfg-pull-up-8ma";
+		pcfg_pull_up_18ma = "/pinctrl/pcfg-pull-up-18ma";
+		pcfg_pull_up_20ma = "/pinctrl/pcfg-pull-up-20ma";
+		pcfg_pull_down_4ma = "/pinctrl/pcfg-pull-down-4ma";
+		pcfg_pull_down_8ma = "/pinctrl/pcfg-pull-down-8ma";
+		pcfg_pull_down_12ma = "/pinctrl/pcfg-pull-down-12ma";
+		pcfg_pull_down_18ma = "/pinctrl/pcfg-pull-down-18ma";
+		pcfg_pull_down_20ma = "/pinctrl/pcfg-pull-down-20ma";
+		pcfg_output_high = "/pinctrl/pcfg-output-high";
+		pcfg_output_low = "/pinctrl/pcfg-output-low";
+		pcfg_input_enable = "/pinctrl/pcfg-input-enable";
+		pcfg_input_pull_up = "/pinctrl/pcfg-input-pull-up";
+		pcfg_input_pull_down = "/pinctrl/pcfg-input-pull-down";
+		clk_32k = "/pinctrl/clock/clk-32k";
+		cif_clkin = "/pinctrl/cif/cif-clkin";
+		cif_clkouta = "/pinctrl/cif/cif-clkouta";
+		edp_hpd = "/pinctrl/edp/edp-hpd";
+		rgmii_pins = "/pinctrl/gmac/rgmii-pins";
+		rmii_pins = "/pinctrl/gmac/rmii-pins";
+		phy_intb = "/pinctrl/gmac/phy-intb";
+		phy_rstb = "/pinctrl/gmac/phy-rstb";
+		i2c0_xfer = "/pinctrl/i2c0/i2c0-xfer";
+		i2c1_xfer = "/pinctrl/i2c1/i2c1-xfer";
+		i2c2_xfer = "/pinctrl/i2c2/i2c2-xfer";
+		i2c3_xfer = "/pinctrl/i2c3/i2c3-xfer";
+		i2c4_xfer = "/pinctrl/i2c4/i2c4-xfer";
+		i2c5_xfer = "/pinctrl/i2c5/i2c5-xfer";
+		i2c6_xfer = "/pinctrl/i2c6/i2c6-xfer";
+		i2c7_xfer = "/pinctrl/i2c7/i2c7-xfer";
+		i2c8_xfer = "/pinctrl/i2c8/i2c8-xfer";
+		i2s0_2ch_bus = "/pinctrl/i2s0/i2s0-2ch-bus";
+		i2s0_8ch_bus = "/pinctrl/i2s0/i2s0-8ch-bus";
+		i2s0_8ch_bus_bclk_off = "/pinctrl/i2s0/i2s0-8ch-bus-bclk-off";
+		i2s1_2ch_bus = "/pinctrl/i2s1/i2s1-2ch-bus";
+		i2s1_2ch_bus_bclk_off = "/pinctrl/i2s1/i2s1-2ch-bus-bclk-off";
+		i2s_8ch_mclk = "/pinctrl/i2s1/i2s-8ch-mclk";
+		sdio0_bus1 = "/pinctrl/sdio0/sdio0-bus1";
+		sdio0_bus4 = "/pinctrl/sdio0/sdio0-bus4";
+		sdio0_cmd = "/pinctrl/sdio0/sdio0-cmd";
+		sdio0_clk = "/pinctrl/sdio0/sdio0-clk";
+		sdio0_cd = "/pinctrl/sdio0/sdio0-cd";
+		sdio0_pwr = "/pinctrl/sdio0/sdio0-pwr";
+		sdio0_bkpwr = "/pinctrl/sdio0/sdio0-bkpwr";
+		sdio0_wp = "/pinctrl/sdio0/sdio0-wp";
+		sdio0_int = "/pinctrl/sdio0/sdio0-int";
+		sdmmc_bus1 = "/pinctrl/sdmmc/sdmmc-bus1";
+		sdmmc_bus4 = "/pinctrl/sdmmc/sdmmc-bus4";
+		sdmmc_clk = "/pinctrl/sdmmc/sdmmc-clk";
+		sdmmc_cmd = "/pinctrl/sdmmc/sdmmc-cmd";
+		sdmmc_cd = "/pinctrl/sdmmc/sdmmc-cd";
+		sdmmc_wp = "/pinctrl/sdmmc/sdmmc-wp";
+		ap_pwroff = "/pinctrl/suspend/ap-pwroff";
+		ddrio_pwroff = "/pinctrl/suspend/ddrio-pwroff";
+		spdif_bus = "/pinctrl/spdif/spdif-bus";
+		spdif_bus_1 = "/pinctrl/spdif/spdif-bus-1";
+		spi0_clk = "/pinctrl/spi0/spi0-clk";
+		spi0_cs0 = "/pinctrl/spi0/spi0-cs0";
+		spi0_cs1 = "/pinctrl/spi0/spi0-cs1";
+		spi0_tx = "/pinctrl/spi0/spi0-tx";
+		spi0_rx = "/pinctrl/spi0/spi0-rx";
+		spi1_clk = "/pinctrl/spi1/spi1-clk";
+		spi1_cs0 = "/pinctrl/spi1/spi1-cs0";
+		spi1_rx = "/pinctrl/spi1/spi1-rx";
+		spi1_tx = "/pinctrl/spi1/spi1-tx";
+		spi2_clk = "/pinctrl/spi2/spi2-clk";
+		spi2_cs0 = "/pinctrl/spi2/spi2-cs0";
+		spi2_rx = "/pinctrl/spi2/spi2-rx";
+		spi2_tx = "/pinctrl/spi2/spi2-tx";
+		spi3_clk = "/pinctrl/spi3/spi3-clk";
+		spi3_cs0 = "/pinctrl/spi3/spi3-cs0";
+		spi3_rx = "/pinctrl/spi3/spi3-rx";
+		spi3_tx = "/pinctrl/spi3/spi3-tx";
+		spi4_clk = "/pinctrl/spi4/spi4-clk";
+		spi4_cs0 = "/pinctrl/spi4/spi4-cs0";
+		spi4_rx = "/pinctrl/spi4/spi4-rx";
+		spi4_tx = "/pinctrl/spi4/spi4-tx";
+		spi5_clk = "/pinctrl/spi5/spi5-clk";
+		spi5_cs0 = "/pinctrl/spi5/spi5-cs0";
+		spi5_rx = "/pinctrl/spi5/spi5-rx";
+		spi5_tx = "/pinctrl/spi5/spi5-tx";
+		test_clkout0 = "/pinctrl/testclk/test-clkout0";
+		test_clkout1 = "/pinctrl/testclk/test-clkout1";
+		test_clkout2 = "/pinctrl/testclk/test-clkout2";
+		otp_pin = "/pinctrl/tsadc/otp-pin";
+		otp_out = "/pinctrl/tsadc/otp-out";
+		uart0_xfer = "/pinctrl/uart0/uart0-xfer";
+		uart0_cts = "/pinctrl/uart0/uart0-cts";
+		uart0_rts = "/pinctrl/uart0/uart0-rts";
+		uart1_xfer = "/pinctrl/uart1/uart1-xfer";
+		uart2a_xfer = "/pinctrl/uart2a/uart2a-xfer";
+		uart2b_xfer = "/pinctrl/uart2b/uart2b-xfer";
+		uart2c_xfer = "/pinctrl/uart2c/uart2c-xfer";
+		uart3_xfer = "/pinctrl/uart3/uart3-xfer";
+		uart3_cts = "/pinctrl/uart3/uart3-cts";
+		uart3_rts = "/pinctrl/uart3/uart3-rts";
+		uart4_xfer = "/pinctrl/uart4/uart4-xfer";
+		uarthdcp_xfer = "/pinctrl/uarthdcp/uarthdcp-xfer";
+		pwm0_pin = "/pinctrl/pwm0/pwm0-pin";
+		pwm0_pin_pull_down = "/pinctrl/pwm0/pwm0-pin-pull-down";
+		vop0_pwm_pin = "/pinctrl/pwm0/vop0-pwm-pin";
+		vop1_pwm_pin = "/pinctrl/pwm0/vop1-pwm-pin";
+		pwm1_pin = "/pinctrl/pwm1/pwm1-pin";
+		pwm1_pin_pull_down = "/pinctrl/pwm1/pwm1-pin-pull-down";
+		pwm2_pin = "/pinctrl/pwm2/pwm2-pin";
+		pwm2_pin_pull_down = "/pinctrl/pwm2/pwm2-pin-pull-down";
+		pwm3a_pin = "/pinctrl/pwm3a/pwm3a-pin";
+		pwm3b_pin = "/pinctrl/pwm3b/pwm3b-pin";
+		hdmi_i2c_xfer = "/pinctrl/hdmi/hdmi-i2c-xfer";
+		hdmi_cec = "/pinctrl/hdmi/hdmi-cec";
+		pcie_clkreqn_cpm = "/pinctrl/pcie/pci-clkreqn-cpm";
+		pcie_clkreqnb_cpm = "/pinctrl/pcie/pci-clkreqnb-cpm";
+		pcie_pwr_en = "/pinctrl/pcie/pcie-pwr-en";
+		cpu_b_sleep = "/pinctrl/pmic/cpu-b-sleep";
+		gpu_sleep = "/pinctrl/pmic/gpu-sleep";
+		pmic_int_l = "/pinctrl/pmic/pmic-int-l";
+		sdmmc0_pwr_h = "/pinctrl/sd/sdmmc0-pwr-h";
+		vcc5v0_host_en = "/pinctrl/usb2/vcc5v0-host-en";
+		vcc5v0_typec_en = "/pinctrl/usb2/vcc5v0-typec-en";
+		wifi_reg_on_h = "/pinctrl/sdio-pwrseq/wifi-reg-on-h";
+		bt_reg_on_h = "/pinctrl/bluetooth/bt-enable-h";
+		bt_host_wake_l = "/pinctrl/bluetooth/bt-host-wake-l";
+		bt_wake_l = "/pinctrl/bluetooth/bt-wake-l";
+		chg_cc_int_l = "/pinctrl/fusb302/chg-cc-int-l";
+		cluster0_opp = "/opp-table-0";
+		cluster1_opp = "/opp-table-1";
+		gpu_opp_table = "/opp-table-2";
+		clkin_gmac = "/external-gmac-clock";
+		sdio_pwrseq = "/sdio-pwrseq";
+		usb_vbus = "/usb-vbus";
+		usb3_vbus = "/usb3-vbus";
+		vbus_typec = "/vbus-typec";
+		vcc_0v9 = "/vcc-0v9";
+		vcc3v0_sd = "/vcc3v0-sd";
+		vcc3v3_sys = "/vcc3v3-sys";
+		vcc5v0_sys = "/vcc5v0-sys";
+		vcc_sys = "/vcc-sys";
+		vdd_log = "/vdd-log";
+		vcc3v3_pcie = "/vcc3v3-pcie-regulator";
+		unisoc_uwe_bsp = "/uwe-bsp";
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-8897-ddr4-v1-linux-base.dts b/arch/arm64/boot/dts/rockchip/rk3568-8897-ddr4-v1-linux-base.dts
new file mode 100644
index 0000000000000000000000000000000000000000..f0303402201a410a78ff08354af9589af0996beb
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-8897-ddr4-v1-linux-base.dts
@@ -0,0 +1,569 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#include "rk3568-evb1-ddr4-v10.dtsi"
+#include "rk3568-linux.dtsi"
+#include <dt-bindings/display/rockchip_vop.h>
+
+/ {
+    boardtype = "RK3568 8897 board V1 (linux base)";
+
+	chosen: chosen {
+		bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait";
+	};
+
+	fiq-debugger {
+		compatible = "rockchip,fiq-debugger";
+		rockchip,serial-id = <2>;
+		rockchip,wake-irq = <0>;
+		/* If enable uart uses irq instead of fiq */
+		rockchip,irq-mode-enable = <1>;
+		rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
+		interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart2m0_xfer>;
+		status = "okay";
+	};
+
+    lvds_panel: lvds-panel {
+		compatible = "simple-panel";
+        status = "disabled";
+    };
+
+    edp_panel: edp-panel {
+        compatible ="simple-panel";
+        status = "disabled";
+    };
+
+    ryd_gpio_control:ryd-gpio-control {
+        compatible = "ryd_gpio_control";
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&gl3523_reset &usb_host_en &hub_rst &gpio3_a4_mux &gpio3_a5_mux &gpio3_b5 &gpio3_c1 &gpio0_c4>;
+        status = "okay";
+
+	   	gl3523_rst: gl3523-rst {
+		    gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+            //can set dir_in, default is dir_out
+		    pull_cfg = <0>; //<0>=null, <1>=pulldown, <2>=pullup
+		    sys_create;  // if set, will export the gpio in sysfs
+		    export;
+	    };
+
+	   	usb_host_en{
+		    gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+            //can set dir_in, default is dir_out
+		    pull_cfg = <0>; //<0>=null, <1>=pulldown, <2>=pullup
+		    sys_create;  // if set, will export the gpio in sysfs
+		    export;
+	    };
+/*
+	   	pcie_pwren{
+		    gpio = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>;
+            //can set dir_in, default is dir_out
+		    pull_cfg = <0>; //<0>=null, <1>=pulldown, <2>=pullup
+		    //sys_create;  // if set, will export the gpio in sysfs
+		    //export;
+	    };
+*/
+	    hub_rst {
+		    gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
+            //can set dir_in, default is dir_out
+		    pull_cfg = <0>; //<0>=null, <1>=pulldown, <2>=pullup
+		    //sys_create;  // if set, will export the gpio in sysfs
+	    };
+
+	    gpio3_a4:gpio3_a4   {
+		    gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
+            //can set dir_in, default is dir_out
+		    pull_cfg = <0>; //<0>=null, <1>=pulldown, <2>=pullup
+		    sys_create;  // if set, will export the gpio in sysfs
+		    export;
+	    };
+
+	    gpio3_a5:gpio3_a5  {
+		    gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
+            //can set dir_in, default is dir_out
+		    pull_cfg = <0>; //<0>=null, <1>=pulldown, <2>=pullup
+		    sys_create;  // if set, will export the gpio in sysfs
+		    export;
+	    };
+
+	    gpio3_b5 {
+		    gpio = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
+            //can set dir_in, default is dir_out
+		    pull_cfg = <0>; //<0>=null, <1>=pulldown, <2>=pullup
+		    sys_create;  // if set, will export the gpio in sysfs
+		    export;
+	    };
+	    gpio3_c1{
+		    gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+            //can set dir_in, default is dir_out
+		    pull_cfg = <0>; //<0>=null, <1>=pulldown, <2>=pullup
+		    sys_create;  // if set, will export the gpio in sysfs
+		    export;
+	    };
+	   	gpio0_c4{
+		    gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+            //can set dir_in, default is dir_out
+		    pull_cfg = <0>; //<0>=null, <1>=pulldown, <2>=pullup
+		    sys_create;  // if set, will export the gpio in sysfs
+		    export;
+	    };
+    };
+
+	rk_modem: rk-modem {
+		compatible="4g-modem-platdata";
+		pinctrl-names = "default";
+		pinctrl-0 = <&lte_power_en &lte_reset>;
+		4G,vbat-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
+        4G,disable = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
+		4G,power = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+		4G,reset = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+/*
+    usb_host_en: usb-host-en {
+        compatible = "regulator-fixed";
+        regulator-name = "usb-host-en";
+        gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        enable-active-high;
+        regulator-always-on;
+        regulator-boot-on;
+    };
+*/
+	vcc5v0_host1: vcc5v0-host1-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host1_en>;
+		regulator-name = "vcc5v0_host1";
+		regulator-always-on;
+	};
+
+	pcie30_3v3: gpio-regulator {
+		compatible = "regulator-gpio";
+		regulator-name = "pcie30_3v3";
+		regulator-min-microvolt = <100000>;
+		regulator-max-microvolt = <3300000>;
+		gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>;
+		gpios-states = <0x1>;
+		states = <100000 0x0
+			  3300000 0x1>;
+	};
+};
+
+&wireless_bluetooth {
+	compatible = "bluetooth-platdata";
+	clocks = <&rk809 1>;
+	clock-names = "ext_clock";
+	//wifi-bt-power-toggle;
+	uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default", "rts_gpio";
+	pinctrl-0 = <&uart8m0_rtsn>;
+	pinctrl-1 = <&uart8_gpios>;
+	BT,reset_gpio    = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+	BT,wake_gpio     = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+	BT,wake_host_irq = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&gmac0 {
+	snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&gmac1 {
+	snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+// EDP1 backlight
+&pwm4 {
+    status = "okay";
+    pinctrl-names = "active";
+    pinctrl-0 = <&pwm4_pins>;
+};
+
+&pwm5 {
+    status = "disabled";
+};
+
+&pwm6 {
+    status = "okay";
+    pinctrl-names = "active";
+    pinctrl-0 = <&pwm6_pins>;
+};
+
+// LVDS backlight
+&pwm7 {
+    status = "disabled";
+    pinctrl-names = "active";
+    pinctrl-0 = <&pwm7_pins>;
+};
+
+&dmc {
+    compatible = "rockchip,rk3568-dmc";
+    interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+    interrupt-names = "complete";
+    devfreq-events = <&dfi>;
+    //clocks = <&cru SCLK_DDRCLK>;
+    clock-names = "dmc_clk";
+    operating-points-v2 = <&dmc_opp_table>;
+
+    system-status-freq = <
+        /*system status         freq(KHz)*/
+        SYS_STATUS_NORMAL       780000
+        SYS_STATUS_REBOOT       1184000
+        SYS_STATUS_SUSPEND      324000
+        SYS_STATUS_VIDEO_4K     780000
+        SYS_STATUS_VIDEO_4K_10B 780000
+        SYS_STATUS_BOOST        1184000
+        SYS_STATUS_ISP          1184000
+        SYS_STATUS_PERFORMANCE  1184000
+        SYS_STATUS_DUALVIEW     1184000
+    >;
+
+    status = "okay";
+};
+
+&dmc_opp_table{
+    compatible = "operating-points-v2";
+
+    mbist-vmin = <825000 900000 950000>;
+    nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>;
+    nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
+    rockchip,temp-hysteresis = <5000>;
+    rockchip,low-temp = <0>;
+    rockchip,low-temp-adjust-volt = <
+        /* MHz    MHz    uV */
+            0      1560   25000
+    >;
+    rockchip,leakage-voltage-sel = <
+            1   80    0
+            81  254   1
+    >;
+
+    opp-324000000 {
+        opp-hz = /bits/ 64 <324000000>;
+        opp-microvolt = <900000>;
+        opp-microvolt-L0 = <900000>;
+        opp-microvolt-L1 = <850000>;
+    };
+    opp-528000000 {
+        opp-hz = /bits/ 64 <528000000>;
+        opp-microvolt = <900000>;
+        opp-microvolt-L0 = <900000>;
+        opp-microvolt-L1 = <850000>;
+    };
+    opp-780000000 {
+        opp-hz = /bits/ 64 <780000000>;
+        opp-microvolt = <900000>;
+        opp-microvolt-L0 = <900000>;
+        opp-microvolt-L1 = <850000>;
+    };
+    opp-920000000 {
+        opp-hz = /bits/ 64 <920000000>;
+        opp-microvolt = <900000>;
+        opp-microvolt-L0 = <900000>;
+        opp-microvolt-L1 = <850000>;
+    };
+    opp-1184000000 {
+        opp-hz = /bits/ 64 <1184000000>;
+        opp-microvolt = <900000>;
+        opp-microvolt-L0 = <900000>;
+        opp-microvolt-L1 = <850000>;
+    };
+    opp-1560000000 {
+        opp-hz = /bits/ 64 <1560000000>;
+        opp-microvolt = <900000>;
+        opp-microvolt-L0 = <900000>;
+        opp-microvolt-L1 = <850000>;
+        status = "disabled";
+    };
+};
+
+&i2c0 {
+    status = "okay";
+};
+
+&i2c4 {
+    status = "disabled";
+};
+
+&i2c5 {
+    status = "okay";
+
+	hym8563: hym8563@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+
+		#clock-cells = <0>;
+		clock-output-names = "xin32k";
+	};
+};
+
+&rk809 {
+	rtc {
+		status = "disabled";
+	};
+};
+
+// MIPI-DSI configuration
+&dsi0 {
+	status = "disabled";
+};
+
+
+&dsi0_in_vp0 {
+	status = "disabled";
+};
+
+&dsi0_in_vp1 {
+    status = "disabled";
+};
+
+&sdmmc0 {
+	max-frequency = <150000000>;
+	supports-sd;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	status = "okay";
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+
+};
+
+&vcc3v3_lcd0_n {
+	gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+	enable-active-high;
+    regulator-always-on;
+};
+
+&vcc3v3_lcd1_n {
+	gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+	enable-active-high;
+    regulator-always-on;
+};
+
+&backlight {
+    status = "okay";
+	pwms = <&pwm4 0 500000 0>;
+    enable-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
+    pinctrl-0 = <&lcd0_bl_en>;      
+	brightness-levels = <
+			255	254	253	252	251	250	249	248	
+		 	247 246 245 244 243 242 241 240
+			239 238 237 236 235 234 233 232 
+			231 230 229 228 227 226 225 224 
+			223 222 221 220 219 218 217 216 
+			215 214 213 212 211 210 209 208 
+			207 206 205 204 203 202 201 200 
+			199 198 197 196 195 194 193 192 
+			191 190 189 188 187 186 185 184 
+			183 182 181 180 179 178 177 176 
+			175 174 173 172 171 170 169 168 
+			167 166 165 164 163 162 161 160 
+			159 158 157 156 155 154 153 152 
+			151 150 149 148 147 146 145 144 
+			143 142 141 140 139 138 137 136 
+			135 134 133 132 131 130 129 128 
+			127 126 125 124 123 122 121 120 
+			119 118 117 116 115 114 113 112 
+			111 110 109 108 107 106 105 104 
+			103 102 101 100 99 	98 	97 	96 
+			95 	94 	93 	92 	91 	90 	89 	88 
+			87 	86 	85 	84 	83 	82 	81 	80 
+			79 	78 	77 	76 	75 	74 	73	72 
+			71 	70 	69 	68 	67 	66 	65 	64 
+			63 	62 	61 	60 	59 	58 	57 	56 
+			55 	54 	53 	52 	51 	50 	49 	48 
+			47 	46 	45 	44 	43 	42 	41 	40 
+			39 	38 	37 	36 	35 	34 	33 	32 
+			31 	30 	29 	28 	27 	26 	25 	24 
+			23 	22 	21 	20	19	18	17	16
+			15	14	13	12	11	10	9	8
+			7	6	5	4	3	2	1	0>;
+	default-brightness-level = <200>;
+};
+
+&uart0 {
+    status = "disabled";
+};
+
+&uart1 {
+    status = "disabled";
+    pinctrl-names = "default";
+    pinctrl-0 = <&uart1m1_xfer>;
+};
+&uart3 {
+    status = "okay";
+    pinctrl-names = "default";
+    pinctrl-0 = <&uart3m1_xfer>;
+};
+&uart4 {
+    status = "okay";
+    pinctrl-names = "default";
+    pinctrl-0 = <&uart4m1_xfer>;
+};
+&uart7 {
+    status = "okay";
+    pinctrl-names = "default";
+    pinctrl-0 = <&uart7m1_xfer>;
+};
+&uart9 {
+    status = "okay";
+    pinctrl-names = "default";
+    pinctrl-0 = <&uart9m1_xfer>;
+};
+
+
+// MUST disable PCI-E function, 
+// otherwise kernel will stall
+&pcie30phy {
+    status = "okay";
+};
+
+&pcie3x2 {
+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&pcie30_3v3>;
+	max-link-speed= <3>;
+	status = "okay";
+};
+
+&rk809_codec {
+    status = "okay";
+    hp-volume = <3>;
+    spk-ctl-gpios =<&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&spk_ctl_gpios &i2s1m0_mclk>;
+    spk-volume = <3>;
+};
+
+&pwm11 {
+    status = "disabled";
+};
+
+&spdif_out {
+    status = "disabled";
+};
+
+&spdif_8ch {
+    status = "disabled";
+};
+
+&can1 {
+    status = "okay";
+
+	assigned-clocks = <&cru CLK_CAN1>;
+	assigned-clock-rates = <100000000>;
+};
+
+&usbdrd_dwc3 {
+    dr_mode = "host";
+    status = "okay";
+};
+
+&pinctrl {
+    backlight {
+        lcd0_bl_en: lcd0_bl_en {
+            rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
+        };
+/*
+        lcd1_bl_en: lcd1_bl_en {
+            rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+        };
+*/
+    };
+    rk809{
+        spk_ctl_gpios: spk-ctl-gpios{
+           rockchip,pins = <RK_GPIO4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+        };
+    };
+    pwm4 {
+        pwm4_pins: pwm4-pins {
+            rockchip,pins = <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
+        };
+    };
+    pwm6 {
+        pwm6_pins: pwm6-pins {
+            rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
+        };
+    };
+    usb {
+        vcc5v0_host1_en: vcc5v0-host1-en {
+            rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+        };
+    };
+    rk-modem {
+        lte_power_en: lte-power-en {
+            rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+        };
+        lte_reset: lte-reset {
+            rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+        };
+    };
+
+    ryd_gpio_control {
+        gl3523_reset: gl3523-reset {
+            rockchip,pins = <RK_GPIO4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+        };
+        hub_rst: usb-otg-en {
+            rockchip,pins = <RK_GPIO3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+        };
+        usb_host_en: usb-host-en {
+            rockchip,pins = <RK_GPIO0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+        cash_pr_en: cash-pr-en {
+            rockchip,pins = <RK_GPIO3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+        };
+
+        gpio3_a4_mux: gpio3-a4-mux {
+            rockchip,pins = <RK_GPIO3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+        };
+        gpio3_a5_mux: gpio3-a5-mux {
+            rockchip,pins = <RK_GPIO3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+        };
+
+        gpio3_b5: gpio3-b5 {
+            rockchip,pins = <RK_GPIO3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+        };
+        gpio3_c1: gpio3-c1 {
+            rockchip,pins = <RK_GPIO3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+        };
+        gpio0_c4: gpio0-c4 {
+            rockchip,pins = <RK_GPIO0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+        };
+    };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-8897-ddr4-v1-linux-hdmi.dts b/arch/arm64/boot/dts/rockchip/rk3568-8897-ddr4-v1-linux-hdmi.dts
new file mode 100644
index 0000000000000000000000000000000000000000..3e81b4bef98a59264e0cd1142c9674f22bf63baa
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-8897-ddr4-v1-linux-hdmi.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#include "rk3568-8897-ddr4-v1-linux-base.dts"
+
+/ {
+	model = "RK3568 8897 V1 Board HDMI";
+};
+
+&video_phy0 {
+    status = "okay";
+};
+
+&hdmi {
+    status = "okay";
+};
+
+&route_hdmi {
+	status = "okay";
+	connect = <&vp0_out_hdmi>;
+};
+
+&hdmi_in_vp0 {
+    status = "okay";
+};
+
+&hdmi_in_vp1 {
+    status = "disabled";
+};
+
+&hdmi_sound {
+    status = "okay";
+};
+
+&edp {
+    status = "disabled";
+};
+
+&edp_in_vp0 {
+    status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..9be417bdb759f3c474260e78f1b1383ea2c9da07
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi
@@ -0,0 +1,1837 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/input/rk-input.h>
+#include <dt-bindings/display/drm_mipi_dsi.h>
+#include <dt-bindings/sensor-dev.h>
+
+/ {
+
+	adc_keys: adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		vol-up-key {
+			label = "volume up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <1750>;
+		};
+
+		vol-down-key {
+			label = "volume down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			press-threshold-microvolt = <297500>;
+		};
+
+		menu-key {
+			label = "menu";
+			linux,code = <KEY_MENU>;
+			press-threshold-microvolt = <980000>;
+		};
+
+		back-key {
+			label = "back";
+			linux,code = <KEY_BACK>;
+			press-threshold-microvolt = <1305500>;
+		};
+	};
+
+	audiopwmout_diff: audiopwmout-diff {
+		status = "disabled";
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "rockchip,audiopwmout-diff";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,bitclock-master = <&master>;
+		simple-audio-card,frame-master = <&master>;
+		simple-audio-card,cpu {
+			sound-dai = <&i2s3_2ch>;
+		};
+		master: simple-audio-card,codec {
+			sound-dai = <&dig_acodec>;
+		};
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm4 0 25000 0>;
+		brightness-levels = <
+			  0  20  20  21  21  22  22  23
+			 23  24  24  25  25  26  26  27
+			 27  28  28  29  29  30  30  31
+			 31  32  32  33  33  34  34  35
+			 35  36  36  37  37  38  38  39
+			 40  41  42  43  44  45  46  47
+			 48  49  50  51  52  53  54  55
+			 56  57  58  59  60  61  62  63
+			 64  65  66  67  68  69  70  71
+			 72  73  74  75  76  77  78  79
+			 80  81  82  83  84  85  86  87
+			 88  89  90  91  92  93  94  95
+			 96  97  98  99 100 101 102 103
+			104 105 106 107 108 109 110 111
+			112 113 114 115 116 117 118 119
+			120 121 122 123 124 125 126 127
+			128 129 130 131 132 133 134 135
+			136 137 138 139 140 141 142 143
+			144 145 146 147 148 149 150 151
+			152 153 154 155 156 157 158 159
+			160 161 162 163 164 165 166 167
+			168 169 170 171 172 173 174 175
+			176 177 178 179 180 181 182 183
+			184 185 186 187 188 189 190 191
+			192 193 194 195 196 197 198 199
+			200 201 202 203 204 205 206 207
+			208 209 210 211 212 213 214 215
+			216 217 218 219 220 221 222 223
+			224 225 226 227 228 229 230 231
+			232 233 234 235 236 237 238 239
+			240 241 242 243 244 245 246 247
+			248 249 250 251 252 253 254 255
+		>;
+		default-brightness-level = <200>;
+	};
+
+	backlight1: backlight1 {
+		compatible = "pwm-backlight";
+		pwms = <&pwm5 0 25000 0>;
+		brightness-levels = <
+			  0  20  20  21  21  22  22  23
+			 23  24  24  25  25  26  26  27
+			 27  28  28  29  29  30  30  31
+			 31  32  32  33  33  34  34  35
+			 35  36  36  37  37  38  38  39
+			 40  41  42  43  44  45  46  47
+			 48  49  50  51  52  53  54  55
+			 56  57  58  59  60  61  62  63
+			 64  65  66  67  68  69  70  71
+			 72  73  74  75  76  77  78  79
+			 80  81  82  83  84  85  86  87
+			 88  89  90  91  92  93  94  95
+			 96  97  98  99 100 101 102 103
+			104 105 106 107 108 109 110 111
+			112 113 114 115 116 117 118 119
+			120 121 122 123 124 125 126 127
+			128 129 130 131 132 133 134 135
+			136 137 138 139 140 141 142 143
+			144 145 146 147 148 149 150 151
+			152 153 154 155 156 157 158 159
+			160 161 162 163 164 165 166 167
+			168 169 170 171 172 173 174 175
+			176 177 178 179 180 181 182 183
+			184 185 186 187 188 189 190 191
+			192 193 194 195 196 197 198 199
+			200 201 202 203 204 205 206 207
+			208 209 210 211 212 213 214 215
+			216 217 218 219 220 221 222 223
+			224 225 226 227 228 229 230 231
+			232 233 234 235 236 237 238 239
+			240 241 242 243 244 245 246 247
+			248 249 250 251 252 253 254 255
+		>;
+		default-brightness-level = <200>;
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	hdmi_sound: hdmi-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <128>;
+		simple-audio-card,name = "rockchip,hdmi";
+		status = "disabled";
+
+		simple-audio-card,cpu {
+				sound-dai = <&i2s0_8ch>;
+		};
+		simple-audio-card,codec {
+				sound-dai = <&hdmi>;
+		};
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+		work_led: work {
+			gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	pdmics: dummy-codec {
+		status = "disabled";
+		compatible = "rockchip,dummy-codec";
+		#sound-dai-cells = <0>;
+	};
+
+	pdm_mic_array: pdm-mic-array {
+		status = "disabled";
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "rockchip,pdm-mic-array";
+		simple-audio-card,cpu {
+			sound-dai = <&pdm>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&pdmics>;
+		};
+	};
+
+	rk809_sound: rk809-sound {
+		status = "okay";
+		compatible = "rockchip,multicodecs-card";
+		rockchip,card-name = "rockchip-rk809";
+		hp-det-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
+		rockchip,format = "i2s";
+		rockchip,mclk-fs = <256>;
+		rockchip,cpu = <&i2s1_8ch>;
+		rockchip,codec = <&rk809_codec>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_det>;
+	};
+
+	spdif-sound {
+		status = "okay";
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "ROCKCHIP,SPDIF";
+		simple-audio-card,cpu {
+				sound-dai = <&spdif_8ch>;
+		};
+		simple-audio-card,codec {
+				sound-dai = <&spdif_out>;
+		};
+	};
+
+	spdif_out: spdif-out {
+			status = "okay";
+			compatible = "linux,spdif-dit";
+			#sound-dai-cells = <0>;
+	};
+
+	vad_sound: vad-sound {
+		status = "disabled";
+		compatible = "rockchip,multicodecs-card";
+		rockchip,card-name = "rockchip,rk3568-vad";
+		rockchip,cpu = <&i2s1_8ch>;
+		rockchip,codec = <&rk809_codec>, <&vad>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_usb: vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_usb>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+	};
+
+	vcc5v0_otg: vcc5v0-otg-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_usb>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg_en>;
+	};
+
+	vcc3v3_lcd0_n: vcc3v3-lcd0-n {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lcd0_n";
+		regulator-boot-on;
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vcc3v3_lcd1_n: vcc3v3-lcd1-n {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lcd1_n";
+		regulator-boot-on;
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		post-power-on-delay-ms = <200>;
+		reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+	};
+
+	wireless_wlan: wireless-wlan {
+		compatible = "wlan-platdata";
+		rockchip,grf = <&grf>;
+		wifi_chip_type = "ap6398s";
+		status = "okay";
+	};
+
+	wireless_bluetooth: wireless-bluetooth {
+		compatible = "bluetooth-platdata";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		//wifi-bt-power-toggle;
+		uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default", "rts_gpio";
+		pinctrl-0 = <&uart8m0_rtsn>;
+		pinctrl-1 = <&uart8_gpios>;
+		BT,reset_gpio    = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
+		BT,wake_gpio     = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
+		BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	test-power {
+		status = "okay";
+	};
+};
+
+&bus_npu {
+	bus-supply = <&vdd_logic>;
+	pvtm-supply = <&vdd_cpu>;
+	status = "okay";
+};
+
+&can0 {
+	assigned-clocks = <&cru CLK_CAN0>;
+	assigned-clock-rates = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&can0m1_pins>;
+	status = "disabled";
+};
+
+&can1 {
+	assigned-clocks = <&cru CLK_CAN1>;
+	assigned-clock-rates = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&can1m1_pins>;
+	status = "disabled";
+};
+
+&can2 {
+	assigned-clocks = <&cru CLK_CAN2>;
+	assigned-clock-rates = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&can2m1_pins>;
+	status = "disabled";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&dfi {
+	status = "okay";
+};
+
+&dmc {
+	center-supply = <&vdd_logic>;
+	status = "okay";
+};
+
+&dsi0 {
+	status = "disabled";
+	//rockchip,lane-rate = <1000>;
+	dsi0_panel: panel@0 {
+		status = "okay";
+		compatible = "simple-panel-dsi";
+		reg = <0>;
+		backlight = <&backlight>;
+		reset-delay-ms = <60>;
+		enable-delay-ms = <60>;
+		prepare-delay-ms = <60>;
+		unprepare-delay-ms = <60>;
+		disable-delay-ms = <60>;
+		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+			MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
+		dsi,format = <MIPI_DSI_FMT_RGB888>;
+		dsi,lanes  = <4>;
+		panel-init-sequence = [
+			23 00 02 FE 21
+			23 00 02 04 00
+			23 00 02 00 64
+			23 00 02 2A 00
+			23 00 02 26 64
+			23 00 02 54 00
+			23 00 02 50 64
+			23 00 02 7B 00
+			23 00 02 77 64
+			23 00 02 A2 00
+			23 00 02 9D 64
+			23 00 02 C9 00
+			23 00 02 C5 64
+			23 00 02 01 71
+			23 00 02 27 71
+			23 00 02 51 71
+			23 00 02 78 71
+			23 00 02 9E 71
+			23 00 02 C6 71
+			23 00 02 02 89
+			23 00 02 28 89
+			23 00 02 52 89
+			23 00 02 79 89
+			23 00 02 9F 89
+			23 00 02 C7 89
+			23 00 02 03 9E
+			23 00 02 29 9E
+			23 00 02 53 9E
+			23 00 02 7A 9E
+			23 00 02 A0 9E
+			23 00 02 C8 9E
+			23 00 02 09 00
+			23 00 02 05 B0
+			23 00 02 31 00
+			23 00 02 2B B0
+			23 00 02 5A 00
+			23 00 02 55 B0
+			23 00 02 80 00
+			23 00 02 7C B0
+			23 00 02 A7 00
+			23 00 02 A3 B0
+			23 00 02 CE 00
+			23 00 02 CA B0
+			23 00 02 06 C0
+			23 00 02 2D C0
+			23 00 02 56 C0
+			23 00 02 7D C0
+			23 00 02 A4 C0
+			23 00 02 CB C0
+			23 00 02 07 CF
+			23 00 02 2F CF
+			23 00 02 58 CF
+			23 00 02 7E CF
+			23 00 02 A5 CF
+			23 00 02 CC CF
+			23 00 02 08 DD
+			23 00 02 30 DD
+			23 00 02 59 DD
+			23 00 02 7F DD
+			23 00 02 A6 DD
+			23 00 02 CD DD
+			23 00 02 0E 15
+			23 00 02 0A E9
+			23 00 02 36 15
+			23 00 02 32 E9
+			23 00 02 5F 15
+			23 00 02 5B E9
+			23 00 02 85 15
+			23 00 02 81 E9
+			23 00 02 AD 15
+			23 00 02 A9 E9
+			23 00 02 D3 15
+			23 00 02 CF E9
+			23 00 02 0B 14
+			23 00 02 33 14
+			23 00 02 5C 14
+			23 00 02 82 14
+			23 00 02 AA 14
+			23 00 02 D0 14
+			23 00 02 0C 36
+			23 00 02 34 36
+			23 00 02 5D 36
+			23 00 02 83 36
+			23 00 02 AB 36
+			23 00 02 D1 36
+			23 00 02 0D 6B
+			23 00 02 35 6B
+			23 00 02 5E 6B
+			23 00 02 84 6B
+			23 00 02 AC 6B
+			23 00 02 D2 6B
+			23 00 02 13 5A
+			23 00 02 0F 94
+			23 00 02 3B 5A
+			23 00 02 37 94
+			23 00 02 64 5A
+			23 00 02 60 94
+			23 00 02 8A 5A
+			23 00 02 86 94
+			23 00 02 B2 5A
+			23 00 02 AE 94
+			23 00 02 D8 5A
+			23 00 02 D4 94
+			23 00 02 10 D1
+			23 00 02 38 D1
+			23 00 02 61 D1
+			23 00 02 87 D1
+			23 00 02 AF D1
+			23 00 02 D5 D1
+			23 00 02 11 04
+			23 00 02 39 04
+			23 00 02 62 04
+			23 00 02 88 04
+			23 00 02 B0 04
+			23 00 02 D6 04
+			23 00 02 12 05
+			23 00 02 3A 05
+			23 00 02 63 05
+			23 00 02 89 05
+			23 00 02 B1 05
+			23 00 02 D7 05
+			23 00 02 18 AA
+			23 00 02 14 36
+			23 00 02 42 AA
+			23 00 02 3D 36
+			23 00 02 69 AA
+			23 00 02 65 36
+			23 00 02 8F AA
+			23 00 02 8B 36
+			23 00 02 B7 AA
+			23 00 02 B3 36
+			23 00 02 DD AA
+			23 00 02 D9 36
+			23 00 02 15 74
+			23 00 02 3F 74
+			23 00 02 66 74
+			23 00 02 8C 74
+			23 00 02 B4 74
+			23 00 02 DA 74
+			23 00 02 16 9F
+			23 00 02 40 9F
+			23 00 02 67 9F
+			23 00 02 8D 9F
+			23 00 02 B5 9F
+			23 00 02 DB 9F
+			23 00 02 17 DC
+			23 00 02 41 DC
+			23 00 02 68 DC
+			23 00 02 8E DC
+			23 00 02 B6 DC
+			23 00 02 DC DC
+			23 00 02 1D FF
+			23 00 02 19 03
+			23 00 02 47 FF
+			23 00 02 43 03
+			23 00 02 6E FF
+			23 00 02 6A 03
+			23 00 02 94 FF
+			23 00 02 90 03
+			23 00 02 BC FF
+			23 00 02 B8 03
+			23 00 02 E2 FF
+			23 00 02 DE 03
+			23 00 02 1A 35
+			23 00 02 44 35
+			23 00 02 6B 35
+			23 00 02 91 35
+			23 00 02 B9 35
+			23 00 02 DF 35
+			23 00 02 1B 45
+			23 00 02 45 45
+			23 00 02 6C 45
+			23 00 02 92 45
+			23 00 02 BA 45
+			23 00 02 E0 45
+			23 00 02 1C 55
+			23 00 02 46 55
+			23 00 02 6D 55
+			23 00 02 93 55
+			23 00 02 BB 55
+			23 00 02 E1 55
+			23 00 02 22 FF
+			23 00 02 1E 68
+			23 00 02 4C FF
+			23 00 02 48 68
+			23 00 02 73 FF
+			23 00 02 6F 68
+			23 00 02 99 FF
+			23 00 02 95 68
+			23 00 02 C1 FF
+			23 00 02 BD 68
+			23 00 02 E7 FF
+			23 00 02 E3 68
+			23 00 02 1F 7E
+			23 00 02 49 7E
+			23 00 02 70 7E
+			23 00 02 96 7E
+			23 00 02 BE 7E
+			23 00 02 E4 7E
+			23 00 02 20 97
+			23 00 02 4A 97
+			23 00 02 71 97
+			23 00 02 97 97
+			23 00 02 BF 97
+			23 00 02 E5 97
+			23 00 02 21 B5
+			23 00 02 4B B5
+			23 00 02 72 B5
+			23 00 02 98 B5
+			23 00 02 C0 B5
+			23 00 02 E6 B5
+			23 00 02 25 F0
+			23 00 02 23 E8
+			23 00 02 4F F0
+			23 00 02 4D E8
+			23 00 02 76 F0
+			23 00 02 74 E8
+			23 00 02 9C F0
+			23 00 02 9A E8
+			23 00 02 C4 F0
+			23 00 02 C2 E8
+			23 00 02 EA F0
+			23 00 02 E8 E8
+			23 00 02 24 FF
+			23 00 02 4E FF
+			23 00 02 75 FF
+			23 00 02 9B FF
+			23 00 02 C3 FF
+			23 00 02 E9 FF
+			23 00 02 FE 3D
+			23 00 02 00 04
+			23 00 02 FE 23
+			23 00 02 08 82
+			23 00 02 0A 00
+			23 00 02 0B 00
+			23 00 02 0C 01
+			23 00 02 16 00
+			23 00 02 18 02
+			23 00 02 1B 04
+			23 00 02 19 04
+			23 00 02 1C 81
+			23 00 02 1F 00
+			23 00 02 20 03
+			23 00 02 23 04
+			23 00 02 21 01
+			23 00 02 54 63
+			23 00 02 55 54
+			23 00 02 6E 45
+			23 00 02 6D 36
+			23 00 02 FE 3D
+			23 00 02 55 78
+			23 00 02 FE 20
+			23 00 02 26 30
+			23 00 02 FE 3D
+			23 00 02 20 71
+			23 00 02 50 8F
+			23 00 02 51 8F
+			23 00 02 FE 00
+			23 00 02 35 00
+			05 78 01 11
+			05 1E 01 29
+		];
+
+		panel-exit-sequence = [
+			05 00 01 28
+			05 00 01 10
+		];
+
+		disp_timings0: display-timings {
+			native-mode = <&dsi0_timing0>;
+			dsi0_timing0: timing0 {
+				clock-frequency = <132000000>;
+				hactive = <1080>;
+				vactive = <1920>;
+				hfront-porch = <15>;
+				hsync-len = <2>;
+				hback-porch = <30>;
+				vfront-porch = <15>;
+				vsync-len = <2>;
+				vback-porch = <15>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <0>;
+				pixelclk-active = <1>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				panel_in_dsi: endpoint {
+					remote-endpoint = <&dsi_out_panel>;
+				};
+			};
+		};
+	};
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@1 {
+			reg = <1>;
+			dsi_out_panel: endpoint {
+				remote-endpoint = <&panel_in_dsi>;
+			};
+		};
+	};
+
+};
+
+&dsi1 {
+	status = "disabled";
+	//rockchip,lane-rate = <1000>;
+	dsi1_panel: panel@0 {
+		status = "okay";
+		compatible = "simple-panel-dsi";
+		reg = <0>;
+		backlight = <&backlight1>;
+		reset-delay-ms = <60>;
+		enable-delay-ms = <60>;
+		prepare-delay-ms = <60>;
+		unprepare-delay-ms = <60>;
+		disable-delay-ms = <60>;
+		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+			MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
+		dsi,format = <MIPI_DSI_FMT_RGB888>;
+		dsi,lanes  = <4>;
+		panel-init-sequence = [
+			23 00 02 FE 21
+			23 00 02 04 00
+			23 00 02 00 64
+			23 00 02 2A 00
+			23 00 02 26 64
+			23 00 02 54 00
+			23 00 02 50 64
+			23 00 02 7B 00
+			23 00 02 77 64
+			23 00 02 A2 00
+			23 00 02 9D 64
+			23 00 02 C9 00
+			23 00 02 C5 64
+			23 00 02 01 71
+			23 00 02 27 71
+			23 00 02 51 71
+			23 00 02 78 71
+			23 00 02 9E 71
+			23 00 02 C6 71
+			23 00 02 02 89
+			23 00 02 28 89
+			23 00 02 52 89
+			23 00 02 79 89
+			23 00 02 9F 89
+			23 00 02 C7 89
+			23 00 02 03 9E
+			23 00 02 29 9E
+			23 00 02 53 9E
+			23 00 02 7A 9E
+			23 00 02 A0 9E
+			23 00 02 C8 9E
+			23 00 02 09 00
+			23 00 02 05 B0
+			23 00 02 31 00
+			23 00 02 2B B0
+			23 00 02 5A 00
+			23 00 02 55 B0
+			23 00 02 80 00
+			23 00 02 7C B0
+			23 00 02 A7 00
+			23 00 02 A3 B0
+			23 00 02 CE 00
+			23 00 02 CA B0
+			23 00 02 06 C0
+			23 00 02 2D C0
+			23 00 02 56 C0
+			23 00 02 7D C0
+			23 00 02 A4 C0
+			23 00 02 CB C0
+			23 00 02 07 CF
+			23 00 02 2F CF
+			23 00 02 58 CF
+			23 00 02 7E CF
+			23 00 02 A5 CF
+			23 00 02 CC CF
+			23 00 02 08 DD
+			23 00 02 30 DD
+			23 00 02 59 DD
+			23 00 02 7F DD
+			23 00 02 A6 DD
+			23 00 02 CD DD
+			23 00 02 0E 15
+			23 00 02 0A E9
+			23 00 02 36 15
+			23 00 02 32 E9
+			23 00 02 5F 15
+			23 00 02 5B E9
+			23 00 02 85 15
+			23 00 02 81 E9
+			23 00 02 AD 15
+			23 00 02 A9 E9
+			23 00 02 D3 15
+			23 00 02 CF E9
+			23 00 02 0B 14
+			23 00 02 33 14
+			23 00 02 5C 14
+			23 00 02 82 14
+			23 00 02 AA 14
+			23 00 02 D0 14
+			23 00 02 0C 36
+			23 00 02 34 36
+			23 00 02 5D 36
+			23 00 02 83 36
+			23 00 02 AB 36
+			23 00 02 D1 36
+			23 00 02 0D 6B
+			23 00 02 35 6B
+			23 00 02 5E 6B
+			23 00 02 84 6B
+			23 00 02 AC 6B
+			23 00 02 D2 6B
+			23 00 02 13 5A
+			23 00 02 0F 94
+			23 00 02 3B 5A
+			23 00 02 37 94
+			23 00 02 64 5A
+			23 00 02 60 94
+			23 00 02 8A 5A
+			23 00 02 86 94
+			23 00 02 B2 5A
+			23 00 02 AE 94
+			23 00 02 D8 5A
+			23 00 02 D4 94
+			23 00 02 10 D1
+			23 00 02 38 D1
+			23 00 02 61 D1
+			23 00 02 87 D1
+			23 00 02 AF D1
+			23 00 02 D5 D1
+			23 00 02 11 04
+			23 00 02 39 04
+			23 00 02 62 04
+			23 00 02 88 04
+			23 00 02 B0 04
+			23 00 02 D6 04
+			23 00 02 12 05
+			23 00 02 3A 05
+			23 00 02 63 05
+			23 00 02 89 05
+			23 00 02 B1 05
+			23 00 02 D7 05
+			23 00 02 18 AA
+			23 00 02 14 36
+			23 00 02 42 AA
+			23 00 02 3D 36
+			23 00 02 69 AA
+			23 00 02 65 36
+			23 00 02 8F AA
+			23 00 02 8B 36
+			23 00 02 B7 AA
+			23 00 02 B3 36
+			23 00 02 DD AA
+			23 00 02 D9 36
+			23 00 02 15 74
+			23 00 02 3F 74
+			23 00 02 66 74
+			23 00 02 8C 74
+			23 00 02 B4 74
+			23 00 02 DA 74
+			23 00 02 16 9F
+			23 00 02 40 9F
+			23 00 02 67 9F
+			23 00 02 8D 9F
+			23 00 02 B5 9F
+			23 00 02 DB 9F
+			23 00 02 17 DC
+			23 00 02 41 DC
+			23 00 02 68 DC
+			23 00 02 8E DC
+			23 00 02 B6 DC
+			23 00 02 DC DC
+			23 00 02 1D FF
+			23 00 02 19 03
+			23 00 02 47 FF
+			23 00 02 43 03
+			23 00 02 6E FF
+			23 00 02 6A 03
+			23 00 02 94 FF
+			23 00 02 90 03
+			23 00 02 BC FF
+			23 00 02 B8 03
+			23 00 02 E2 FF
+			23 00 02 DE 03
+			23 00 02 1A 35
+			23 00 02 44 35
+			23 00 02 6B 35
+			23 00 02 91 35
+			23 00 02 B9 35
+			23 00 02 DF 35
+			23 00 02 1B 45
+			23 00 02 45 45
+			23 00 02 6C 45
+			23 00 02 92 45
+			23 00 02 BA 45
+			23 00 02 E0 45
+			23 00 02 1C 55
+			23 00 02 46 55
+			23 00 02 6D 55
+			23 00 02 93 55
+			23 00 02 BB 55
+			23 00 02 E1 55
+			23 00 02 22 FF
+			23 00 02 1E 68
+			23 00 02 4C FF
+			23 00 02 48 68
+			23 00 02 73 FF
+			23 00 02 6F 68
+			23 00 02 99 FF
+			23 00 02 95 68
+			23 00 02 C1 FF
+			23 00 02 BD 68
+			23 00 02 E7 FF
+			23 00 02 E3 68
+			23 00 02 1F 7E
+			23 00 02 49 7E
+			23 00 02 70 7E
+			23 00 02 96 7E
+			23 00 02 BE 7E
+			23 00 02 E4 7E
+			23 00 02 20 97
+			23 00 02 4A 97
+			23 00 02 71 97
+			23 00 02 97 97
+			23 00 02 BF 97
+			23 00 02 E5 97
+			23 00 02 21 B5
+			23 00 02 4B B5
+			23 00 02 72 B5
+			23 00 02 98 B5
+			23 00 02 C0 B5
+			23 00 02 E6 B5
+			23 00 02 25 F0
+			23 00 02 23 E8
+			23 00 02 4F F0
+			23 00 02 4D E8
+			23 00 02 76 F0
+			23 00 02 74 E8
+			23 00 02 9C F0
+			23 00 02 9A E8
+			23 00 02 C4 F0
+			23 00 02 C2 E8
+			23 00 02 EA F0
+			23 00 02 E8 E8
+			23 00 02 24 FF
+			23 00 02 4E FF
+			23 00 02 75 FF
+			23 00 02 9B FF
+			23 00 02 C3 FF
+			23 00 02 E9 FF
+			23 00 02 FE 3D
+			23 00 02 00 04
+			23 00 02 FE 23
+			23 00 02 08 82
+			23 00 02 0A 00
+			23 00 02 0B 00
+			23 00 02 0C 01
+			23 00 02 16 00
+			23 00 02 18 02
+			23 00 02 1B 04
+			23 00 02 19 04
+			23 00 02 1C 81
+			23 00 02 1F 00
+			23 00 02 20 03
+			23 00 02 23 04
+			23 00 02 21 01
+			23 00 02 54 63
+			23 00 02 55 54
+			23 00 02 6E 45
+			23 00 02 6D 36
+			23 00 02 FE 3D
+			23 00 02 55 78
+			23 00 02 FE 20
+			23 00 02 26 30
+			23 00 02 FE 3D
+			23 00 02 20 71
+			23 00 02 50 8F
+			23 00 02 51 8F
+			23 00 02 FE 00
+			23 00 02 35 00
+			05 78 01 11
+			05 1E 01 29
+		];
+
+		panel-exit-sequence = [
+			05 00 01 28
+			05 00 01 10
+		];
+
+		disp_timings1: display-timings {
+			native-mode = <&dsi1_timing0>;
+			dsi1_timing0: timing0 {
+				clock-frequency = <132000000>;
+				hactive = <1080>;
+				vactive = <1920>;
+				hfront-porch = <15>;
+				hsync-len = <2>;
+				hback-porch = <30>;
+				vfront-porch = <15>;
+				vsync-len = <2>;
+				vback-porch = <15>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <0>;
+				pixelclk-active = <1>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				panel_in_dsi1: endpoint {
+					remote-endpoint = <&dsi1_out_panel>;
+				};
+			};
+		};
+	};
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@1 {
+			reg = <1>;
+			dsi1_out_panel: endpoint {
+				remote-endpoint = <&panel_in_dsi1>;
+			};
+		};
+	};
+
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	status = "okay";
+	rockchip,phy-table =
+		<92812500  0x8009 0x0000 0x0270>,
+		<165000000 0x800b 0x0000 0x026d>,
+		<185625000 0x800b 0x0000 0x01ed>,
+		<297000000 0x800b 0x0000 0x01ad>,
+		<594000000 0x8029 0x0000 0x0088>,
+		<000000000 0x0000 0x0000 0x0000>;
+};
+
+&hdmi_in_vp0 {
+	status = "okay";
+};
+
+&hdmi_in_vp1 {
+	status = "disabled";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: tcs4525@1c {
+		compatible = "tcs,tcs452x";
+		reg = <0x1c>;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-compatible = "fan53555-reg";
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1390000>;
+		regulator-init-microvolt = <900000>;
+		regulator-initial-mode = <1>;
+		regulator-ramp-delay = <2300>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-names = "default", "pmic-sleep",
+				"pmic-power-off", "pmic-reset";
+		pinctrl-0 = <&pmic_int>;
+		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
+		pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
+		pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
+
+		rockchip,system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+		//fb-inner-reg-idxs = <2>;
+		/* 1: rst regs (default in codes), 0: rst the pmic */
+		pmic-reset-func = <0>;
+		/* not save the PMIC_POWER_EN register in uboot */
+		not-save-power-en = <1>;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		pwrkey {
+			status = "okay";
+		};
+
+		pinctrl_rk8xx: pinctrl_rk8xx {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			rk817_slppin_null: rk817_slppin_null {
+				pins = "gpio_slp";
+				function = "pin_fun0";
+			};
+
+			rk817_slppin_slp: rk817_slppin_slp {
+				pins = "gpio_slp";
+				function = "pin_fun1";
+			};
+
+			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
+				pins = "gpio_slp";
+				function = "pin_fun2";
+			};
+
+			rk817_slppin_rst: rk817_slppin_rst {
+				pins = "gpio_slp";
+				function = "pin_fun3";
+			};
+		};
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_logic";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_gpu";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_ddr";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_npu";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vccio_acodec";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_image";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_3v3";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+
+		rk809_codec: codec {
+			#sound-dai-cells = <1>;
+			compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
+			clocks = <&cru I2S1_MCLKOUT>;
+			clock-names = "mclk";
+			assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>;
+			assigned-clock-rates = <12288000>;
+			assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2s1m0_mclk>;
+			hp-volume = <20>;
+			spk-volume = <3>;
+			mic-in-differential;
+			status = "okay";
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+
+	gt1x: gt1x@14 {
+		compatible = "goodix,gt1x";
+		reg = <0x14>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touch_gpio>;
+		goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+		goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&i2c5 {
+	status = "okay";
+
+	mxc6655xa: mxc6655xa@15 {
+		status = "okay";
+		compatible = "gs_mxc6655xa";
+		pinctrl-names = "default";
+		pinctrl-0 = <&mxc6655xa_irq_gpio>;
+		reg = <0x15>;
+		irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>;
+		irq_enable = <0>;
+		poll_delay_ms = <30>;
+		type = <SENSOR_TYPE_ACCEL>;
+		power-off-in-suspend = <1>;
+		layout = <1>;
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	status = "okay";
+	rockchip,clk-trcm = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m0_sclktx
+		     &i2s1m0_lrcktx
+		     &i2s1m0_sdi0
+		     &i2s1m0_sdo0>;
+};
+
+&iep {
+	status = "okay";
+};
+
+&iep_mmu {
+	status = "okay";
+};
+
+&jpegd {
+	status = "okay";
+};
+
+&jpegd_mmu {
+	status = "okay";
+};
+
+&mpp_srv {
+	status = "okay";
+};
+
+&nandc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+		nand-bus-width = <8>;
+		nand-ecc-mode = "hw";
+		nand-ecc-strength = <16>;
+		nand-ecc-step-size = <1024>;
+	};
+};
+
+&pinctrl {
+
+	headphone {
+		hp_det: hp-det {
+			rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	mxc6655xa {
+		mxc6655xa_irq_gpio: mxc6655xa_irq_gpio {
+			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		soc_slppin_gpio: soc_slppin_gpio {
+			rockchip,pins =
+				<0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>;
+		};
+
+		soc_slppin_slp: soc_slppin_slp {
+			rockchip,pins =
+				<0 RK_PA2 1 &pcfg_pull_none>;
+		};
+
+		soc_slppin_rst: soc_slppin_rst {
+			rockchip,pins =
+				<0 RK_PA2 2 &pcfg_pull_none>;
+		};
+	};
+
+	touch {
+		touch_gpio: touch-gpio {
+			rockchip,pins =
+				<0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
+				<0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_otg_en: vcc5v0-otg-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wireless-bluetooth {
+		uart8_gpios: uart8-gpios {
+			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+ /*
+  * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7].
+  * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured;
+  * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages
+  *    must be consistent with the software configuration correspondingly
+  *	a/ When the hardware IO level is connected to 1.8V, the software voltage configuration
+  *	   should also be configured to 1.8V accordingly;
+  *	b/ When the hardware IO level is connected to 3.3V, the software voltage configuration
+  *	   should also be configured to 3.3V accordingly;
+  * 3/ VCCIO2 voltage control selection (0xFDC20140)
+  *	BIT[0]: 0x0: from GPIO_0A7 (default)
+  *	BIT[0]: 0x1: from GRF
+  *    Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7:
+  *	L:VCCIO2 must supply 3.3V
+  *	H:VCCIO2 must supply 1.8V
+  */
+&pmu_io_domains {
+	status = "okay";
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_3v3>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+};
+
+&pwm4 {
+	status = "okay";
+};
+
+&pwm5 {
+	status = "okay";
+};
+
+&pwm7 {
+	status = "okay";
+
+	compatible = "rockchip,remotectl-pwm";
+	remote_pwm_id = <3>;
+	handle_cpu_id = <1>;
+	remote_support_psci = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm7_pins>;
+
+	ir_key1 {
+		rockchip,usercode = <0x4040>;
+		rockchip,key_table =
+			<0xf2	KEY_REPLY>,
+			<0xba	KEY_BACK>,
+			<0xf4	KEY_UP>,
+			<0xf1	KEY_DOWN>,
+			<0xef	KEY_LEFT>,
+			<0xee	KEY_RIGHT>,
+			<0xbd	KEY_HOME>,
+			<0xea	KEY_VOLUMEUP>,
+			<0xe3	KEY_VOLUMEDOWN>,
+			<0xe2	KEY_SEARCH>,
+			<0xb2	KEY_POWER>,
+			<0xbc	KEY_MUTE>,
+			<0xec	KEY_MENU>,
+			<0xbf	0x190>,
+			<0xe0	0x191>,
+			<0xe1	0x192>,
+			<0xe9	183>,
+			<0xe6	248>,
+			<0xe8	185>,
+			<0xe7	186>,
+			<0xf0	388>,
+			<0xbe	0x175>;
+	};
+
+	ir_key2 {
+		rockchip,usercode = <0xff00>;
+		rockchip,key_table =
+			<0xf9	KEY_HOME>,
+			<0xbf	KEY_BACK>,
+			<0xfb	KEY_MENU>,
+			<0xaa	KEY_REPLY>,
+			<0xb9	KEY_UP>,
+			<0xe9	KEY_DOWN>,
+			<0xb8	KEY_LEFT>,
+			<0xea	KEY_RIGHT>,
+			<0xeb	KEY_VOLUMEDOWN>,
+			<0xef	KEY_VOLUMEUP>,
+			<0xf7	KEY_MUTE>,
+			<0xe7	KEY_POWER>,
+			<0xfc	KEY_POWER>,
+			<0xa9	KEY_VOLUMEDOWN>,
+			<0xa8	KEY_VOLUMEDOWN>,
+			<0xe0	KEY_VOLUMEDOWN>,
+			<0xa5	KEY_VOLUMEDOWN>,
+			<0xab	183>,
+			<0xb7	388>,
+			<0xe8	388>,
+			<0xf8	184>,
+			<0xaf	185>,
+			<0xed	KEY_VOLUMEDOWN>,
+			<0xee	186>,
+			<0xb3	KEY_VOLUMEDOWN>,
+			<0xf1	KEY_VOLUMEDOWN>,
+			<0xf2	KEY_VOLUMEDOWN>,
+			<0xf3	KEY_SEARCH>,
+			<0xb4	KEY_VOLUMEDOWN>,
+			<0xbe	KEY_SEARCH>;
+	};
+
+	ir_key3 {
+		rockchip,usercode = <0x1dcc>;
+		rockchip,key_table =
+			<0xee	KEY_REPLY>,
+			<0xf0	KEY_BACK>,
+			<0xf8	KEY_UP>,
+			<0xbb	KEY_DOWN>,
+			<0xef	KEY_LEFT>,
+			<0xed	KEY_RIGHT>,
+			<0xfc	KEY_HOME>,
+			<0xf1	KEY_VOLUMEUP>,
+			<0xfd	KEY_VOLUMEDOWN>,
+			<0xb7	KEY_SEARCH>,
+			<0xff	KEY_POWER>,
+			<0xf3	KEY_MUTE>,
+			<0xbf	KEY_MENU>,
+			<0xf9	0x191>,
+			<0xf5	0x192>,
+			<0xb3	388>,
+			<0xbe	KEY_1>,
+			<0xba	KEY_2>,
+			<0xb2	KEY_3>,
+			<0xbd	KEY_4>,
+			<0xf9	KEY_5>,
+			<0xb1	KEY_6>,
+			<0xfc	KEY_7>,
+			<0xf8	KEY_8>,
+			<0xb0	KEY_9>,
+			<0xb6	KEY_0>,
+			<0xb5	KEY_BACKSPACE>;
+	};
+};
+
+&rk_rga {
+	status = "okay";
+};
+
+&rkvdec {
+	status = "okay";
+};
+
+&rkvdec_mmu {
+	status = "okay";
+};
+
+&rkvenc {
+	venc-supply = <&vdd_logic>;
+	status = "okay";
+};
+
+&rkvenc_mmu {
+	status = "okay";
+};
+
+&rknpu {
+	rknpu-supply = <&vdd_npu>;
+	status = "okay";
+};
+
+&rknpu_mmu {
+	status = "okay";
+};
+
+&route_hdmi {
+	status = "okay";
+	connect = <&vp0_out_hdmi>;
+};
+
+&saradc {
+	status = "okay";
+	vref-supply = <&vcca_1v8>;
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	max-frequency = <200000000>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	max-frequency = <150000000>;
+	no-sdio;
+	no-mmc;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	status = "okay";
+};
+
+&sfc {
+	status = "okay";
+
+	flash@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <75000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&spdif_8ch {
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&u2phy0_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy0_otg {
+	vbus-supply = <&vcc5v0_otg>;
+	status = "okay";
+};
+
+&u2phy1_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd_dwc3 {
+	dr_mode = "otg";
+	extcon = <&usb2phy0>;
+	status = "okay";
+};
+
+&usbdrd30 {
+	status = "okay";
+};
+
+&usbhost_dwc3 {
+	status = "okay";
+};
+
+&usbhost30 {
+	status = "okay";
+};
+
+&vad {
+	rockchip,audio-src = <&i2s1_8ch>;
+	rockchip,buffer-time-ms = <128>;
+	rockchip,det-channel = <0>;
+	rockchip,mode = <0>;
+};
+
+&vdpu {
+	status = "okay";
+};
+
+&vdpu_mmu {
+	status = "okay";
+};
+
+&vepu {
+	status = "okay";
+};
+
+&vepu_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+};
+
+&vop_mmu {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..7ef900001f51f3c77c29b092dddcc8a7e67c7cd8
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dtsi
@@ -0,0 +1,492 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568.dtsi"
+#include "rk3568-evb.dtsi"
+
+/ {
+	model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
+	compatible = "rockchip,rk3568-evb1-ddr4-v10", "rockchip,rk3568";
+
+	vcc2v5_sys: vcc2v5-ddr {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc2v5-sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_vga: vcc3v3-vga {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_vga";
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	pcie30_avdd0v9: pcie30-avdd0v9 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	pcie30_avdd1v8: pcie30-avdd1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_pcie: gpio-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <5000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc3v3_bu: vcc3v3-bu {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_bu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_camera: vcc-camera-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&camera_pwr>;
+		regulator-name = "vcc_camera";
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&combphy0_us {
+	status = "okay";
+};
+
+&combphy1_usq {
+	status = "okay";
+};
+
+&combphy2_psq {
+	status = "okay";
+};
+
+&csi2_dphy_hw {
+	status = "okay";
+};
+
+&csi2_dphy0 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi_in_ucam0: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&ucam_out0>;
+				data-lanes = <1 2 3 4>;
+			};
+			mipi_in_ucam1: endpoint@2 {
+				reg = <2>;
+				remote-endpoint = <&gc8034_out>;
+				data-lanes = <1 2 3 4>;
+			};
+			mipi_in_ucam2: endpoint@3 {
+				reg = <3>;
+				remote-endpoint = <&ov5695_out>;
+				data-lanes = <1 2>;
+			};
+		};
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csidphy_out: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&isp0_in>;
+			};
+		};
+	};
+};
+
+/*
+ * video_phy0 needs to be enabled
+ * when dsi0 is enabled
+ */
+&dsi0 {
+	status = "okay";
+};
+
+&dsi0_in_vp0 {
+	status = "disabled";
+};
+
+&dsi0_in_vp1 {
+	status = "okay";
+};
+
+&dsi0_panel {
+	power-supply = <&vcc3v3_lcd0_n>;
+};
+
+/*
+ * video_phy1 needs to be enabled
+ * when dsi1 is enabled
+ */
+&dsi1 {
+	status = "disabled";
+};
+
+&dsi1_in_vp0 {
+	status = "disabled";
+};
+
+&dsi1_in_vp1 {
+	status = "disabled";
+};
+
+&dsi1_panel {
+	power-supply = <&vcc3v3_lcd1_n>;
+};
+
+&edp {
+	hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&edp_phy {
+	status = "okay";
+};
+
+&edp_in_vp0 {
+	status = "okay";
+};
+
+&edp_in_vp1 {
+	status = "disabled";
+};
+
+&gmac0 {
+	phy-mode = "rgmii";
+	clock_in_out = "output";
+
+	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+	assigned-clock-rates = <0>, <125000000>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+
+	tx_delay = <0x3c>;
+	rx_delay = <0x2f>;
+
+	phy-handle = <&rgmii_phy0>;
+	status = "okay";
+};
+
+&gmac1 {
+	phy-mode = "rgmii";
+	clock_in_out = "output";
+
+	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+	assigned-clock-rates = <0>, <125000000>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus>;
+
+	tx_delay = <0x4f>;
+	rx_delay = <0x26>;
+
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+/*
+ * power-supply should switche to vcc3v3_lcd1_n
+ * when mipi panel is connected to dsi1.
+ */
+&gt1x {
+	power-supply = <&vcc3v3_lcd0_n>;
+};
+
+&i2c4 {
+	status = "okay";
+	gc8034: gc8034@37 {
+		compatible = "galaxycore,gc8034";
+		status = "okay";
+		reg = <0x37>;
+		clocks = <&cru CLK_CIF_OUT>;
+		clock-names = "xvclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&cif_clk>;
+		reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>;
+		pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>;
+		rockchip,grf = <&grf>;
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "RK-CMK-8M-2-v1";
+		rockchip,camera-module-lens-name = "CK8401";
+		port {
+			gc8034_out: endpoint {
+				remote-endpoint = <&mipi_in_ucam1>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+	os04a10: os04a10@36 {
+		compatible = "ovti,os04a10";
+		reg = <0x36>;
+		clocks = <&cru CLK_CIF_OUT>;
+		clock-names = "xvclk";
+		power-domains = <&power RK3568_PD_VI>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cif_clk>;
+		reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>;
+		pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "CMK-OT1607-FV1";
+		rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16";
+		port {
+			ucam_out0: endpoint {
+				remote-endpoint = <&mipi_in_ucam0>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+	ov5695: ov5695@36 {
+		status = "okay";
+		compatible = "ovti,ov5695";
+		reg = <0x36>;
+		clocks = <&cru CLK_CIF_OUT>;
+		clock-names = "xvclk";
+		power-domains = <&power RK3568_PD_VI>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cif_clk>;
+		reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>;
+		pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "TongJu";
+		rockchip,camera-module-lens-name = "CHT842-MD";
+		port {
+			ov5695_out: endpoint {
+				remote-endpoint = <&mipi_in_ucam2>;
+				data-lanes = <1 2>;
+			};
+		};
+	};
+};
+
+&mdio0 {
+	rgmii_phy0: phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+	};
+};
+
+&video_phy0 {
+	status = "okay";
+};
+
+&video_phy1 {
+	status = "disabled";
+};
+
+&pcie30phy {
+	status = "okay";
+};
+
+&pcie3x2 {
+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pinctrl {
+	cam {
+		camera_pwr: camera-pwr {
+			rockchip,pins =
+				/* camera power en */
+				<0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+	headphone {
+		hp_det: hp-det {
+			rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	wireless-wlan {
+		wifi_host_wake_irq: wifi-host-wake-irq {
+			rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	wireless-bluetooth {
+		uart8_gpios: uart8-gpios {
+			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&rk809_sound {
+	hp-det-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
+};
+
+&rkisp {
+	status = "okay";
+};
+
+&rkisp_mmu {
+	status = "okay";
+};
+
+&rkisp_vir0 {
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		isp0_in: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&csidphy_out>;
+		};
+	};
+};
+
+&route_dsi0 {
+	status = "okay";
+	connect = <&vp1_out_dsi0>;
+};
+
+&route_edp {
+	status = "okay";
+	connect = <&vp0_out_edp>;
+};
+
+&sata2 {
+	status = "okay";
+};
+
+&sdmmc2 {
+	max-frequency = <150000000>;
+	no-sd;
+	no-mmc;
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&spdif_8ch {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spdifm1_tx>;
+};
+
+&uart8 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>;
+};
+
+&vcc3v3_lcd0_n {
+	gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+	enable-active-high;
+};
+
+&vcc3v3_lcd1_n {
+	gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+	enable-active-high;
+};
+
+&wireless_wlan {
+	pinctrl-names = "default";
+	pinctrl-0 = <&wifi_host_wake_irq>;
+	WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+};
+
+&wireless_bluetooth {
+	compatible = "bluetooth-platdata";
+	clocks = <&rk809 1>;
+	clock-names = "ext_clock";
+	//wifi-bt-power-toggle;
+	uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default", "rts_gpio";
+	pinctrl-0 = <&uart8m0_rtsn>;
+	pinctrl-1 = <&uart8_gpios>;
+	BT,reset_gpio    = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
+	BT,wake_gpio     = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
+	BT,wake_host_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-linux.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-linux.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..c7e309645099b720d2d22865811b0095313d385b
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-linux.dtsi
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/ {
+	aliases {
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc0;
+		mmc2 = &sdmmc1;
+		mmc3 = &sdmmc2;
+	};
+
+	chosen: chosen {
+		bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait";
+	};
+
+	fiq-debugger {
+		compatible = "rockchip,fiq-debugger";
+		rockchip,serial-id = <2>;
+		rockchip,wake-irq = <0>;
+		/* If enable uart uses irq instead of fiq */
+		rockchip,irq-mode-enable = <1>;
+		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
+		interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart2m0_xfer>;
+		status = "okay";
+	};
+
+	debug: debug@fd904000 {
+		compatible = "rockchip,debug";
+		reg = <0x0 0xfd904000 0x0 0x1000>,
+			<0x0 0xfd905000 0x0 0x1000>,
+			<0x0 0xfd906000 0x0 0x1000>,
+			<0x0 0xfd907000 0x0 0x1000>;
+	};
+
+	cspmu: cspmu@fd90c000 {
+		compatible = "rockchip,cspmu";
+		reg = <0x0 0xfd90c000 0x0 0x1000>,
+			<0x0 0xfd90d000 0x0 0x1000>,
+			<0x0 0xfd90e000 0x0 0x1000>,
+			<0x0 0xfd90f000 0x0 0x1000>;
+	};
+};
+
+&reserved_memory {
+	ramoops: ramoops@110000 {
+		compatible = "ramoops";
+		reg = <0x0 0x110000 0x0 0xf0000>;
+		record-size = <0x20000>;
+		console-size = <0x80000>;
+		ftrace-size = <0x00000>;
+		pmsg-size = <0x50000>;
+	};
+};
+
+&rng {
+	status = "okay";
+};
+
+&rockchip_suspend {
+	status = "okay";
+};
+
+&vop {
+	disable-win-move;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
new file mode 100644
index 0000000000000000000000000000000000000000..65386cc44aa9925d2b1b513dc702134a21f0fa45
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
@@ -0,0 +1,11141 @@
+/dts-v1/;
+
+/ {
+	compatible = "rockchip,rk3588s-orangepi-5\0rockchip,rk3588";
+	interrupt-parent = <0x01>;
+	#address-cells = <0x02>;
+	#size-cells = <0x02>;
+	model = "Orange Pi 5";
+
+	aliases {
+		csi2dcphy0 = "/csi2-dcphy0";
+		csi2dcphy1 = "/csi2-dcphy1";
+		csi2dphy0 = "/csi2-dphy0";
+		csi2dphy1 = "/csi2-dphy1";
+		csi2dphy2 = "/csi2-dphy2";
+		dsi0 = "/dsi@fde20000";
+		dsi1 = "/dsi@fde30000";
+		ethernet1 = "/ethernet@fe1c0000";
+		gpio0 = "/pinctrl/gpio@fd8a0000";
+		gpio1 = "/pinctrl/gpio@fec20000";
+		gpio2 = "/pinctrl/gpio@fec30000";
+		gpio3 = "/pinctrl/gpio@fec40000";
+		gpio4 = "/pinctrl/gpio@fec50000";
+		i2c0 = "/i2c@fd880000";
+		i2c1 = "/i2c@fea90000";
+		i2c2 = "/i2c@feaa0000";
+		i2c3 = "/i2c@feab0000";
+		i2c4 = "/i2c@feac0000";
+		i2c5 = "/i2c@fead0000";
+		i2c6 = "/i2c@fec80000";
+		i2c7 = "/i2c@fec90000";
+		i2c8 = "/i2c@feca0000";
+		rkcif_mipi_lvds0 = "/rkcif-mipi-lvds";
+		rkcif_mipi_lvds1 = "/rkcif-mipi-lvds1";
+		rkcif_mipi_lvds2 = "/rkcif-mipi-lvds2";
+		rkcif_mipi_lvds3 = "/rkcif-mipi-lvds3";
+		rkvenc0 = "/rkvenc-core@fdbd0000";
+		rkvenc1 = "/rkvenc-core@fdbe0000";
+		jpege0 = "/jpege-core@fdba0000";
+		jpege1 = "/jpege-core@fdba4000";
+		jpege2 = "/jpege-core@fdba8000";
+		jpege3 = "/jpege-core@fdbac000";
+		serial0 = "/serial@fd890000";
+		serial1 = "/serial@feb40000";
+		serial2 = "/serial@feb50000";
+		serial3 = "/serial@feb60000";
+		serial4 = "/serial@feb70000";
+		serial5 = "/serial@feb80000";
+		serial6 = "/serial@feb90000";
+		serial7 = "/serial@feba0000";
+		serial8 = "/serial@febb0000";
+		serial9 = "/serial@febc0000";
+		spi0 = "/spi@feb00000";
+		spi1 = "/spi@feb10000";
+		spi2 = "/spi@feb20000";
+		spi3 = "/spi@feb30000";
+		spi4 = "/spi@fecb0000";
+		spi5 = "/spi@fe2b0000";
+		hdcp0 = "/hdcp@fde40000";
+		hdcp1 = "/hdcp@fde70000";
+		mmc0 = "/mmc@fe2e0000";
+		mmc1 = "/mmc@fe2c0000";
+		mmc2 = "/mmc@fe2d0000";
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+
+		spll {
+			compatible = "fixed-clock";
+			#clock-cells = <0x00>;
+			clock-frequency = <0x29d7ab80>;
+			clock-output-names = "spll";
+			phandle = <0x1b2>;
+		};
+
+		xin32k {
+			compatible = "fixed-clock";
+			#clock-cells = <0x00>;
+			clock-frequency = <0x8000>;
+			clock-output-names = "xin32k";
+			phandle = <0x1b3>;
+		};
+
+		xin24m {
+			compatible = "fixed-clock";
+			#clock-cells = <0x00>;
+			clock-frequency = <0x16e3600>;
+			clock-output-names = "xin24m";
+			phandle = <0x1b4>;
+		};
+
+		hclk_vo1@fd7c08ec {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08ec 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x264>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x05>;
+		};
+
+		aclk_vdpu_low_pre@fd7c08b0 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08b0 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1bc>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1b5>;
+		};
+
+		hclk_vo0@fd7c08dc {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08dc 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x26d>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x04>;
+		};
+
+		hclk_usb@fd7c08a8 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08a8 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x264>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1b6>;
+		};
+
+		hclk_nvm@fd7c087c {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c087c 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x141>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x03>;
+		};
+
+		aclk_usb@fd7c08a8 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08a8 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x263>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1b7>;
+		};
+
+		hclk_isp1_pre@fd7c0868 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c0868 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1e1>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1b8>;
+		};
+
+		aclk_isp1_pre@fd7c0868 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c0868 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1e0>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1b9>;
+		};
+
+		aclk_rkvdec0_pre@fd7c08a0 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08a0 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1bc>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1ba>;
+		};
+
+		hclk_rkvdec0_pre@fd7c08a0 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08a0 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1be>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1bb>;
+		};
+
+		aclk_rkvdec1_pre@fd7c08a4 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08a4 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1bc>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1bc>;
+		};
+
+		hclk_rkvdec1_pre@fd7c08a4 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08a4 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1be>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1bd>;
+		};
+
+		aclk_jpeg_decoder_pre@fd7c08b0 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08b0 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1bc>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1be>;
+		};
+
+		aclk_rkvenc1_pre@fd7c08c0 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08c0 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1c5>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1bf>;
+		};
+
+		hclk_rkvenc1_pre@fd7c08c0 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08c0 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1c4>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1c0>;
+		};
+
+		aclk_hdcp0_pre@fd7c08dc {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08dc 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x26c>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1c1>;
+		};
+
+		aclk_hdcp1_pre@fd7c08ec {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08ec 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x263>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1c2>;
+		};
+
+		pclk_av1_pre@fd7c0910 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c0910 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1be>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1c3>;
+		};
+
+		aclk_av1_pre@fd7c0910 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c0910 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1bc>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1c4>;
+		};
+
+		hclk_sdio_pre@fd7c092c {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c092c 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x03>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x1c5>;
+		};
+
+		pclk_vo0_grf@fd7c08dc {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08dc 0x00 0x04>;
+			clocks = <0x04>;
+			clock-names = "link";
+			#clock-cells = <0x00>;
+			phandle = <0x6b>;
+		};
+
+		pclk_vo1_grf@fd7c08ec {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08ec 0x00 0x04>;
+			clocks = <0x05>;
+			clock-names = "link";
+			#clock-cells = <0x00>;
+			phandle = <0x6c>;
+		};
+	};
+
+	cpus {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		cpu-map {
+
+			cluster0 {
+
+				core0 {
+					cpu = <0x06>;
+				};
+
+				core1 {
+					cpu = <0x07>;
+				};
+
+				core2 {
+					cpu = <0x08>;
+				};
+
+				core3 {
+					cpu = <0x09>;
+				};
+			};
+
+			cluster1 {
+
+				core0 {
+					cpu = <0x0a>;
+				};
+
+				core1 {
+					cpu = <0x0b>;
+				};
+			};
+
+			cluster2 {
+
+				core0 {
+					cpu = <0x0c>;
+				};
+
+				core1 {
+					cpu = <0x0d>;
+				};
+			};
+		};
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x00>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x212>;
+			clocks = <0x0e 0x00>;
+			operating-points-v2 = <0x0f>;
+			cpu-idle-states = <0x10>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x80>;
+			next-level-cache = <0x11>;
+			#cooling-cells = <0x02>;
+			dynamic-power-coefficient = <0x64>;
+			cpu-supply = <0x12>;
+			mem-supply = <0x12>;
+			phandle = <0x06>;
+		};
+
+		cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x212>;
+			clocks = <0x0e 0x00>;
+			operating-points-v2 = <0x0f>;
+			cpu-idle-states = <0x10>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x80>;
+			next-level-cache = <0x13>;
+			phandle = <0x07>;
+		};
+
+		cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x212>;
+			clocks = <0x0e 0x00>;
+			operating-points-v2 = <0x0f>;
+			cpu-idle-states = <0x10>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x80>;
+			next-level-cache = <0x14>;
+			phandle = <0x08>;
+		};
+
+		cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x212>;
+			clocks = <0x0e 0x00>;
+			operating-points-v2 = <0x0f>;
+			cpu-idle-states = <0x10>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x80>;
+			next-level-cache = <0x15>;
+			phandle = <0x09>;
+		};
+
+		cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x400>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x400>;
+			clocks = <0x0e 0x02>;
+			operating-points-v2 = <0x16>;
+			cpu-idle-states = <0x10>;
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x100>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x100>;
+			next-level-cache = <0x17>;
+			#cooling-cells = <0x02>;
+			dynamic-power-coefficient = <0x12c>;
+			cpu-supply = <0x18>;
+			mem-supply = <0x18>;
+			phandle = <0x0a>;
+		};
+
+		cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x500>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x400>;
+			clocks = <0x0e 0x02>;
+			operating-points-v2 = <0x16>;
+			cpu-idle-states = <0x10>;
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x100>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x100>;
+			next-level-cache = <0x19>;
+			phandle = <0x0b>;
+		};
+
+		cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x600>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x400>;
+			clocks = <0x0e 0x03>;
+			operating-points-v2 = <0x1a>;
+			cpu-idle-states = <0x10>;
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x100>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x100>;
+			next-level-cache = <0x1b>;
+			#cooling-cells = <0x02>;
+			dynamic-power-coefficient = <0x12c>;
+			cpu-supply = <0x1c>;
+			mem-supply = <0x1c>;
+			phandle = <0x0c>;
+		};
+
+		cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x700>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x400>;
+			clocks = <0x0e 0x03>;
+			operating-points-v2 = <0x1a>;
+			cpu-idle-states = <0x10>;
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x100>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x100>;
+			next-level-cache = <0x1d>;
+			phandle = <0x0d>;
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			cpu-sleep {
+				compatible = "arm,idle-state";
+				local-timer-stop;
+				arm,psci-suspend-param = <0x10000>;
+				entry-latency-us = <0x64>;
+				exit-latency-us = <0x78>;
+				min-residency-us = <0x3e8>;
+				phandle = <0x10>;
+			};
+		};
+
+		l2-cache-l0 {
+			compatible = "cache";
+			cache-size = <0x20000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x200>;
+			next-level-cache = <0x1e>;
+			phandle = <0x11>;
+		};
+
+		l2-cache-l1 {
+			compatible = "cache";
+			cache-size = <0x20000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x200>;
+			next-level-cache = <0x1e>;
+			phandle = <0x13>;
+		};
+
+		l2-cache-l2 {
+			compatible = "cache";
+			cache-size = <0x20000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x200>;
+			next-level-cache = <0x1e>;
+			phandle = <0x14>;
+		};
+
+		l2-cache-l3 {
+			compatible = "cache";
+			cache-size = <0x20000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x200>;
+			next-level-cache = <0x1e>;
+			phandle = <0x15>;
+		};
+
+		l2-cache-b0 {
+			compatible = "cache";
+			cache-size = <0x80000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x400>;
+			next-level-cache = <0x1e>;
+			phandle = <0x17>;
+		};
+
+		l2-cache-b1 {
+			compatible = "cache";
+			cache-size = <0x80000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x400>;
+			next-level-cache = <0x1e>;
+			phandle = <0x19>;
+		};
+
+		l2-cache-b2 {
+			compatible = "cache";
+			cache-size = <0x80000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x400>;
+			next-level-cache = <0x1e>;
+			phandle = <0x1b>;
+		};
+
+		l2-cache-b3 {
+			compatible = "cache";
+			cache-size = <0x80000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x400>;
+			next-level-cache = <0x1e>;
+			phandle = <0x1d>;
+		};
+
+		l3-cache {
+			compatible = "cache";
+			cache-size = <0x300000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x1000>;
+			phandle = <0x1e>;
+		};
+	};
+
+	cluster0-opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+		nvmem-cells = <0x1f 0x20>;
+		nvmem-cell-names = "leakage\0specification_serial_number";
+		rockchip,supported-hw;
+		rockchip,opp-shared-dsu;
+		rockchip,pvtm-voltage-sel = <0x00 0x582 0x00 0x583 0x59a 0x01 0x59b 0x5b2 0x02 0x5b3 0x5ca 0x03 0x5cb 0x5e2 0x04 0x5e3 0x5fa 0x05 0x5fb 0x270f 0x06>;
+		rockchip,pvtm-pvtpll;
+		rockchip,pvtm-offset = <0x64>;
+		rockchip,pvtm-sample-time = <0x44c>;
+		rockchip,pvtm-freq = <0x159b40>;
+		rockchip,pvtm-volt = <0xb71b0>;
+		rockchip,pvtm-ref-temp = <0x19>;
+		rockchip,pvtm-temp-prop = <0xf4 0xf4>;
+		rockchip,pvtm-thermal-zone = "soc-thermal";
+		rockchip,grf = <0x21>;
+		rockchip,reboot-freq = <0x159b40>;
+		rockchip,temp-hysteresis = <0x1388>;
+		rockchip,low-temp = <0x2710>;
+		rockchip,low-temp-min-volt = <0xb71b0>;
+		rockchip,high-temp = <0x14c08>;
+		rockchip,high-temp-max-freq = <0x188940>;
+		phandle = <0x0f>;
+
+		opp-408000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x18519600>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-600000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x23c34600>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-816000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x30a32c00>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1008000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x3c14dc00>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1200000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x47868c00>;
+			opp-microvolt = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>;
+			opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>;
+			opp-microvolt-L2 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>;
+			opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>;
+			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
+			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
+			opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1416000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x54667200>;
+			opp-microvolt = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>;
+			opp-microvolt-L1 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
+			opp-microvolt-L2 = <0xb40dc 0xb40dc 0xe7ef0 0xb40dc 0xb40dc 0xe7ef0>;
+			opp-microvolt-L3 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>;
+			opp-microvolt-L4 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>;
+			opp-microvolt-L5 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>;
+			opp-microvolt-L6 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>;
+			clock-latency-ns = <0x9c40>;
+			opp-suspend;
+		};
+
+		opp-1608000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x5fd82200>;
+			opp-microvolt = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>;
+			opp-microvolt-L1 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>;
+			opp-microvolt-L2 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>;
+			opp-microvolt-L3 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>;
+			opp-microvolt-L4 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>;
+			opp-microvolt-L5 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>;
+			opp-microvolt-L6 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1800000000 {
+			opp-supported-hw = <0xfd 0xffff>;
+			opp-hz = <0x00 0x6b49d200>;
+			opp-microvolt = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>;
+			opp-microvolt-L1 = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>;
+			opp-microvolt-L2 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>;
+			opp-microvolt-L3 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>;
+			opp-microvolt-L4 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>;
+			opp-microvolt-L5 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>;
+			opp-microvolt-L6 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>;
+			clock-latency-ns = <0x9c40>;
+		};
+	};
+
+	cluster1-opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+		nvmem-cells = <0x22 0x20>;
+		nvmem-cell-names = "leakage\0specification_serial_number";
+		rockchip,supported-hw;
+		rockchip,pvtm-voltage-sel = <0x00 0x63b 0x00 0x63c 0x64f 0x01 0x650 0x668 0x02 0x669 0x68b 0x03 0x68c 0x6ae 0x04 0x6af 0x6cf 0x05 0x6d0 0x6f0 0x06 0x6f1 0x270f 0x07>;
+		rockchip,pvtm-pvtpll;
+		rockchip,pvtm-offset = <0x18>;
+		rockchip,pvtm-sample-time = <0x44c>;
+		rockchip,pvtm-freq = <0x188940>;
+		rockchip,pvtm-volt = <0xb71b0>;
+		rockchip,pvtm-ref-temp = <0x19>;
+		rockchip,pvtm-temp-prop = <0x10e 0x10e>;
+		rockchip,pvtm-thermal-zone = "soc-thermal";
+		rockchip,pvtm-low-len-sel = <0x03>;
+		rockchip,grf = <0x23>;
+		volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>;
+		low-volt-mem-read-margin = <0x04>;
+		intermediate-threshold-freq = <0xf6180>;
+		rockchip,idle-threshold-freq = <0x21b100>;
+		rockchip,reboot-freq = <0x1b7740>;
+		rockchip,temp-hysteresis = <0x1388>;
+		rockchip,low-temp = <0x2710>;
+		rockchip,low-temp-min-volt = <0xb71b0>;
+		rockchip,high-temp = <0x14c08>;
+		rockchip,high-temp-max-freq = <0x21b100>;
+		phandle = <0x16>;
+
+		opp-408000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x18519600>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+			opp-suspend;
+		};
+
+		opp-600000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x23c34600>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-816000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x30a32c00>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1008000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x3c14dc00>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1200000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x47868c00>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1416000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x54667200>;
+			opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>;
+			opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>;
+			opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
+			opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
+			opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>;
+			opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1608000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x5fd82200>;
+			opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>;
+			opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>;
+			opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>;
+			opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>;
+			opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>;
+			opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
+			opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1800000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x6b49d200>;
+			opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>;
+			opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>;
+			opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>;
+			opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>;
+			opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>;
+			opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>;
+			opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>;
+			opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2016000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x7829b800>;
+			opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>;
+			opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>;
+			opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>;
+			opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>;
+			opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>;
+			opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>;
+			opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>;
+			opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2208000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x839b6800>;
+			opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>;
+			opp-microvolt-L1 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>;
+			opp-microvolt-L2 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>;
+			opp-microvolt-L3 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>;
+			opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>;
+			opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>;
+			opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>;
+			opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2256000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x8677d400>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2304000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x89544000>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2352000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x8c30ac00>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2400000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x8f0d1800>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+	};
+
+	cluster2-opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+		nvmem-cells = <0x24 0x20>;
+		nvmem-cell-names = "leakage\0specification_serial_number";
+		rockchip,supported-hw;
+		rockchip,pvtm-voltage-sel = <0x00 0x63b 0x00 0x63c 0x64f 0x01 0x650 0x668 0x02 0x669 0x68b 0x03 0x68c 0x6ae 0x04 0x6af 0x6cf 0x05 0x6d0 0x6f0 0x06 0x6f1 0x270f 0x07>;
+		rockchip,pvtm-pvtpll;
+		rockchip,pvtm-offset = <0x18>;
+		rockchip,pvtm-sample-time = <0x44c>;
+		rockchip,pvtm-freq = <0x188940>;
+		rockchip,pvtm-volt = <0xb71b0>;
+		rockchip,pvtm-ref-temp = <0x19>;
+		rockchip,pvtm-temp-prop = <0x10e 0x10e>;
+		rockchip,pvtm-thermal-zone = "soc-thermal";
+		rockchip,pvtm-low-len-sel = <0x03>;
+		rockchip,grf = <0x25>;
+		volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>;
+		low-volt-mem-read-margin = <0x04>;
+		intermediate-threshold-freq = <0xf6180>;
+		rockchip,idle-threshold-freq = <0x21b100>;
+		rockchip,reboot-freq = <0x1b7740>;
+		rockchip,temp-hysteresis = <0x1388>;
+		rockchip,low-temp = <0x2710>;
+		rockchip,low-temp-min-volt = <0xb71b0>;
+		rockchip,high-temp = <0x14c08>;
+		rockchip,high-temp-max-freq = <0x21b100>;
+		phandle = <0x1a>;
+
+		opp-408000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x18519600>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+			opp-suspend;
+		};
+
+		opp-600000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x23c34600>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-816000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x30a32c00>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1008000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x3c14dc00>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1200000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x47868c00>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1416000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x54667200>;
+			opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>;
+			opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>;
+			opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
+			opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
+			opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>;
+			opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1608000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x5fd82200>;
+			opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>;
+			opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>;
+			opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>;
+			opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>;
+			opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>;
+			opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
+			opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1800000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x6b49d200>;
+			opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>;
+			opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>;
+			opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>;
+			opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>;
+			opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>;
+			opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>;
+			opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>;
+			opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2016000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x7829b800>;
+			opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>;
+			opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>;
+			opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>;
+			opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>;
+			opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>;
+			opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>;
+			opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>;
+			opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2208000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x839b6800>;
+			opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>;
+			opp-microvolt-L3 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>;
+			opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>;
+			opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>;
+			opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>;
+			opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2256000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x8677d400>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2304000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x89544000>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2352000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x8c30ac00>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2400000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x8f0d1800>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+	};
+
+	arm-pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <0x01 0x07 0x08>;
+		interrupt-affinity = <0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d>;
+		phandle = <0x1c6>;
+	};
+
+	cpuinfo {
+		compatible = "rockchip,cpuinfo";
+		nvmem-cells = <0x26 0x27 0x28>;
+		nvmem-cell-names = "id\0cpu-version\0cpu-code";
+	};
+
+	csi2-dcphy0 {
+		compatible = "rockchip,rk3588-csi2-dcphy";
+		phys = <0x29>;
+		phy-names = "dcphy";
+		status = "disabled";
+		phandle = <0x1c7>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0x2a>;
+					data-lanes = <0x01 0x02>;
+					phandle = <0x17a>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0x2b>;
+					data-lanes = <0x01 0x02>;
+					phandle = <0x17c>;
+				};
+			};
+
+			port@1 {
+				reg = <0x01>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0x2c>;
+					phandle = <0xc5>;
+				};
+			};
+		};
+	};
+
+	csi2-dcphy1 {
+		compatible = "rockchip,rk3588-csi2-dcphy";
+		phys = <0x2d>;
+		phy-names = "dcphy";
+		status = "disabled";
+		phandle = <0x1c8>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0x2e>;
+					data-lanes = <0x01 0x02>;
+					phandle = <0x139>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0x2f>;
+					data-lanes = <0x01 0x02>;
+					phandle = <0x13b>;
+				};
+			};
+
+			port@1 {
+				reg = <0x01>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0x30>;
+					phandle = <0xc7>;
+				};
+			};
+		};
+	};
+
+	csi2-dphy0 {
+		compatible = "rockchip,rk3568-csi2-dphy";
+		rockchip,hw = <0x31>;
+		status = "disabled";
+		phandle = <0x1c9>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0x32>;
+					data-lanes = <0x01 0x02>;
+					phandle = <0x176>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0x33>;
+					data-lanes = <0x01 0x02>;
+					phandle = <0x178>;
+				};
+			};
+
+			port@1 {
+				reg = <0x01>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0x34>;
+					phandle = <0xc9>;
+				};
+			};
+		};
+	};
+
+	csi2-dphy1 {
+		compatible = "rockchip,rk3568-csi2-dphy";
+		rockchip,hw = <0x31>;
+		status = "disabled";
+		phandle = <0x1ca>;
+	};
+
+	csi2-dphy2 {
+		compatible = "rockchip,rk3568-csi2-dphy";
+		rockchip,hw = <0x31>;
+		status = "disabled";
+		phandle = <0x1cb>;
+	};
+
+	display-subsystem {
+		compatible = "rockchip,display-subsystem";
+		ports = <0x35>;
+		clocks = <0x36>;
+		clock-names = "hdmi0_phy_pll";
+		memory-region = <0x37>;
+		memory-region-names = "drm-logo";
+		phandle = <0x1cc>;
+
+		route {
+
+			route-dp0 {
+				status = "disabled";
+				logo,uboot = "logo.bmp";
+				logo,kernel = "logo_kernel.bmp";
+				logo,mode = "center";
+				charge_logo,mode = "center";
+				connect = <0x38>;
+				phandle = <0x1cd>;
+			};
+
+			route-dsi0 {
+				status = "disabled";
+				logo,uboot = "logo.bmp";
+				logo,kernel = "logo_kernel.bmp";
+				logo,mode = "center";
+				charge_logo,mode = "center";
+				connect = <0x39>;
+				phandle = <0x1ce>;
+			};
+
+			route-dsi1 {
+				status = "disabled";
+				logo,uboot = "logo.bmp";
+				logo,kernel = "logo_kernel.bmp";
+				logo,mode = "center";
+				charge_logo,mode = "center";
+				connect = <0x3a>;
+				phandle = <0x1cf>;
+			};
+
+			route-edp0 {
+				status = "disabled";
+				logo,uboot = "logo.bmp";
+				logo,kernel = "logo_kernel.bmp";
+				logo,mode = "center";
+				charge_logo,mode = "center";
+				connect = <0x3b>;
+				phandle = <0x1d0>;
+			};
+
+			route-edp1 {
+				status = "disabled";
+				logo,uboot = "logo.bmp";
+				logo,kernel = "logo_kernel.bmp";
+				logo,mode = "center";
+				charge_logo,mode = "center";
+				phandle = <0x1d1>;
+			};
+
+			route-hdmi0 {
+				status = "okay";
+				logo,uboot = "logo.bmp";
+				logo,kernel = "logo_kernel.bmp";
+				logo,mode = "center";
+				charge_logo,mode = "center";
+				connect = <0x3c>;
+				phandle = <0x1d2>;
+			};
+
+			route-rgb {
+				status = "disabled";
+				logo,uboot = "logo.bmp";
+				logo,kernel = "logo_kernel.bmp";
+				logo,mode = "center";
+				charge_logo,mode = "center";
+				connect = <0x3d>;
+				phandle = <0x1d3>;
+			};
+		};
+	};
+
+	dmc {
+		compatible = "rockchip,rk3588-dmc";
+		interrupts = <0x00 0x49 0x04>;
+		interrupt-names = "complete";
+		devfreq-events = <0x3e>;
+		clocks = <0x0e 0x04>;
+		clock-names = "dmc_clk";
+		operating-points-v2 = <0x3f>;
+		upthreshold = <0x28>;
+		downdifferential = <0x14>;
+		system-status-level = <0x01 0x04 0x08 0x08 0x02 0x01 0x10 0x04 0x10000 0x04 0x80000 0x04 0x1000 0x08 0x4000 0x08 0x2000 0x08 0xc00 0x08 0x40000 0x08>;
+		auto-freq-en = <0x01>;
+		status = "disabled";
+		center-supply = <0x40>;
+		mem-supply = <0x41>;
+		phandle = <0x1d4>;
+	};
+
+	dmc-opp-table {
+		compatible = "operating-points-v2";
+		nvmem-cells = <0x42>;
+		nvmem-cell-names = "leakage";
+		rockchip,leakage-voltage-sel = <0x01 0x1f 0x00 0x20 0x2c 0x01 0x2d 0x39 0x02 0x3a 0xfe 0x03>;
+		rockchip,temp-hysteresis = <0x1388>;
+		rockchip,low-temp = <0x2710>;
+		rockchip,low-temp-min-volt = <0xb71b0>;
+		phandle = <0x3f>;
+
+		opp-528000000 {
+			opp-hz = <0x00 0x1f78a400>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xd59f8 0xb1008 0xb1008 0xb71b0>;
+			opp-microvolt-L1 = <0xa4cb8 0xa4cb8 0xd59f8 0xaae60 0xaae60 0xb71b0>;
+			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xd59f8 0xa7d8c 0xa7d8c 0xb71b0>;
+			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xd59f8 0xa4cb8 0xa4cb8 0xb71b0>;
+		};
+
+		opp-1068000000 {
+			opp-hz = <0x00 0x3fa86300>;
+			opp-microvolt = <0xb1008 0xb1008 0xd59f8 0xb40dc 0xb40dc 0xb71b0>;
+			opp-microvolt-L1 = <0xaae60 0xaae60 0xd59f8 0xadf34 0xadf34 0xb71b0>;
+			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xd59f8 0xaae60 0xaae60 0xb71b0>;
+			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xd59f8 0xa7d8c 0xa7d8c 0xb71b0>;
+		};
+
+		opp-1560000000 {
+			opp-hz = <0x00 0x5cfbb600>;
+			opp-microvolt = <0xc3500 0xc3500 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
+			opp-microvolt-L1 = <0xbd358 0xbd358 0xd59f8 0xb1008 0xb1008 0xb71b0>;
+			opp-microvolt-L2 = <0xb71b0 0xb71b0 0xd59f8 0xadf34 0xadf34 0xb71b0>;
+			opp-microvolt-L3 = <0xb1008 0xb1008 0xd59f8 0xaae60 0xaae60 0xb71b0>;
+		};
+
+		opp-2750000000 {
+			opp-hz = <0x00 0xa3e9ab80>;
+			opp-microvolt = <0xd59f8 0xd59f8 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
+			opp-microvolt-L1 = <0xcf850 0xcf850 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
+			opp-microvolt-L2 = <0xcc77c 0xcc77c 0xd59f8 0xb1008 0xb1008 0xb71b0>;
+			opp-microvolt-L3 = <0xc96a8 0xc8320 0xd59f8 0xaae60 0xaae60 0xb71b0>;
+		};
+	};
+
+	firmware {
+
+		scmi {
+			compatible = "arm,scmi-smc";
+			shmem = <0x43>;
+			arm,smc-id = <0x82000010>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			phandle = <0x1d5>;
+
+			protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <0x01>;
+				assigned-clocks = <0x0e 0x00 0x0e 0x02 0x0e 0x03>;
+				assigned-clock-rates = <0x30a32c00 0x30a32c00 0x30a32c00>;
+				phandle = <0x0e>;
+			};
+
+			protocol@16 {
+				reg = <0x16>;
+				#reset-cells = <0x01>;
+				phandle = <0x112>;
+			};
+		};
+
+		sdei {
+			compatible = "arm,sdei-1.0";
+			method = "smc";
+			phandle = <0x1d6>;
+		};
+
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+			phandle = <0x1d7>;
+		};
+	};
+
+	jpege-ccu {
+		compatible = "rockchip,vpu-jpege-ccu";
+		status = "okay";
+		phandle = <0xb1>;
+	};
+
+	mpp-srv {
+		compatible = "rockchip,mpp-service";
+		rockchip,taskqueue-count = <0x0c>;
+		rockchip,resetgroup-count = <0x01>;
+		status = "okay";
+		phandle = <0xac>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	rkcif-dvp {
+		compatible = "rockchip,rkcif-dvp";
+		rockchip,hw = <0x44>;
+		iommus = <0x45>;
+		status = "disabled";
+		phandle = <0x46>;
+	};
+
+	rkcif-dvp-sditf {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x46>;
+		status = "disabled";
+		phandle = <0x1d8>;
+	};
+
+	rkcif-mipi-lvds {
+		compatible = "rockchip,rkcif-mipi-lvds";
+		rockchip,hw = <0x44>;
+		iommus = <0x45>;
+		status = "disabled";
+		phandle = <0x48>;
+
+		port {
+
+			endpoint {
+				remote-endpoint = <0x47>;
+				phandle = <0xc6>;
+			};
+		};
+	};
+
+	rkcif-mipi-lvds-sditf {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x48>;
+		status = "disabled";
+		phandle = <0x1d9>;
+
+		port {
+
+			endpoint {
+				remote-endpoint = <0x49>;
+				phandle = <0x52>;
+			};
+		};
+	};
+
+	rkcif-mipi-lvds-sditf-vir1 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x48>;
+		status = "disabled";
+		phandle = <0x1da>;
+	};
+
+	rkcif-mipi-lvds-sditf-vir2 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x48>;
+		status = "disabled";
+		phandle = <0x1db>;
+	};
+
+	rkcif-mipi-lvds-sditf-vir3 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x48>;
+		status = "disabled";
+		phandle = <0x1dc>;
+	};
+
+	rkcif-mipi-lvds1 {
+		compatible = "rockchip,rkcif-mipi-lvds";
+		rockchip,hw = <0x44>;
+		iommus = <0x45>;
+		status = "disabled";
+		phandle = <0x4b>;
+
+		port {
+
+			endpoint {
+				remote-endpoint = <0x4a>;
+				phandle = <0xc8>;
+			};
+		};
+	};
+
+	rkcif-mipi-lvds1-sditf {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x4b>;
+		status = "disabled";
+		phandle = <0x1dd>;
+
+		port {
+
+			endpoint {
+				remote-endpoint = <0x4c>;
+				phandle = <0x55>;
+			};
+		};
+	};
+
+	rkcif-mipi-lvds1-sditf-vir1 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x4b>;
+		status = "disabled";
+		phandle = <0x1de>;
+	};
+
+	rkcif-mipi-lvds1-sditf-vir2 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x4b>;
+		status = "disabled";
+		phandle = <0x1df>;
+	};
+
+	rkcif-mipi-lvds1-sditf-vir3 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x4b>;
+		status = "disabled";
+		phandle = <0x1e0>;
+	};
+
+	rkcif-mipi-lvds2 {
+		compatible = "rockchip,rkcif-mipi-lvds";
+		rockchip,hw = <0x44>;
+		iommus = <0x45>;
+		status = "disabled";
+		phandle = <0x4e>;
+
+		port {
+
+			endpoint {
+				remote-endpoint = <0x4d>;
+				phandle = <0xca>;
+			};
+		};
+	};
+
+	rkcif-mipi-lvds2-sditf {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x4e>;
+		status = "disabled";
+		phandle = <0x1e1>;
+
+		port {
+
+			endpoint {
+				remote-endpoint = <0x4f>;
+				phandle = <0x53>;
+			};
+		};
+	};
+
+	rkcif-mipi-lvds2-sditf-vir1 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x4e>;
+		status = "disabled";
+		phandle = <0x1e2>;
+	};
+
+	rkcif-mipi-lvds2-sditf-vir2 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x4e>;
+		status = "disabled";
+		phandle = <0x1e3>;
+	};
+
+	rkcif-mipi-lvds2-sditf-vir3 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x4e>;
+		status = "disabled";
+		phandle = <0x1e4>;
+	};
+
+	rkcif-mipi-lvds3 {
+		compatible = "rockchip,rkcif-mipi-lvds";
+		rockchip,hw = <0x44>;
+		iommus = <0x45>;
+		status = "disabled";
+		phandle = <0x50>;
+	};
+
+	rkcif-mipi-lvds3-sditf {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x50>;
+		status = "disabled";
+		phandle = <0x1e5>;
+	};
+
+	rkcif-mipi-lvds3-sditf-vir1 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x50>;
+		status = "disabled";
+		phandle = <0x1e6>;
+	};
+
+	rkcif-mipi-lvds3-sditf-vir2 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x50>;
+		status = "disabled";
+		phandle = <0x1e7>;
+	};
+
+	rkcif-mipi-lvds3-sditf-vir3 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x50>;
+		status = "disabled";
+		phandle = <0x1e8>;
+	};
+
+	rkisp0-vir0 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <0x51>;
+		status = "disabled";
+		phandle = <0x1e9>;
+
+		port {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			endpoint@0 {
+				reg = <0x00>;
+				remote-endpoint = <0x52>;
+				phandle = <0x49>;
+			};
+		};
+	};
+
+	rkisp0-vir1 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <0x51>;
+		status = "disabled";
+		phandle = <0x1ea>;
+
+		port {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			endpoint@0 {
+				reg = <0x00>;
+				remote-endpoint = <0x53>;
+				phandle = <0x4f>;
+			};
+		};
+	};
+
+	rkisp0-vir2 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <0x51>;
+		status = "disabled";
+		phandle = <0x1eb>;
+	};
+
+	rkisp0-vir3 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <0x51>;
+		status = "disabled";
+		phandle = <0x1ec>;
+	};
+
+	rkisp1-vir0 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <0x54>;
+		status = "disabled";
+		phandle = <0x1ed>;
+
+		port {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			endpoint@0 {
+				reg = <0x00>;
+				remote-endpoint = <0x55>;
+				phandle = <0x4c>;
+			};
+		};
+	};
+
+	rkisp1-vir1 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <0x54>;
+		status = "disabled";
+		phandle = <0x1ee>;
+	};
+
+	rkisp1-vir2 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <0x54>;
+		status = "disabled";
+		phandle = <0x1ef>;
+	};
+
+	rkisp1-vir3 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <0x54>;
+		status = "disabled";
+		phandle = <0x1f0>;
+	};
+
+	rkispp0-vir0 {
+		compatible = "rockchip,rk3588-rkispp-vir";
+		rockchip,hw = <0x56>;
+		status = "disabled";
+		phandle = <0x1f1>;
+	};
+
+	rkispp1-vir0 {
+		compatible = "rockchip,rk3588-rkispp-vir";
+		rockchip,hw = <0x57>;
+		status = "disabled";
+		phandle = <0x1f2>;
+	};
+
+	rkvenc-ccu {
+		compatible = "rockchip,rkv-encoder-v2-ccu";
+		status = "okay";
+		phandle = <0xb7>;
+	};
+
+	rockchip-suspend {
+		compatible = "rockchip,pm-rk3588";
+		status = "okay";
+		rockchip,sleep-debug-en = <0x01>;
+		rockchip,sleep-mode-config = <0x5000604>;
+		rockchip,wakeup-config = <0x100>;
+		phandle = <0x1f3>;
+	};
+
+	rockchip-system-monitor {
+		compatible = "rockchip,system-monitor";
+		rockchip,thermal-zone = "soc-thermal";
+		phandle = <0x1f4>;
+	};
+
+	thermal-zones {
+		phandle = <0x1f5>;
+
+		soc-thermal {
+			polling-delay-passive = <0x14>;
+			polling-delay = <0x3e8>;
+			sustainable-power = <0x834>;
+			thermal-sensors = <0x58 0x00>;
+			phandle = <0x1f6>;
+
+			trips {
+
+				trip-point-0 {
+					temperature = <0x124f8>;
+					hysteresis = <0x7d0>;
+					type = "passive";
+					phandle = <0x1f7>;
+				};
+
+				trip-point-1 {
+					temperature = <0x14c08>;
+					hysteresis = <0x7d0>;
+					type = "passive";
+					phandle = <0x59>;
+				};
+
+				soc-crit {
+					temperature = <0x1c138>;
+					hysteresis = <0x7d0>;
+					type = "critical";
+					phandle = <0x1f8>;
+				};
+			};
+
+			cooling-maps {
+
+				map0 {
+					trip = <0x59>;
+					cooling-device = <0x06 0xffffffff 0xffffffff>;
+					contribution = <0x400>;
+				};
+
+				map1 {
+					trip = <0x59>;
+					cooling-device = <0x0a 0xffffffff 0xffffffff>;
+					contribution = <0x400>;
+				};
+
+				map2 {
+					trip = <0x59>;
+					cooling-device = <0x0c 0xffffffff 0xffffffff>;
+					contribution = <0x400>;
+				};
+
+				map3 {
+					trip = <0x59>;
+					cooling-device = <0x5a 0xffffffff 0xffffffff>;
+					contribution = <0x400>;
+				};
+			};
+		};
+
+		bigcore0-thermal {
+			polling-delay-passive = <0x14>;
+			polling-delay = <0x3e8>;
+			thermal-sensors = <0x58 0x01>;
+			phandle = <0x1f9>;
+		};
+
+		bigcore1-thermal {
+			polling-delay-passive = <0x14>;
+			polling-delay = <0x3e8>;
+			thermal-sensors = <0x58 0x02>;
+			phandle = <0x1fa>;
+		};
+
+		littlecore-thermal {
+			polling-delay-passive = <0x14>;
+			polling-delay = <0x3e8>;
+			thermal-sensors = <0x58 0x03>;
+			phandle = <0x1fb>;
+		};
+
+		center-thermal {
+			polling-delay-passive = <0x14>;
+			polling-delay = <0x3e8>;
+			thermal-sensors = <0x58 0x04>;
+			phandle = <0x1fc>;
+		};
+
+		gpu-thermal {
+			polling-delay-passive = <0x14>;
+			polling-delay = <0x3e8>;
+			thermal-sensors = <0x58 0x05>;
+			phandle = <0x1fd>;
+		};
+
+		npu-thermal {
+			polling-delay-passive = <0x14>;
+			polling-delay = <0x3e8>;
+			thermal-sensors = <0x58 0x06>;
+			phandle = <0x1fe>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>;
+	};
+
+	sram@10f000 {
+		compatible = "mmio-sram";
+		reg = <0x00 0x10f000 0x00 0x100>;
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+		ranges = <0x00 0x00 0x10f000 0x100>;
+
+		sram@0 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x00 0x100>;
+			phandle = <0x43>;
+		};
+	};
+
+	gpu@fb000000 {
+		compatible = "arm,mali-bifrost";
+		reg = <0x00 0xfb000000 0x00 0x200000>;
+		interrupts = <0x00 0x5e 0x04 0x00 0x5d 0x04 0x00 0x5c 0x04>;
+		interrupt-names = "GPU\0MMU\0JOB";
+		clocks = <0x0e 0x05 0x02 0x115 0x02 0x116 0x02 0x114>;
+		clock-names = "clk_mali\0clk_gpu_coregroup\0clk_gpu_stacks\0clk_gpu";
+		assigned-clocks = <0x0e 0x05>;
+		assigned-clock-rates = <0xbebc200>;
+		power-domains = <0x5b 0x0c>;
+		operating-points-v2 = <0x5c>;
+		#cooling-cells = <0x02>;
+		dynamic-power-coefficient = <0xba6>;
+		upthreshold = <0x1e>;
+		downdifferential = <0x0a>;
+		status = "okay";
+		mali-supply = <0x5d>;
+		mem-supply = <0x5d>;
+		phandle = <0x5a>;
+	};
+
+	gpu-opp-table {
+		compatible = "operating-points-v2";
+		nvmem-cells = <0x5e>;
+		nvmem-cell-names = "leakage";
+		rockchip,pvtm-voltage-sel = <0x00 0x32f 0x00 0x330 0x343 0x01 0x344 0x35c 0x02 0x35d 0x375 0x03 0x376 0x38e 0x04 0x38f 0x270f 0x05>;
+		rockchip,pvtm-pvtpll;
+		rockchip,pvtm-offset = <0x1c>;
+		rockchip,pvtm-sample-time = <0x44c>;
+		rockchip,pvtm-freq = "\0\f5";
+		rockchip,pvtm-volt = <0xb71b0>;
+		rockchip,pvtm-ref-temp = <0x19>;
+		rockchip,pvtm-temp-prop = <0xffffff79 0xffffff79>;
+		rockchip,pvtm-thermal-zone = "gpu-thermal";
+		clocks = <0x02 0x114>;
+		clock-names = "clk";
+		rockchip,grf = <0x5f>;
+		volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>;
+		low-volt-mem-read-margin = <0x04>;
+		intermediate-threshold-freq = <0x61a80>;
+		rockchip,temp-hysteresis = <0x1388>;
+		rockchip,low-temp = <0x2710>;
+		rockchip,low-temp-min-volt = <0xb71b0>;
+		rockchip,high-temp = <0x14c08>;
+		rockchip,high-temp-max-freq = "\0\f5";
+		phandle = <0x5c>;
+
+		opp-300000000 {
+			opp-hz = <0x00 0x11e1a300>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-400000000 {
+			opp-hz = <0x00 0x17d78400>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-500000000 {
+			opp-hz = <0x00 0x1dcd6500>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-600000000 {
+			opp-hz = <0x00 0x23c34600>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-700000000 {
+			opp-hz = <0x00 0x29b92700>;
+			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+			opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
+			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-800000000 {
+			opp-hz = <0x00 0x2faf0800>;
+			opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
+			opp-microvolt-L1 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>;
+			opp-microvolt-L2 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>;
+			opp-microvolt-L3 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>;
+			opp-microvolt-L4 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+			opp-microvolt-L5 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+		};
+
+		opp-900000000 {
+			opp-hz = <0x00 0x35a4e900>;
+			opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
+			opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
+			opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>;
+			opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>;
+			opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
+			opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>;
+		};
+
+		opp-1000000000 {
+			opp-hz = <0x00 0x3b9aca00>;
+			opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>;
+			opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>;
+			opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>;
+			opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>;
+			opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
+			opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
+		};
+	};
+
+	usbdrd3_0 {
+		compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3";
+		clocks = <0x02 0x1a3 0x02 0x1a2 0x02 0x1a1>;
+		clock-names = "ref\0suspend\0bus";
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+		status = "okay";
+		phandle = <0x1ff>;
+
+		usb@fc000000 {
+			compatible = "snps,dwc3";
+			reg = <0x00 0xfc000000 0x00 0x400000>;
+			interrupts = <0x00 0xdc 0x04>;
+			power-domains = <0x5b 0x1f>;
+			resets = <0x02 0x2a4>;
+			reset-names = "usb3-otg";
+			dr_mode = "otg";
+			phys = <0x60 0x61>;
+			phy-names = "usb2-phy\0usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			snps,parkmode-disable-ss-quirk;
+			quirk-skip-phy-init;
+			status = "okay";
+			usb-role-switch;
+			phandle = <0x200>;
+
+			port {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0x62>;
+					phandle = <0x16f>;
+				};
+			};
+		};
+	};
+
+	usb@fc800000 {
+		compatible = "rockchip,rk3588-ehci\0generic-ehci";
+		reg = <0x00 0xfc800000 0x00 0x40000>;
+		interrupts = <0x00 0xd7 0x04>;
+		clocks = <0x02 0x19d 0x02 0x19e 0x63>;
+		clock-names = "usbhost\0arbiter\0utmi";
+		companion = <0x64>;
+		phys = <0x65>;
+		phy-names = "usb2-phy";
+		power-domains = <0x5b 0x1f>;
+		status = "okay";
+		phandle = <0x201>;
+	};
+
+	usb@fc840000 {
+		compatible = "generic-ohci";
+		reg = <0x00 0xfc840000 0x00 0x40000>;
+		interrupts = <0x00 0xd8 0x04>;
+		clocks = <0x02 0x19d 0x02 0x19e 0x63>;
+		clock-names = "usbhost\0arbiter\0utmi";
+		phys = <0x65>;
+		phy-names = "usb2-phy";
+		power-domains = <0x5b 0x1f>;
+		status = "okay";
+		phandle = <0x64>;
+	};
+
+	usb@fc880000 {
+		compatible = "rockchip,rk3588-ehci\0generic-ehci";
+		reg = <0x00 0xfc880000 0x00 0x40000>;
+		interrupts = <0x00 0xda 0x04>;
+		clocks = <0x02 0x19f 0x02 0x1a0 0x66>;
+		clock-names = "usbhost\0arbiter\0utmi";
+		companion = <0x67>;
+		phys = <0x68>;
+		phy-names = "usb2-phy";
+		power-domains = <0x5b 0x1f>;
+		status = "okay";
+		phandle = <0x202>;
+	};
+
+	usb@fc8c0000 {
+		compatible = "generic-ohci";
+		reg = <0x00 0xfc8c0000 0x00 0x40000>;
+		interrupts = <0x00 0xdb 0x04>;
+		clocks = <0x02 0x19f 0x02 0x1a0 0x66>;
+		clock-names = "usbhost\0arbiter\0utmi";
+		phys = <0x68>;
+		phy-names = "usb2-phy";
+		power-domains = <0x5b 0x1f>;
+		status = "okay";
+		phandle = <0x67>;
+	};
+
+	iommu@fc900000 {
+		compatible = "arm,smmu-v3";
+		reg = <0x00 0xfc900000 0x00 0x200000>;
+		interrupts = <0x00 0x171 0x04 0x00 0x173 0x04 0x00 0x176 0x04 0x00 0x16f 0x04>;
+		interrupt-names = "eventq\0gerror\0priq\0cmdq-sync";
+		#iommu-cells = <0x01>;
+		status = "disabled";
+		phandle = <0x203>;
+	};
+
+	iommu@fcb00000 {
+		compatible = "arm,smmu-v3";
+		reg = <0x00 0xfcb00000 0x00 0x200000>;
+		interrupts = <0x00 0x17d 0x04 0x00 0x17f 0x04 0x00 0x182 0x04 0x00 0x17b 0x04>;
+		interrupt-names = "eventq\0gerror\0priq\0cmdq-sync";
+		#iommu-cells = <0x01>;
+		status = "disabled";
+		phandle = <0x204>;
+	};
+
+	usbhost3_0 {
+		compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3";
+		clocks = <0x02 0x179 0x02 0x178 0x02 0x177 0x02 0x17a 0x02 0x166 0x02 0x181>;
+		clock-names = "ref\0suspend\0bus\0utmi\0php\0pipe";
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+		status = "okay";
+		dr_mode = "host";
+		phandle = <0x205>;
+
+		usb@fcd00000 {
+			compatible = "snps,dwc3";
+			reg = <0x00 0xfcd00000 0x00 0x400000>;
+			interrupts = <0x00 0xde 0x04>;
+			resets = <0x02 0x237>;
+			reset-names = "usb3-host";
+			dr_mode = "host";
+			phys = <0x69 0x04>;
+			phy-names = "usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			snps,dis_rxdet_inp3_quirk;
+			snps,parkmode-disable-ss-quirk;
+			status = "okay";
+			phandle = <0x206>;
+		};
+	};
+
+	syscon@fd588000 {
+		compatible = "rockchip,rk3588-pmu0-grf\0syscon\0simple-mfd";
+		reg = <0x00 0xfd588000 0x00 0x2000>;
+		phandle = <0x207>;
+
+		reboot-mode {
+			compatible = "syscon-reboot-mode";
+			offset = <0x80>;
+			mode-bootloader = <0x5242c301>;
+			mode-charge = <0x5242c30b>;
+			mode-fastboot = <0x5242c309>;
+			mode-loader = <0x5242c301>;
+			mode-normal = <0x5242c300>;
+			mode-recovery = <0x5242c303>;
+			mode-ums = <0x5242c30c>;
+			mode-panic = <0x5242c307>;
+			mode-watchdog = <0x5242c308>;
+			phandle = <0x208>;
+		};
+	};
+
+	syscon@fd58a000 {
+		compatible = "rockchip,rk3588-pmu1-grf\0syscon";
+		reg = <0x00 0xfd58a000 0x00 0x2000>;
+		phandle = <0xf9>;
+	};
+
+	syscon@fd58c000 {
+		compatible = "rockchip,rk3588-sys-grf\0syscon\0simple-mfd";
+		reg = <0x00 0xfd58c000 0x00 0x1000>;
+		phandle = <0xc4>;
+
+		rgb {
+			compatible = "rockchip,rk3588-rgb";
+			pinctrl-names = "default";
+			pinctrl-0 = <0x6a>;
+			status = "disabled";
+			phandle = <0x209>;
+
+			ports {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				port@0 {
+					reg = <0x00>;
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+
+					endpoint@2 {
+						reg = <0x02>;
+						remote-endpoint = <0x3d>;
+						status = "disabled";
+						phandle = <0xdc>;
+					};
+				};
+			};
+		};
+	};
+
+	syscon@fd590000 {
+		compatible = "rockchip,rk3588-bigcore0-grf\0syscon";
+		reg = <0x00 0xfd590000 0x00 0x100>;
+		phandle = <0x23>;
+	};
+
+	syscon@fd592000 {
+		compatible = "rockchip,rk3588-bigcore1-grf\0syscon";
+		reg = <0x00 0xfd592000 0x00 0x100>;
+		phandle = <0x25>;
+	};
+
+	syscon@fd594000 {
+		compatible = "rockchip,rk3588-litcore-grf\0syscon";
+		reg = <0x00 0xfd594000 0x00 0x100>;
+		phandle = <0x21>;
+	};
+
+	syscon@fd598000 {
+		compatible = "rockchip,rk3588-dsu-grf\0syscon";
+		reg = <0x00 0xfd598000 0x00 0x100>;
+		phandle = <0x20a>;
+	};
+
+	syscon@fd5a0000 {
+		compatible = "rockchip,rk3588-gpu-grf\0syscon";
+		reg = <0x00 0xfd5a0000 0x00 0x100>;
+		phandle = <0x5f>;
+	};
+
+	syscon@fd5a2000 {
+		compatible = "rockchip,rk3588-npu-grf\0syscon";
+		reg = <0x00 0xfd5a2000 0x00 0x100>;
+		phandle = <0xaa>;
+	};
+
+	syscon@fd5a4000 {
+		compatible = "rockchip,rk3588-vop-grf\0syscon";
+		reg = <0x00 0xfd5a4000 0x00 0x2000>;
+		phandle = <0xcc>;
+	};
+
+	syscon@fd5a6000 {
+		compatible = "rockchip,rk3588-vo-grf\0syscon";
+		reg = <0x00 0xfd5a6000 0x00 0x2000>;
+		clocks = <0x6b>;
+		phandle = <0xea>;
+	};
+
+	syscon@fd5a8000 {
+		compatible = "rockchip,rk3588-vo-grf\0syscon";
+		reg = <0x00 0xfd5a8000 0x00 0x100>;
+		clocks = <0x6c>;
+		phandle = <0xcd>;
+	};
+
+	syscon@fd5ac000 {
+		compatible = "rockchip,rk3588-usb-grf\0syscon";
+		reg = <0x00 0xfd5ac000 0x00 0x4000>;
+		phandle = <0x6d>;
+	};
+
+	syscon@fd5b0000 {
+		compatible = "rockchip,rk3588-php-grf\0syscon";
+		reg = <0x00 0xfd5b0000 0x00 0x1000>;
+		phandle = <0x6e>;
+	};
+
+	syscon@fd5b4000 {
+		compatible = "rockchip,mipi-dphy-grf\0syscon";
+		reg = <0x00 0xfd5b4000 0x00 0x1000>;
+		phandle = <0x188>;
+	};
+
+	syscon@fd5b5000 {
+		compatible = "rockchip,mipi-dphy-grf\0syscon";
+		reg = <0x00 0xfd5b5000 0x00 0x1000>;
+		phandle = <0x20b>;
+	};
+
+	syscon@fd5bc000 {
+		compatible = "rockchip,pipe-phy-grf\0syscon";
+		reg = <0x00 0xfd5bc000 0x00 0x100>;
+		phandle = <0x189>;
+	};
+
+	syscon@fd5c4000 {
+		compatible = "rockchip,pipe-phy-grf\0syscon";
+		reg = <0x00 0xfd5c4000 0x00 0x100>;
+		phandle = <0x18a>;
+	};
+
+	syscon@fd5c8000 {
+		compatible = "rockchip,rk3588-usbdpphy-grf\0syscon";
+		reg = <0x00 0xfd5c8000 0x00 0x4000>;
+		phandle = <0x182>;
+	};
+
+	syscon@fd5d0000 {
+		compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd";
+		reg = <0x00 0xfd5d0000 0x00 0x4000>;
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+		phandle = <0x181>;
+
+		usb2-phy@0 {
+			compatible = "rockchip,rk3588-usb2phy";
+			reg = <0x00 0x10>;
+			interrupts = <0x00 0x189 0x04>;
+			resets = <0x02 0xc0047 0x02 0x488>;
+			reset-names = "phy\0apb";
+			clocks = <0x02 0x2b5>;
+			clock-names = "phyclk";
+			clock-output-names = "usb480m_phy0";
+			#clock-cells = <0x00>;
+			rockchip,usbctrl-grf = <0x6d>;
+			status = "okay";
+			phandle = <0x183>;
+
+			otg-port {
+				#phy-cells = <0x00>;
+				status = "okay";
+				rockchip,typec-vbus-det;
+				phandle = <0x60>;
+			};
+		};
+	};
+
+	syscon@fd5d8000 {
+		compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd";
+		reg = <0x00 0xfd5d8000 0x00 0x4000>;
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+		phandle = <0x20c>;
+
+		usb2-phy@8000 {
+			compatible = "rockchip,rk3588-usb2phy";
+			reg = <0x8000 0x10>;
+			interrupts = <0x00 0x187 0x04>;
+			resets = <0x02 0xc0049 0x02 0x48a>;
+			reset-names = "phy\0apb";
+			clocks = <0x02 0x2b5>;
+			clock-names = "phyclk";
+			clock-output-names = "usb480m_phy2";
+			#clock-cells = <0x00>;
+			status = "okay";
+			phandle = <0x63>;
+
+			host-port {
+				#phy-cells = <0x00>;
+				status = "okay";
+				phandle = <0x65>;
+			};
+		};
+	};
+
+	syscon@fd5dc000 {
+		compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd";
+		reg = <0x00 0xfd5dc000 0x00 0x4000>;
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+		phandle = <0x20d>;
+
+		usb2-phy@c000 {
+			compatible = "rockchip,rk3588-usb2phy";
+			reg = <0xc000 0x10>;
+			interrupts = <0x00 0x188 0x04>;
+			resets = <0x02 0xc004a 0x02 0x48b>;
+			reset-names = "phy\0apb";
+			clocks = <0x02 0x2b5>;
+			clock-names = "phyclk";
+			clock-output-names = "usb480m_phy3";
+			#clock-cells = <0x00>;
+			status = "okay";
+			phandle = <0x66>;
+
+			host-port {
+				#phy-cells = <0x00>;
+				status = "okay";
+				phandle = <0x68>;
+			};
+		};
+	};
+
+	syscon@fd5e0000 {
+		compatible = "rockchip,rk3588-hdptxphy-grf\0syscon";
+		reg = <0x00 0xfd5e0000 0x00 0x100>;
+		phandle = <0x180>;
+	};
+
+	syscon@fd5e8000 {
+		compatible = "rockchip,mipi-dcphy-grf\0syscon";
+		reg = <0x00 0xfd5e8000 0x00 0x4000>;
+		phandle = <0x186>;
+	};
+
+	syscon@fd5ec000 {
+		compatible = "rockchip,mipi-dcphy-grf\0syscon";
+		reg = <0x00 0xfd5ec000 0x00 0x4000>;
+		phandle = <0x187>;
+	};
+
+	syscon@fd5f0000 {
+		compatible = "rockchip,rk3588-ioc\0syscon";
+		reg = <0x00 0xfd5f0000 0x00 0x10000>;
+		phandle = <0x18b>;
+	};
+
+	clock-controller@fd7c0000 {
+		compatible = "rockchip,rk3588-cru";
+		rockchip,grf = <0x6e>;
+		reg = <0x00 0xfd7c0000 0x00 0x5c000>;
+		#clock-cells = <0x01>;
+		#reset-cells = <0x01>;
+		assigned-clocks = <0x02 0x09 0x02 0x05 0x02 0x08 0x02 0x07 0x02 0xd8 0x02 0xda 0x02 0xd9 0x02 0x10e 0x02 0x10f 0x02 0x110 0x02 0x299 0x02 0x29a 0x02 0x7b 0x02 0xec 0x02 0x114>;
+		assigned-clock-rates = <0x4190ab00 0x2ee00000 0x32a9f880 0x46cf7100 0x29d7ab80 0x17d78400 0x1dcd6500 0x2faf0800 0x5f5e100 0x17d78400 0x5f5e100 0xbebc200 0x165a0bc0 0x8f0d180 0xbebc200>;
+		phandle = <0x02>;
+	};
+
+	i2c@fd880000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfd880000 0x00 0x1000>;
+		clocks = <0x02 0x287 0x02 0x286>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x13d 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x6f>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+		phandle = <0x20e>;
+
+		rk8602@42 {
+			compatible = "rockchip,rk8602";
+			reg = <0x42>;
+			vin-supply = <0x70>;
+			regulator-compatible = "rk860x-reg";
+			regulator-name = "vdd_cpu_big0_s0";
+			regulator-min-microvolt = <0x86470>;
+			regulator-max-microvolt = <0x100590>;
+			regulator-ramp-delay = <0x8fc>;
+			rockchip,suspend-voltage-selector = <0x01>;
+			regulator-boot-on;
+			regulator-always-on;
+			phandle = <0x18>;
+
+			regulator-state-mem {
+				regulator-off-in-suspend;
+			};
+		};
+
+		rk8603@43 {
+			compatible = "rockchip,rk8603";
+			reg = <0x43>;
+			vin-supply = <0x70>;
+			regulator-compatible = "rk860x-reg";
+			regulator-name = "vdd_cpu_big1_s0";
+			regulator-min-microvolt = <0x86470>;
+			regulator-max-microvolt = <0x100590>;
+			regulator-ramp-delay = <0x8fc>;
+			rockchip,suspend-voltage-selector = <0x01>;
+			regulator-boot-on;
+			regulator-always-on;
+			phandle = <0x1c>;
+
+			regulator-state-mem {
+				regulator-off-in-suspend;
+			};
+		};
+	};
+
+	serial@fd890000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfd890000 0x00 0x100>;
+		interrupts = <0x00 0x14b 0x04>;
+		clocks = <0x02 0x2ae 0x02 0x2af>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0x71 0x06 0x71 0x07>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x72>;
+		status = "disabled";
+		phandle = <0x20f>;
+	};
+
+	pwm@fd8b0000 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfd8b0000 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x73>;
+		clocks = <0x02 0x2a5 0x02 0x2a4>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+		phandle = <0x210>;
+	};
+
+	pwm@fd8b0010 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfd8b0010 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x74>;
+		clocks = <0x02 0x2a5 0x02 0x2a4>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+		phandle = <0x211>;
+	};
+
+	pwm@fd8b0020 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfd8b0020 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x75>;
+		clocks = <0x02 0x2a5 0x02 0x2a4>;
+		clock-names = "pwm\0pclk";
+		status = "okay";
+		phandle = <0x198>;
+	};
+
+	pwm@fd8b0030 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfd8b0030 0x00 0x10>;
+		interrupts = <0x00 0x158 0x04 0x00 0x159 0x04>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x76>;
+		clocks = <0x02 0x2a5 0x02 0x2a4>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+		phandle = <0x212>;
+	};
+
+	power-management@fd8d8000 {
+		compatible = "rockchip,rk3588-pmu\0syscon\0simple-mfd";
+		reg = <0x00 0xfd8d8000 0x00 0x400>;
+		phandle = <0xce>;
+
+		power-controller {
+			compatible = "rockchip,rk3588-power-controller";
+			#power-domain-cells = <0x01>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			status = "okay";
+			phandle = <0x5b>;
+
+			power-domain@8 {
+				reg = <0x08>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				power-domain@9 {
+					reg = <0x09>;
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+					clocks = <0x02 0x12f 0x02 0x131 0x02 0x130 0x02 0x126>;
+					pm_qos = <0x77 0x78 0x79>;
+
+					power-domain@10 {
+						reg = <0x0a>;
+						clocks = <0x02 0x12f 0x02 0x131 0x02 0x130>;
+						pm_qos = <0x7a>;
+					};
+
+					power-domain@11 {
+						reg = <0x0b>;
+						clocks = <0x02 0x12f 0x02 0x131 0x02 0x130>;
+						pm_qos = <0x7b>;
+					};
+				};
+			};
+
+			power-domain@12 {
+				reg = <0x0c>;
+				clocks = <0x02 0x114 0x02 0x115 0x02 0x116>;
+				pm_qos = <0x7c 0x7d 0x7e 0x7f>;
+			};
+
+			power-domain@13 {
+				reg = <0x0d>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				power-domain@14 {
+					reg = <0x0e>;
+					clocks = <0x02 0x18f 0x02 0x1be 0x02 0x1bc 0x02 0x190 0x02 0x18e>;
+					pm_qos = <0x80>;
+				};
+
+				power-domain@15 {
+					reg = <0x0f>;
+					clocks = <0x02 0x194 0x02 0x1be 0x02 0x1bc 0x02 0x195>;
+					pm_qos = <0x81>;
+				};
+
+				power-domain@16 {
+					reg = <0x10>;
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+					clocks = <0x02 0x1c4 0x02 0x1c5>;
+					pm_qos = <0x82 0x83 0x84>;
+
+					power-domain@17 {
+						reg = <0x11>;
+						clocks = <0x02 0x1c9 0x02 0x1c4 0x02 0x1c5 0x02 0x1ca>;
+						pm_qos = <0x85 0x86 0x87>;
+					};
+				};
+			};
+
+			power-domain@21 {
+				reg = <0x15>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				clocks = <0x02 0x1be 0x02 0x1bd 0x02 0x1bc 0x02 0x1bf 0x02 0x1aa 0x02 0x1a9 0x02 0x1ac 0x02 0x1ad 0x02 0x1ae 0x02 0x1af 0x02 0x1b0 0x02 0x1b1 0x02 0x1b2 0x02 0x1b3 0x02 0x1b4 0x02 0x1b5 0x02 0x1b7 0x02 0x1b6>;
+				pm_qos = <0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f>;
+
+				power-domain@23 {
+					reg = <0x17>;
+					clocks = <0x02 0x4b 0x02 0x49 0x02 0x1be>;
+					pm_qos = <0x90>;
+				};
+
+				power-domain@14 {
+					reg = <0x0e>;
+					clocks = <0x02 0x18f 0x02 0x1be 0x02 0x1bc 0x02 0x190>;
+					pm_qos = <0x80>;
+				};
+
+				power-domain@15 {
+					reg = <0x0f>;
+					clocks = <0x02 0x194 0x02 0x1be 0x02 0x1bc>;
+					pm_qos = <0x81>;
+				};
+
+				power-domain@22 {
+					reg = <0x16>;
+					clocks = <0x02 0x1ba 0x02 0x1b9>;
+					pm_qos = <0x91>;
+				};
+			};
+
+			power-domain@24 {
+				reg = <0x18>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				clocks = <0x02 0x26e 0x02 0x26d 0x02 0x270>;
+				pm_qos = <0x92 0x93>;
+
+				power-domain@25 {
+					reg = <0x19>;
+					clocks = <0x02 0x1f6 0x02 0x1f7 0x02 0x1f5 0x02 0x1f3 0x02 0x1ee 0x02 0x1ed 0x02 0x26d>;
+					pm_qos = <0x94>;
+				};
+			};
+
+			power-domain@26 {
+				reg = <0x1a>;
+				clocks = <0x02 0x22e 0x02 0x22f 0x02 0x22d 0x02 0x218 0x02 0x217 0x02 0x22b 0x02 0x264>;
+				pm_qos = <0x95 0x96>;
+			};
+
+			power-domain@27 {
+				reg = <0x1b>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				clocks = <0x02 0x1e1 0x02 0x1e2 0x02 0x1df 0x02 0x1de 0x02 0x1e5 0x02 0x1e4>;
+				pm_qos = <0x97 0x98 0x99 0x9a>;
+
+				power-domain@28 {
+					reg = <0x1c>;
+					clocks = <0x02 0x121 0x02 0x120 0x02 0x1e1 0x02 0x1e2>;
+					pm_qos = <0x9b 0x9c>;
+				};
+
+				power-domain@29 {
+					reg = <0x1d>;
+					clocks = <0x02 0x1d6 0x02 0x1d5 0x02 0x1d9 0x02 0x1d8 0x02 0x1e2>;
+					pm_qos = <0x9d 0x9e>;
+				};
+			};
+
+			power-domain@30 {
+				reg = <0x1e>;
+				clocks = <0x02 0x189 0x02 0x18a>;
+				pm_qos = <0x9f>;
+			};
+
+			power-domain@31 {
+				reg = <0x1f>;
+				clocks = <0x02 0x166 0x02 0x19b 0x02 0x19c 0x02 0x19d 0x02 0x19e 0x02 0x19f 0x02 0x1a0>;
+				pm_qos = <0xa0 0xa1 0xa2 0xa3>;
+			};
+
+			power-domain@33 {
+				reg = <0x21>;
+				clocks = <0x02 0x166 0x02 0x169 0x02 0x16a>;
+			};
+
+			power-domain@34 {
+				reg = <0x22>;
+				clocks = <0x02 0x166 0x02 0x169 0x02 0x16a>;
+			};
+
+			power-domain@37 {
+				reg = <0x25>;
+				clocks = <0x02 0x199 0x02 0x140>;
+				pm_qos = <0xa4>;
+			};
+
+			power-domain@38 {
+				reg = <0x26>;
+				clocks = <0x02 0x3c 0x02 0x3d>;
+			};
+
+			power-domain@40 {
+				reg = <0x28>;
+				pm_qos = <0xa5>;
+			};
+		};
+	};
+
+	pvtm@fda40000 {
+		compatible = "rockchip,rk3588-bigcore0-pvtm";
+		reg = <0x00 0xfda40000 0x00 0x100>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		pvtm@0 {
+			reg = <0x00>;
+			clocks = <0x02 0x2c6 0x02 0x15>;
+			clock-names = "clk\0pclk";
+		};
+	};
+
+	pvtm@fda50000 {
+		compatible = "rockchip,rk3588-bigcore1-pvtm";
+		reg = <0x00 0xfda50000 0x00 0x100>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		pvtm@1 {
+			reg = <0x01>;
+			clocks = <0x02 0x2c8 0x02 0x17>;
+			clock-names = "clk\0pclk";
+		};
+	};
+
+	pvtm@fda60000 {
+		compatible = "rockchip,rk3588-litcore-pvtm";
+		reg = <0x00 0xfda60000 0x00 0x100>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		pvtm@2 {
+			reg = <0x02>;
+			clocks = <0x02 0x2ca 0x02 0x1b>;
+			clock-names = "clk\0pclk";
+		};
+	};
+
+	pvtm@fdaf0000 {
+		compatible = "rockchip,rk3588-npu-pvtm";
+		reg = <0x00 0xfdaf0000 0x00 0x100>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		pvtm@3 {
+			reg = <0x03>;
+			clocks = <0x02 0x12b 0x02 0x129>;
+			clock-names = "clk\0pclk";
+			resets = <0x02 0x1de 0x02 0x1dc>;
+			reset-names = "rts\0rst-p";
+		};
+	};
+
+	pvtm@fdb30000 {
+		compatible = "rockchip,rk3588-gpu-pvtm";
+		reg = <0x00 0xfdb30000 0x00 0x100>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		pvtm@4 {
+			reg = <0x04>;
+			clocks = <0x02 0x118>;
+			clock-names = "clk";
+			resets = <0x02 0x430 0x02 0x42f>;
+			reset-names = "rts\0rst-p";
+		};
+	};
+
+	npu@fdab0000 {
+		compatible = "rockchip,rk3588-rknpu";
+		reg = <0x00 0xfdab0000 0x00 0x10000 0x00 0xfdac0000 0x00 0x10000 0x00 0xfdad0000 0x00 0x10000>;
+		interrupts = <0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04>;
+		interrupt-names = "npu0_irq\0npu1_irq\0npu2_irq";
+		clocks = <0x0e 0x06 0x02 0x12d 0x02 0x122 0x02 0x124 0x02 0x12e 0x02 0x123 0x02 0x125 0x02 0x131>;
+		clock-names = "clk_npu\0aclk0\0aclk1\0aclk2\0hclk0\0hclk1\0hclk2\0pclk";
+		assigned-clocks = <0x0e 0x06>;
+		assigned-clock-rates = <0xbebc200>;
+		resets = <0x02 0x1e6 0x02 0x1b0 0x02 0x1c0 0x02 0x1e8 0x02 0x1b2 0x02 0x1c2>;
+		reset-names = "srst_a0\0srst_a1\0srst_a2\0srst_h0\0srst_h1\0srst_h2";
+		power-domains = <0x5b 0x09 0x5b 0x0a 0x5b 0x0b>;
+		power-domain-names = "npu0\0npu1\0npu2";
+		operating-points-v2 = <0xa6>;
+		iommus = <0xa7>;
+		status = "okay";
+		rknpu-supply = <0xa8>;
+		mem-supply = <0xa8>;
+		phandle = <0x213>;
+	};
+
+	npu-opp-table {
+		compatible = "operating-points-v2";
+		nvmem-cells = <0xa9>;
+		nvmem-cell-names = "leakage";
+		rockchip,pvtm-voltage-sel = <0x00 0x32f 0x00 0x330 0x343 0x01 0x344 0x35c 0x02 0x35d 0x375 0x03 0x376 0x38e 0x04 0x38f 0x270f 0x05>;
+		rockchip,pvtm-pvtpll;
+		rockchip,pvtm-offset = <0x50>;
+		rockchip,pvtm-sample-time = <0x44c>;
+		rockchip,pvtm-freq = "\0\f5";
+		rockchip,pvtm-volt = <0xb71b0>;
+		rockchip,pvtm-ref-temp = <0x19>;
+		rockchip,pvtm-temp-prop = <0xffffff8f 0xffffff8f>;
+		rockchip,pvtm-thermal-zone = "npu-thermal";
+		clocks = <0x02 0x12a>;
+		clock-names = "pclk";
+		rockchip,grf = <0xaa>;
+		volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>;
+		low-volt-read-margin = <0x04>;
+		intermediate-threshold-freq = <0x7a120>;
+		rockchip,init-freq = <0xf4240>;
+		rockchip,temp-hysteresis = <0x1388>;
+		rockchip,low-temp = <0x2710>;
+		rockchip,low-temp-min-volt = <0xb71b0>;
+		rockchip,high-temp = <0x14c08>;
+		rockchip,high-temp-max-freq = "\0\f5";
+		phandle = <0xa6>;
+
+		opp-300000000 {
+			opp-hz = <0x00 0x11e1a300>;
+			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+			opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
+			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-400000000 {
+			opp-hz = <0x00 0x17d78400>;
+			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+			opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
+			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-500000000 {
+			opp-hz = <0x00 0x1dcd6500>;
+			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+			opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
+			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-600000000 {
+			opp-hz = <0x00 0x23c34600>;
+			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+			opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
+			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-700000000 {
+			opp-hz = <0x00 0x29b92700>;
+			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+			opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
+			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-800000000 {
+			opp-hz = <0x00 0x2faf0800>;
+			opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
+			opp-microvolt-L2 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>;
+			opp-microvolt-L3 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>;
+			opp-microvolt-L4 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>;
+			opp-microvolt-L5 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+		};
+
+		opp-900000000 {
+			opp-hz = <0x00 0x35a4e900>;
+			opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
+			opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
+			opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>;
+			opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>;
+			opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
+			opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>;
+		};
+
+		opp-1000000000 {
+			opp-hz = <0x00 0x3b9aca00>;
+			opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>;
+			opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>;
+			opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>;
+			opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>;
+			opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
+			opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
+		};
+	};
+
+	iommu@fdab9000 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdab9000 0x00 0x100 0x00 0xfdaba000 0x00 0x100 0x00 0xfdaca000 0x00 0x100 0x00 0xfdada000 0x00 0x100>;
+		interrupts = <0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04>;
+		interrupt-names = "npu0_mmu\0npu1_mmu\0npu2_mmu";
+		clocks = <0x02 0x12d 0x02 0x122 0x02 0x124 0x02 0x12e 0x02 0x123 0x02 0x125>;
+		clock-names = "aclk0\0aclk1\0aclk2\0iface0\0iface1\0iface2";
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0xa7>;
+	};
+
+	vepu@fdb50000 {
+		compatible = "rockchip,vpu-encoder-v2";
+		reg = <0x00 0xfdb50000 0x00 0x400>;
+		interrupts = <0x00 0x78 0x04>;
+		interrupt-names = "irq_vepu";
+		clocks = <0x02 0x1c0 0x02 0x1c1>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		rockchip,normal-rates = <0x2367b880 0x00>;
+		assigned-clocks = <0x02 0x1c0>;
+		assigned-clock-rates = <0x2367b880>;
+		resets = <0x02 0x2c8 0x02 0x2c9>;
+		reset-names = "shared_video_a\0shared_video_h";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xab>;
+		rockchip,srv = <0xac>;
+		rockchip,taskqueue-node = <0x00>;
+		rockchip,resetgroup-node = <0x00>;
+		power-domains = <0x5b 0x15>;
+		status = "okay";
+		phandle = <0x214>;
+	};
+
+	vdpu@fdb50400 {
+		compatible = "rockchip,vpu-decoder-v2";
+		reg = <0x00 0xfdb50400 0x00 0x400>;
+		interrupts = <0x00 0x77 0x04>;
+		interrupt-names = "irq_vdpu";
+		clocks = <0x02 0x1c0 0x02 0x1c1>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		rockchip,normal-rates = <0x2367b880 0x00>;
+		assigned-clocks = <0x02 0x1c0>;
+		assigned-clock-rates = <0x2367b880>;
+		resets = <0x02 0x2c8 0x02 0x2c9>;
+		reset-names = "shared_video_a\0shared_video_h";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xab>;
+		rockchip,srv = <0xac>;
+		rockchip,taskqueue-node = <0x00>;
+		rockchip,resetgroup-node = <0x00>;
+		power-domains = <0x5b 0x15>;
+		status = "okay";
+		phandle = <0x215>;
+	};
+
+	iommu@fdb50800 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdb50800 0x00 0x40>;
+		interrupts = <0x00 0x76 0x04>;
+		interrupt-names = "irq_vdpu_mmu";
+		clocks = <0x02 0x1c0 0x02 0x1c1>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x5b 0x15>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0xab>;
+	};
+
+	avsd-plus@fdb51000 {
+		compatible = "rockchip,avs-plus-decoder";
+		reg = <0x00 0xfdb51000 0x00 0x200>;
+		interrupts = <0x00 0x77 0x04>;
+		interrupt-names = "irq_avsd";
+		clocks = <0x02 0x1c0 0x02 0x1c1>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		resets = <0x02 0x2c8 0x02 0x2c9>;
+		reset-names = "shared_video_a\0shared_video_h";
+		iommus = <0xab>;
+		power-domains = <0x5b 0x15>;
+		rockchip,srv = <0xac>;
+		rockchip,taskqueue-node = <0x00>;
+		rockchip,resetgroup-node = <0x00>;
+		status = "disabled";
+		phandle = <0x216>;
+	};
+
+	rga@fdb60000 {
+		compatible = "rockchip,rga3_core0";
+		reg = <0x00 0xfdb60000 0x00 0x1000>;
+		interrupts = <0x00 0x72 0x04>;
+		interrupt-names = "rga3_core0_irq";
+		clocks = <0x02 0x1ba 0x02 0x1b9 0x02 0x1bb>;
+		clock-names = "aclk_rga3_0\0hclk_rga3_0\0clk_rga3_0";
+		power-domains = <0x5b 0x16>;
+		iommus = <0xad>;
+		status = "okay";
+		phandle = <0x217>;
+	};
+
+	iommu@fdb60f00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdb60f00 0x00 0x100>;
+		interrupts = <0x00 0x72 0x04>;
+		interrupt-names = "rga3_0_mmu";
+		clocks = <0x02 0x1ba 0x02 0x1b9>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x5b 0x16>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0xad>;
+	};
+
+	rga@fdb70000 {
+		compatible = "rockchip,rga3_core1";
+		reg = <0x00 0xfdb70000 0x00 0x1000>;
+		interrupts = <0x00 0x73 0x04>;
+		interrupt-names = "rga3_core1_irq";
+		clocks = <0x02 0x18a 0x02 0x189 0x02 0x18b>;
+		clock-names = "aclk_rga3_1\0hclk_rga3_1\0clk_rga3_1";
+		power-domains = <0x5b 0x1e>;
+		iommus = <0xae>;
+		status = "okay";
+		phandle = <0x218>;
+	};
+
+	iommu@fdb70f00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdb70f00 0x00 0x100>;
+		interrupts = <0x00 0x73 0x04>;
+		interrupt-names = "rga3_1_mmu";
+		clocks = <0x02 0x18a 0x02 0x189>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x5b 0x1e>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0xae>;
+	};
+
+	rga@fdb80000 {
+		compatible = "rockchip,rga2_core0";
+		reg = <0x00 0xfdb80000 0x00 0x1000>;
+		interrupts = <0x00 0x74 0x04>;
+		interrupt-names = "rga2_irq";
+		clocks = <0x02 0x1b7 0x02 0x1b6 0x02 0x1b8>;
+		clock-names = "aclk_rga2\0hclk_rga2\0clk_rga2";
+		power-domains = <0x5b 0x15>;
+		status = "okay";
+		phandle = <0x219>;
+	};
+
+	jpegd@fdb90000 {
+		compatible = "rockchip,rkv-jpeg-decoder-v1";
+		reg = <0x00 0xfdb90000 0x00 0x400>;
+		interrupts = <0x00 0x81 0x04>;
+		interrupt-names = "irq_jpegd";
+		clocks = <0x02 0x1b4 0x02 0x1b5>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		rockchip,normal-rates = <0x23c34600 0x00>;
+		assigned-clocks = <0x02 0x1b4>;
+		assigned-clock-rates = <0x23c34600>;
+		resets = <0x02 0x2d2 0x02 0x2d3>;
+		reset-names = "video_a\0video_h";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xaf>;
+		rockchip,srv = <0xac>;
+		rockchip,taskqueue-node = <0x01>;
+		power-domains = <0x5b 0x15>;
+		status = "okay";
+		phandle = <0x21a>;
+	};
+
+	iommu@fdb90480 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdb90480 0x00 0x40>;
+		interrupts = <0x00 0x82 0x04>;
+		interrupt-names = "irq_jpegd_mmu";
+		clocks = <0x02 0x1b4 0x02 0x1b5>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x5b 0x15>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0xaf>;
+	};
+
+	jpege-core@fdba0000 {
+		compatible = "rockchip,vpu-jpege-core";
+		reg = <0x00 0xfdba0000 0x00 0x400>;
+		interrupts = <0x00 0x7a 0x04>;
+		interrupt-names = "irq_jpege0";
+		clocks = <0x02 0x1ac 0x02 0x1ad>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		rockchip,normal-rates = <0x2367b880 0x00>;
+		assigned-clocks = <0x02 0x1ac>;
+		assigned-clock-rates = <0x2367b880>;
+		resets = <0x02 0x2ca 0x02 0x2cb>;
+		reset-names = "video_a\0video_h";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xb0>;
+		rockchip,srv = <0xac>;
+		rockchip,taskqueue-node = <0x02>;
+		rockchip,ccu = <0xb1>;
+		power-domains = <0x5b 0x15>;
+		status = "okay";
+		phandle = <0x21b>;
+	};
+
+	iommu@fdba0800 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdba0800 0x00 0x40>;
+		interrupts = <0x00 0x79 0x04>;
+		interrupt-names = "irq_jpege0_mmu";
+		clocks = <0x02 0x1ac 0x02 0x1ad>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x5b 0x15>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0xb0>;
+	};
+
+	jpege-core@fdba4000 {
+		compatible = "rockchip,vpu-jpege-core";
+		reg = <0x00 0xfdba4000 0x00 0x400>;
+		interrupts = <0x00 0x7c 0x04>;
+		interrupt-names = "irq_jpege1";
+		clocks = <0x02 0x1ae 0x02 0x1af>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		rockchip,normal-rates = <0x2367b880 0x00>;
+		assigned-clocks = <0x02 0x1ae>;
+		assigned-clock-rates = <0x2367b880>;
+		resets = <0x02 0x2cc 0x02 0x2cd>;
+		reset-names = "video_a\0video_h";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xb2>;
+		rockchip,srv = <0xac>;
+		rockchip,taskqueue-node = <0x02>;
+		rockchip,ccu = <0xb1>;
+		power-domains = <0x5b 0x15>;
+		status = "okay";
+		phandle = <0x21c>;
+	};
+
+	iommu@fdba4800 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdba4800 0x00 0x40>;
+		interrupts = <0x00 0x7b 0x04>;
+		interrupt-names = "irq_jpege1_mmu";
+		clocks = <0x02 0x1ae 0x02 0x1af>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x5b 0x15>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0xb2>;
+	};
+
+	jpege-core@fdba8000 {
+		compatible = "rockchip,vpu-jpege-core";
+		reg = <0x00 0xfdba8000 0x00 0x400>;
+		interrupts = <0x00 0x7e 0x04>;
+		interrupt-names = "irq_jpege2";
+		clocks = <0x02 0x1b0 0x02 0x1b1>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		rockchip,normal-rates = <0x2367b880 0x00>;
+		assigned-clocks = <0x02 0x1b0>;
+		assigned-clock-rates = <0x2367b880>;
+		resets = <0x02 0x2ce 0x02 0x2cf>;
+		reset-names = "video_a\0video_h";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xb3>;
+		rockchip,srv = <0xac>;
+		rockchip,taskqueue-node = <0x02>;
+		rockchip,ccu = <0xb1>;
+		power-domains = <0x5b 0x15>;
+		status = "okay";
+		phandle = <0x21d>;
+	};
+
+	iommu@fdba8800 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdba8800 0x00 0x40>;
+		interrupts = <0x00 0x7d 0x04>;
+		interrupt-names = "irq_jpege2_mmu";
+		clocks = <0x02 0x1b0 0x02 0x1b1>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x5b 0x15>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0xb3>;
+	};
+
+	jpege-core@fdbac000 {
+		compatible = "rockchip,vpu-jpege-core";
+		reg = <0x00 0xfdbac000 0x00 0x400>;
+		interrupts = <0x00 0x80 0x04>;
+		interrupt-names = "irq_jpege3";
+		clocks = <0x02 0x1b2 0x02 0x1b3>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		rockchip,normal-rates = <0x2367b880 0x00>;
+		assigned-clocks = <0x02 0x1b2>;
+		assigned-clock-rates = <0x2367b880>;
+		resets = <0x02 0x2d0 0x02 0x2d1>;
+		reset-names = "video_a\0video_h";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xb4>;
+		rockchip,srv = <0xac>;
+		rockchip,taskqueue-node = <0x02>;
+		rockchip,ccu = <0xb1>;
+		power-domains = <0x5b 0x15>;
+		status = "okay";
+		phandle = <0x21e>;
+	};
+
+	iommu@fdbac800 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdbac800 0x00 0x40>;
+		interrupts = <0x00 0x7f 0x04>;
+		interrupt-names = "irq_jpege3_mmu";
+		clocks = <0x02 0x1b2 0x02 0x1b3>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x5b 0x15>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0xb4>;
+	};
+
+	iep@fdbb0000 {
+		compatible = "rockchip,iep-v2";
+		reg = <0x00 0xfdbb0000 0x00 0x500>;
+		interrupts = <0x00 0x75 0x04>;
+		interrupt-names = "irq_iep";
+		clocks = <0x02 0x1aa 0x02 0x1a9 0x02 0x1ab>;
+		clock-names = "aclk\0hclk\0sclk";
+		resets = <0x02 0x2d5 0x02 0x2d4 0x02 0x2d6>;
+		reset-names = "rst_a\0rst_h\0rst_s";
+		rockchip,skip-pmu-idle-request;
+		power-domains = <0x5b 0x15>;
+		rockchip,srv = <0xac>;
+		rockchip,taskqueue-node = <0x06>;
+		iommus = <0xb5>;
+		status = "okay";
+		phandle = <0x21f>;
+	};
+
+	iommu@fdbb0800 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdbb0800 0x00 0x100>;
+		interrupts = <0x00 0x75 0x04>;
+		interrupt-names = "irq_iep_mmu";
+		clocks = <0x02 0x1aa 0x02 0x1a9>;
+		clock-names = "aclk\0iface";
+		#iommu-cells = <0x00>;
+		power-domains = <0x5b 0x15>;
+		status = "okay";
+		phandle = <0xb5>;
+	};
+
+	rkvenc-core@fdbd0000 {
+		compatible = "rockchip,rkv-encoder-v2-core";
+		reg = <0x00 0xfdbd0000 0x00 0x6000>;
+		interrupts = <0x00 0x65 0x04>;
+		interrupt-names = "irq_rkvenc0";
+		clocks = <0x02 0x1c5 0x02 0x1c4 0x02 0x1c6>;
+		clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core";
+		rockchip,normal-rates = <0x23c34600 0x00 0x2faf0800>;
+		assigned-clocks = <0x02 0x1c5 0x02 0x1c6>;
+		assigned-clock-rates = <0x23c34600 0x2faf0800>;
+		resets = <0x02 0x2f5 0x02 0x2f4 0x02 0x2f6>;
+		reset-names = "video_a\0video_h\0video_core";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xb6>;
+		rockchip,srv = <0xac>;
+		rockchip,ccu = <0xb7>;
+		rockchip,taskqueue-node = <0x07>;
+		rockchip,task-capacity = <0x08>;
+		power-domains = <0x5b 0x10>;
+		status = "okay";
+		phandle = <0x220>;
+	};
+
+	iommu@fdbdf000 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdbdf000 0x00 0x40 0x00 0xfdbdf040 0x00 0x40>;
+		interrupts = <0x00 0x63 0x04 0x00 0x64 0x04>;
+		interrupt-names = "irq_rkvenc0_mmu0\0irq_rkvenc0_mmu1";
+		clocks = <0x02 0x1c5 0x02 0x1c4>;
+		clock-names = "aclk\0iface";
+		rockchip,disable-mmu-reset;
+		rockchip,enable-cmd-retry;
+		rockchip,shootdown-entire;
+		#iommu-cells = <0x00>;
+		power-domains = <0x5b 0x10>;
+		status = "okay";
+		phandle = <0xb6>;
+	};
+
+	rkvenc-core@fdbe0000 {
+		compatible = "rockchip,rkv-encoder-v2-core";
+		reg = <0x00 0xfdbe0000 0x00 0x6000>;
+		interrupts = <0x00 0x68 0x04>;
+		interrupt-names = "irq_rkvenc1";
+		clocks = <0x02 0x1ca 0x02 0x1c9 0x02 0x1cb>;
+		clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core";
+		rockchip,normal-rates = <0x23c34600 0x00 0x2faf0800>;
+		assigned-clocks = <0x02 0x1ca 0x02 0x1cb>;
+		assigned-clock-rates = <0x23c34600 0x2faf0800>;
+		resets = <0x02 0x305 0x02 0x304 0x02 0x306>;
+		reset-names = "video_a\0video_h\0video_core";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xb8>;
+		rockchip,srv = <0xac>;
+		rockchip,ccu = <0xb7>;
+		rockchip,taskqueue-node = <0x07>;
+		rockchip,task-capacity = <0x08>;
+		power-domains = <0x5b 0x11>;
+		status = "okay";
+		phandle = <0x221>;
+	};
+
+	iommu@fdbef000 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdbef000 0x00 0x40 0x00 0xfdbef040 0x00 0x40>;
+		interrupts = <0x00 0x66 0x04 0x00 0x67 0x04>;
+		interrupt-names = "irq_rkvenc1_mmu0\0irq_rkvenc1_mmu1";
+		clocks = <0x02 0x1ca 0x02 0x1c9>;
+		lock-names = "aclk\0iface";
+		rockchip,disable-mmu-reset;
+		rockchip,enable-cmd-retry;
+		rockchip,shootdown-entire;
+		#iommu-cells = <0x00>;
+		power-domains = <0x5b 0x11>;
+		status = "okay";
+		phandle = <0xb8>;
+	};
+
+	rkvdec-ccu@fdc30000 {
+		compatible = "rockchip,rkv-decoder-v2-ccu";
+		reg = <0x00 0xfdc30000 0x00 0x100>;
+		reg-names = "ccu";
+		clocks = <0x02 0x18e>;
+		clock-names = "aclk_ccu";
+		assigned-clocks = <0x02 0x18e>;
+		assigned-clock-rates = <0x23c34600>;
+		resets = <0x02 0x282>;
+		reset-names = "video_ccu";
+		rockchip,skip-pmu-idle-request;
+		power-domains = <0x5b 0x0e>;
+		status = "okay";
+		phandle = <0xba>;
+	};
+
+	rkvdec-core@fdc38000 {
+		compatible = "rockchip,rkv-decoder-v2";
+		reg = <0x00 0xfdc38100 0x00 0x400 0x00 0xfdc38000 0x00 0x100>;
+		reg-names = "regs\0link";
+		interrupts = <0x00 0x5f 0x04>;
+		interrupt-names = "irq_rkvdec0";
+		clocks = <0x02 0x190 0x02 0x18f 0x02 0x193 0x02 0x191 0x02 0x192>;
+		clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core\0clk_cabac\0clk_hevc_cabac";
+		rockchip,normal-rates = <0x2faf0800 0x00 0x23c34600 0x23c34600 0x3b9aca00>;
+		assigned-clocks = <0x02 0x190 0x02 0x193 0x02 0x191 0x02 0x192>;
+		assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>;
+		resets = <0x02 0x284 0x02 0x283 0x02 0x289 0x02 0x287 0x02 0x288>;
+		reset-names = "video_a\0video_h\0video_core\0video_cabac\0video_hevc_cabac";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xb9>;
+		rockchip,srv = <0xac>;
+		rockchip,ccu = <0xba>;
+		rockchip,core-mask = <0x10001>;
+		rockchip,taskqueue-node = <0x09>;
+		rockchip,sram = <0xbb>;
+		rockchip,rcb-iova = <0xfff00000 0x100000>;
+		rockchip,rcb-min-width = <0x200>;
+		power-domains = <0x5b 0x0e>;
+		status = "okay";
+		phandle = <0x222>;
+	};
+
+	iommu@fdc38700 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdc38700 0x00 0x40 0x00 0xfdc38740 0x00 0x40>;
+		interrupts = <0x00 0x60 0x04>;
+		interrupt-names = "irq_rkvdec0_mmu";
+		clocks = <0x02 0x190 0x02 0x18f>;
+		clock-names = "aclk\0iface";
+		rockchip,disable-mmu-reset;
+		rockchip,enable-cmd-retry;
+		rockchip,shootdown-entire;
+		rockchip,master-handle-irq;
+		#iommu-cells = <0x00>;
+		power-domains = <0x5b 0x0e>;
+		status = "okay";
+		phandle = <0xb9>;
+	};
+
+	rkvdec-core@fdc48000 {
+		compatible = "rockchip,rkv-decoder-v2";
+		reg = <0x00 0xfdc48100 0x00 0x400 0x00 0xfdc48000 0x00 0x100>;
+		reg-names = "regs\0link";
+		interrupts = <0x00 0x61 0x04>;
+		interrupt-names = "irq_rkvdec1";
+		clocks = <0x02 0x195 0x02 0x194 0x02 0x198 0x02 0x196 0x02 0x197>;
+		clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core\0clk_cabac\0clk_hevc_cabac";
+		rockchip,normal-rates = <0x2faf0800 0x00 0x23c34600 0x23c34600 0x3b9aca00>;
+		assigned-clocks = <0x02 0x195 0x02 0x198 0x02 0x196 0x02 0x197>;
+		assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>;
+		resets = <0x02 0x293 0x02 0x292 0x02 0x298 0x02 0x296 0x02 0x297>;
+		reset-names = "video_a\0video_h\0video_core\0video_cabac\0video_hevc_cabac";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xbc>;
+		rockchip,srv = <0xac>;
+		rockchip,ccu = <0xba>;
+		rockchip,core-mask = <0x20002>;
+		rockchip,taskqueue-node = <0x09>;
+		rockchip,sram = <0xbd>;
+		rockchip,rcb-iova = <0xffe00000 0x100000>;
+		rockchip,rcb-min-width = <0x200>;
+		power-domains = <0x5b 0x0f>;
+		status = "okay";
+		phandle = <0x223>;
+	};
+
+	iommu@fdc48700 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdc48700 0x00 0x40 0x00 0xfdc48740 0x00 0x40>;
+		interrupts = <0x00 0x62 0x04>;
+		interrupt-names = "irq_rkvdec1_mmu";
+		clocks = <0x02 0x195 0x02 0x194>;
+		clock-names = "aclk\0iface";
+		rockchip,disable-mmu-reset;
+		rockchip,enable-cmd-retry;
+		rockchip,shootdown-entire;
+		rockchip,master-handle-irq;
+		#iommu-cells = <0x00>;
+		power-domains = <0x5b 0x0f>;
+		status = "okay";
+		phandle = <0xbc>;
+	};
+
+	av1d@fdc70000 {
+		compatible = "rockchip,av1-decoder";
+		reg = <0x00 0xfdc70000 0x00 0x800 0x00 0xfdc80000 0x00 0x400 0x00 0xfdc90000 0x00 0x400>;
+		reg-names = "vcd\0cache\0afbc";
+		interrupts = <0x00 0x6c 0x04 0x00 0x6b 0x04 0x00 0x6a 0x04>;
+		interrupt-names = "irq_av1d\0irq_cache\0irq_afbc";
+		clocks = <0x02 0x49 0x02 0x4b>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		rockchip,normal-rates = <0x17d78400 0x17d78400>;
+		assigned-clocks = <0x02 0x49 0x02 0x4b>;
+		assigned-clock-rates = <0x17d78400 0x17d78400>;
+		resets = <0x02 0x442 0x02 0x445>;
+		reset-names = "video_a\0video_h";
+		iommus = <0xbe>;
+		rockchip,srv = <0xac>;
+		rockchip,taskqueue-node = <0x0b>;
+		power-domains = <0x5b 0x17>;
+		status = "okay";
+		phandle = <0x224>;
+	};
+
+	iommu@fdca0000 {
+		compatible = "rockchip,iommu-av1";
+		reg = <0x00 0xfdca0000 0x00 0x600>;
+		interrupts = <0x00 0x6d 0x04>;
+		interrupt-names = "irq_av1d_mmu";
+		clocks = <0x02 0x49 0x02 0x4b>;
+		clock-names = "aclk\0iface";
+		#iommu-cells = <0x00>;
+		power-domains = <0x5b 0x17>;
+		status = "okay";
+		phandle = <0xbe>;
+	};
+
+	rkisp-unite@fdcb0000 {
+		compatible = "rockchip,rk3588-rkisp-unite";
+		reg = <0x00 0xfdcb0000 0x00 0x10000 0x00 0xfdcc0000 0x00 0x10000>;
+		interrupts = <0x00 0x87 0x04 0x00 0x89 0x04 0x00 0x8a 0x04>;
+		interrupt-names = "isp_irq\0mi_irq\0mipi_irq";
+		clocks = <0x02 0x1de 0x02 0x1df 0x02 0x1db 0x02 0x1dc 0x02 0x1dd 0x02 0x120 0x02 0x121 0x02 0x11d 0x02 0x11e 0x02 0x11f>;
+		clock-names = "aclk_isp0\0hclk_isp0\0clk_isp_core0\0clk_isp_core_marvin0\0clk_isp_core_vicap0\0aclk_isp1\0hclk_isp1\0clk_isp_core1\0clk_isp_core_marvin1\0clk_isp_core_vicap1";
+		power-domains = <0x5b 0x1c>;
+		iommus = <0xbf>;
+		status = "disabled";
+		phandle = <0x225>;
+	};
+
+	rkisp@fdcb0000 {
+		compatible = "rockchip,rk3588-rkisp";
+		reg = <0x00 0xfdcb0000 0x00 0x7f00>;
+		interrupts = <0x00 0x83 0x04 0x00 0x85 0x04 0x00 0x86 0x04>;
+		interrupt-names = "isp_irq\0mi_irq\0mipi_irq";
+		clocks = <0x02 0x1de 0x02 0x1df 0x02 0x1db 0x02 0x1dc 0x02 0x1dd>;
+		clock-names = "aclk_isp\0hclk_isp\0clk_isp_core\0clk_isp_core_marvin\0clk_isp_core_vicap";
+		power-domains = <0x5b 0x1b>;
+		iommus = <0xc0>;
+		status = "okay";
+		phandle = <0x51>;
+	};
+
+	rkisp-unite-mmu@fdcb7f00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdcb7f00 0x00 0x100 0x00 0xfdcc7f00 0x00 0x100>;
+		interrupts = <0x00 0x84 0x04 0x00 0x88 0x04>;
+		interrupt-names = "isp0_mmu\0isp1_mmu";
+		clocks = <0x02 0x1de 0x02 0x1df 0x02 0x120 0x02 0x121>;
+		clock-names = "aclk0\0iface0\0aclk1\0iface1";
+		power-domains = <0x5b 0x1c>;
+		#iommu-cells = <0x00>;
+		rockchip,disable-mmu-reset;
+		status = "disabled";
+		phandle = <0xbf>;
+	};
+
+	iommu@fdcb7f00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdcb7f00 0x00 0x100>;
+		interrupts = <0x00 0x84 0x04>;
+		interrupt-names = "isp0_mmu";
+		clocks = <0x02 0x1de 0x02 0x1df>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x5b 0x1b>;
+		#iommu-cells = <0x00>;
+		rockchip,disable-mmu-reset;
+		status = "okay";
+		phandle = <0xc0>;
+	};
+
+	rkisp@fdcc0000 {
+		compatible = "rockchip,rk3588-rkisp";
+		reg = <0x00 0xfdcc0000 0x00 0x7f00>;
+		interrupts = <0x00 0x87 0x04 0x00 0x89 0x04 0x00 0x8a 0x04>;
+		interrupt-names = "isp_irq\0mi_irq\0mipi_irq";
+		clocks = <0x02 0x120 0x02 0x121 0x02 0x11d 0x02 0x11e 0x02 0x11f>;
+		clock-names = "aclk_isp\0hclk_isp\0clk_isp_core\0clk_isp_core_marvin\0clk_isp_core_vicap";
+		power-domains = <0x5b 0x1c>;
+		iommus = <0xc1>;
+		status = "okay";
+		phandle = <0x54>;
+	};
+
+	iommu@fdcc7f00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdcc7f00 0x00 0x100>;
+		interrupts = <0x00 0x88 0x04>;
+		interrupt-names = "isp1_mmu";
+		clocks = <0x02 0x120 0x02 0x121>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x5b 0x1c>;
+		#iommu-cells = <0x00>;
+		rockchip,disable-mmu-reset;
+		status = "okay";
+		phandle = <0xc1>;
+	};
+
+	rkispp@fdcd0000 {
+		compatible = "rockchip,rk3588-rkispp";
+		reg = <0x00 0xfdcd0000 0x00 0xf00>;
+		interrupts = <0x00 0x8b 0x04>;
+		interrupt-names = "fec_irq";
+		clocks = <0x02 0x1d5 0x02 0x1d6 0x02 0x1d7>;
+		clock-names = "aclk_ispp\0hclk_ispp\0clk_ispp";
+		power-domains = <0x5b 0x1d>;
+		iommus = <0xc2>;
+		status = "disabled";
+		phandle = <0x56>;
+	};
+
+	iommu@fdcd0f00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdcd0f00 0x00 0x100>;
+		interrupts = <0x00 0x8c 0x04>;
+		interrupt-names = "fec0_mmu";
+		clocks = <0x02 0x1d5 0x02 0x1d6 0x02 0x1d7>;
+		clock-names = "aclk\0iface\0pclk";
+		power-domains = <0x5b 0x1d>;
+		#iommu-cells = <0x00>;
+		rockchip,disable-mmu-reset;
+		status = "disabled";
+		phandle = <0xc2>;
+	};
+
+	rkispp@fdcd8000 {
+		compatible = "rockchip,rk3588-rkispp";
+		reg = <0x00 0xfdcd8000 0x00 0xf00>;
+		interrupts = <0x00 0x8d 0x04>;
+		interrupt-names = "fec_irq";
+		clocks = <0x02 0x1d8 0x02 0x1d9 0x02 0x1da>;
+		clock-names = "aclk_ispp\0hclk_ispp\0clk_ispp";
+		power-domains = <0x5b 0x1d>;
+		iommus = <0xc3>;
+		status = "disabled";
+		phandle = <0x57>;
+	};
+
+	iommu@fdcd8f00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdcd8f00 0x00 0x100>;
+		interrupts = <0x00 0x8e 0x04>;
+		interrupt-names = "fec1_mmu";
+		clocks = <0x02 0x1d8 0x02 0x1d9 0x02 0x1da>;
+		clock-names = "aclk\0iface\0pclk";
+		power-domains = <0x5b 0x1d>;
+		#iommu-cells = <0x00>;
+		rockchip,disable-mmu-reset;
+		status = "disabled";
+		phandle = <0xc3>;
+	};
+
+	rkcif@fdce0000 {
+		compatible = "rockchip,rk3588-cif";
+		reg = <0x00 0xfdce0000 0x00 0x800>;
+		reg-names = "cif_regs";
+		interrupts = <0x00 0x9b 0x04>;
+		interrupt-names = "cif-intr";
+		clocks = <0x02 0x1e4 0x02 0x1e5 0x02 0x1e3>;
+		clock-names = "aclk_cif\0hclk_cif\0dclk_cif";
+		resets = <0x02 0x317 0x02 0x318 0x02 0x316>;
+		reset-names = "rst_cif_a\0rst_cif_h\0rst_cif_d";
+		assigned-clocks = <0x02 0x1e3>;
+		assigned-clock-rates = <0x23c34600>;
+		power-domains = <0x5b 0x1b>;
+		rockchip,grf = <0xc4>;
+		iommus = <0x45>;
+		status = "okay";
+		phandle = <0x44>;
+	};
+
+	iommu@fdce0800 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdce0800 0x00 0x100 0x00 0xfdce0900 0x00 0x100>;
+		interrupts = <0x00 0x71 0x04>;
+		interrupt-names = "cif_mmu";
+		clocks = <0x02 0x1e4 0x02 0x1e5>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x5b 0x1b>;
+		rockchip,disable-mmu-reset;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0x45>;
+	};
+
+	mipi0-csi2@fdd10000 {
+		compatible = "rockchip,rk3588-mipi-csi2";
+		reg = <0x00 0xfdd10000 0x00 0x10000>;
+		reg-names = "csihost_regs";
+		interrupts = <0x00 0x8f 0x04 0x00 0x90 0x04>;
+		interrupt-names = "csi-intr1\0csi-intr2";
+		clocks = <0x02 0x1cf 0x02 0x1cd>;
+		clock-names = "pclk_csi2host\0iclk_csi2host";
+		resets = <0x02 0x324 0x02 0x334>;
+		reset-names = "srst_csihost_p\0srst_csihost_vicap";
+		status = "disabled";
+		phandle = <0x226>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xc5>;
+					phandle = <0x2c>;
+				};
+			};
+
+			port@1 {
+				reg = <0x01>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xc6>;
+					phandle = <0x47>;
+				};
+			};
+		};
+	};
+
+	mipi1-csi2@fdd20000 {
+		compatible = "rockchip,rk3588-mipi-csi2";
+		reg = <0x00 0xfdd20000 0x00 0x10000>;
+		reg-names = "csihost_regs";
+		interrupts = <0x00 0x91 0x04 0x00 0x92 0x04>;
+		interrupt-names = "csi-intr1\0csi-intr2";
+		clocks = <0x02 0x1d0 0x02 0x1ce>;
+		clock-names = "pclk_csi2host\0iclk_csi2host";
+		resets = <0x02 0x325 0x02 0x335>;
+		reset-names = "srst_csihost_p\0srst_csihost_vicap";
+		status = "disabled";
+		phandle = <0x227>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xc7>;
+					phandle = <0x30>;
+				};
+			};
+
+			port@1 {
+				reg = <0x01>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xc8>;
+					phandle = <0x4a>;
+				};
+			};
+		};
+	};
+
+	mipi2-csi2@fdd30000 {
+		compatible = "rockchip,rk3588-mipi-csi2";
+		reg = <0x00 0xfdd30000 0x00 0x10000>;
+		reg-names = "csihost_regs";
+		interrupts = <0x00 0x93 0x04 0x00 0x94 0x04>;
+		interrupt-names = "csi-intr1\0csi-intr2";
+		clocks = <0x02 0x1d1>;
+		clock-names = "pclk_csi2host";
+		resets = <0x02 0x326 0x02 0x336>;
+		reset-names = "srst_csihost_p\0srst_csihost_vicap";
+		status = "disabled";
+		phandle = <0x228>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xc9>;
+					phandle = <0x34>;
+				};
+			};
+
+			port@1 {
+				reg = <0x01>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xca>;
+					phandle = <0x4d>;
+				};
+			};
+		};
+	};
+
+	mipi3-csi2@fdd40000 {
+		compatible = "rockchip,rk3588-mipi-csi2";
+		reg = <0x00 0xfdd40000 0x00 0x10000>;
+		reg-names = "csihost_regs";
+		interrupts = <0x00 0x95 0x04 0x00 0x96 0x04>;
+		interrupt-names = "csi-intr1\0csi-intr2";
+		clocks = <0x02 0x1d2>;
+		clock-names = "pclk_csi2host";
+		resets = <0x02 0x327 0x02 0x337>;
+		reset-names = "srst_csihost_p\0srst_csihost_vicap";
+		status = "disabled";
+		phandle = <0x229>;
+	};
+
+	vop@fdd90000 {
+		compatible = "rockchip,rk3588-vop";
+		reg = <0x00 0xfdd90000 0x00 0x4200 0x00 0xfdd95000 0x00 0x1000>;
+		reg-names = "regs\0gamma_lut";
+		interrupts = <0x00 0x9c 0x04>;
+		clocks = <0x02 0x270 0x02 0x26f 0x02 0x274 0x02 0x275 0x02 0x276 0x02 0x277 0x02 0x26e 0x02 0x271 0x02 0x272 0x02 0x273>;
+		clock-names = "aclk_vop\0hclk_vop\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0pclk_vop\0dclk_src_vp0\0dclk_src_vp1\0dclk_src_vp2";
+		assigned-clocks = <0x02 0x270>;
+		assigned-clock-rates = <0x2faf0800>;
+		resets = <0x02 0x349 0x02 0x348 0x02 0x34d 0x02 0x350 0x02 0x351 0x02 0x352>;
+		reset-names = "axi\0ahb\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3";
+		iommus = <0xcb>;
+		power-domains = <0x5b 0x18>;
+		rockchip,grf = <0xc4>;
+		rockchip,vop-grf = <0xcc>;
+		rockchip,vo1-grf = <0xcd>;
+		rockchip,pmu = <0xce>;
+		status = "okay";
+		disable-win-move;
+		phandle = <0x22a>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			phandle = <0x35>;
+
+			port@0 {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				reg = <0x00>;
+				cursor-win-id = <0x02>;
+				rockchip,plane-mask = <0x05>;
+				rockchip,primary-plane = <0x00>;
+				phandle = <0x22b>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xcf>;
+					phandle = <0xec>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xd0>;
+					phandle = <0xf7>;
+				};
+
+				endpoint@2 {
+					reg = <0x02>;
+					remote-endpoint = <0xd1>;
+					phandle = <0x3c>;
+				};
+			};
+
+			port@1 {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				reg = <0x01>;
+				cursor-win-id = <0x03>;
+				rockchip,plane-mask = <0x0a>;
+				rockchip,primary-plane = <0x01>;
+				phandle = <0x22c>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xd2>;
+					phandle = <0x38>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xd3>;
+					phandle = <0xf8>;
+				};
+
+				endpoint@2 {
+					reg = <0x02>;
+					remote-endpoint = <0xd4>;
+					phandle = <0xf4>;
+				};
+			};
+
+			port@2 {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				reg = <0x02>;
+				assigned-clocks = <0x02 0x273>;
+				assigned-clock-parents = <0x02 0x04>;
+				cursor-win-id = <0x08>;
+				rockchip,plane-mask = <0x140>;
+				rockchip,primary-plane = <0x06>;
+				phandle = <0x22d>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xd5>;
+					phandle = <0xed>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xd6>;
+					phandle = <0x3b>;
+				};
+
+				endpoint@2 {
+					reg = <0x02>;
+					remote-endpoint = <0xd7>;
+					phandle = <0xf5>;
+				};
+
+				endpoint@3 {
+					reg = <0x03>;
+					remote-endpoint = <0xd8>;
+					phandle = <0xdf>;
+				};
+
+				endpoint@4 {
+					reg = <0x04>;
+					remote-endpoint = <0xd9>;
+					phandle = <0xe5>;
+				};
+			};
+
+			port@3 {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				reg = <0x03>;
+				cursor-win-id = <0x09>;
+				rockchip,plane-mask = <0x280>;
+				rockchip,primary-plane = <0x07>;
+				phandle = <0x22e>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xda>;
+					phandle = <0x39>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xdb>;
+					phandle = <0x3a>;
+				};
+
+				endpoint@2 {
+					reg = <0x02>;
+					remote-endpoint = <0xdc>;
+					phandle = <0x3d>;
+				};
+			};
+		};
+	};
+
+	iommu@fdd97e00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdd97e00 0x00 0x100 0x00 0xfdd97f00 0x00 0x100>;
+		interrupts = <0x00 0x9c 0x04>;
+		interrupt-names = "vop_mmu";
+		clocks = <0x02 0x270 0x02 0x26f>;
+		clock-names = "aclk\0iface";
+		#iommu-cells = <0x00>;
+		rockchip,disable-device-link-resume;
+		rockchip,shootdown-entire;
+		status = "okay";
+		phandle = <0xcb>;
+	};
+
+	spdif-tx@fddb0000 {
+		compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif";
+		reg = <0x00 0xfddb0000 0x00 0x1000>;
+		interrupts = <0x00 0xc3 0x04>;
+		dmas = <0xdd 0x06>;
+		dma-names = "tx";
+		clock-names = "mclk\0hclk";
+		clocks = <0x02 0x209 0x02 0x204>;
+		assigned-clocks = <0x02 0x205>;
+		assigned-clock-parents = <0x02 0x05>;
+		power-domains = <0x5b 0x19>;
+		#sound-dai-cells = <0x00>;
+		status = "okay";
+		phandle = <0x19a>;
+	};
+
+	i2s@fddc0000 {
+		compatible = "rockchip,rk3588-i2s-tdm";
+		reg = <0x00 0xfddc0000 0x00 0x1000>;
+		interrupts = <0x00 0xb8 0x04>;
+		clocks = <0x02 0x1fb 0x02 0x1fb 0x02 0x1f0>;
+		clock-names = "mclk_tx\0mclk_rx\0hclk";
+		assigned-clocks = <0x02 0x1f9>;
+		assigned-clock-parents = <0x02 0x05>;
+		dmas = <0xde 0x00>;
+		dma-names = "tx";
+		power-domains = <0x5b 0x19>;
+		resets = <0x02 0x38d>;
+		reset-names = "tx-m";
+		rockchip,playback-only;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x22f>;
+	};
+
+	spdif-tx@fdde0000 {
+		compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif";
+		reg = <0x00 0xfdde0000 0x00 0x1000>;
+		interrupts = <0x00 0xc4 0x04>;
+		dmas = <0xdd 0x07>;
+		dma-names = "tx";
+		clock-names = "mclk\0hclk";
+		clocks = <0x02 0x257 0x02 0x253>;
+		assigned-clocks = <0x02 0x254>;
+		assigned-clock-parents = <0x02 0x05>;
+		power-domains = <0x5b 0x1a>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x230>;
+	};
+
+	i2s@fddf0000 {
+		compatible = "rockchip,rk3588-i2s-tdm";
+		reg = <0x00 0xfddf0000 0x00 0x1000>;
+		interrupts = <0x00 0xb9 0x04>;
+		clocks = <0x02 0x246 0x02 0x246 0x02 0x248>;
+		clock-names = "mclk_tx\0mclk_rx\0hclk";
+		assigned-clocks = <0x02 0x243>;
+		assigned-clock-parents = <0x02 0x05>;
+		dmas = <0xde 0x02>;
+		dma-names = "tx";
+		power-domains = <0x5b 0x1a>;
+		resets = <0x02 0x3e8>;
+		reset-names = "tx-m";
+		rockchip,always-on;
+		rockchip,hdmi-path;
+		rockchip,playback-only;
+		#sound-dai-cells = <0x00>;
+		status = "okay";
+		phandle = <0x19c>;
+	};
+
+	i2s@fddfc000 {
+		compatible = "rockchip,rk3588-i2s-tdm";
+		reg = <0x00 0xfddfc000 0x00 0x1000>;
+		interrupts = <0x00 0xbd 0x04>;
+		clocks = <0x02 0x242 0x02 0x242 0x02 0x23e>;
+		clock-names = "mclk_tx\0mclk_rx\0hclk";
+		assigned-clocks = <0x02 0x23f>;
+		assigned-clock-parents = <0x02 0x05>;
+		dmas = <0xde 0x17>;
+		dma-names = "rx";
+		power-domains = <0x5b 0x1a>;
+		resets = <0x02 0x413>;
+		reset-names = "rx-m";
+		rockchip,capture-only;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x231>;
+	};
+
+	spdif-rx@fde08000 {
+		compatible = "rockchip,rk3588-spdifrx\0rockchip,rk3308-spdifrx";
+		reg = <0x00 0xfde08000 0x00 0x1000>;
+		interrupts = <0x00 0xc7 0x04>;
+		clocks = <0x02 0x25e 0x02 0x25d>;
+		clock-names = "mclk\0hclk";
+		assigned-clocks = <0x02 0x25e>;
+		assigned-clock-parents = <0x02 0x05>;
+		dmas = <0x71 0x15>;
+		dma-names = "rx";
+		power-domains = <0x5b 0x1a>;
+		resets = <0x02 0x3fd>;
+		reset-names = "spdifrx-m";
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x232>;
+	};
+
+	dsi@fde20000 {
+		compatible = "rockchip,rk3588-mipi-dsi2";
+		reg = <0x00 0xfde20000 0x00 0x10000>;
+		interrupts = <0x00 0xa7 0x04>;
+		clocks = <0x02 0x278 0x02 0x27a>;
+		clock-names = "pclk\0sys_clk";
+		resets = <0x02 0x354>;
+		reset-names = "apb";
+		power-domains = <0x5b 0x18>;
+		phys = <0x29>;
+		phy-names = "dcphy";
+		rockchip,grf = <0xcc>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x233>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				phandle = <0x234>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xdf>;
+					status = "disabled";
+					phandle = <0xd8>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0x39>;
+					status = "disabled";
+					phandle = <0xda>;
+				};
+			};
+
+			port@1 {
+				reg = <0x01>;
+
+				endpoint {
+					remote-endpoint = <0xe0>;
+					phandle = <0xe4>;
+				};
+			};
+		};
+
+		panel@0 {
+			status = "disabled";
+			compatible = "innolux,afj101-ba2131";
+			reg = <0x00>;
+			backlight = <0xe1>;
+			reset-gpios = <0xe2 0x09 0x01>;
+			enable-gpios = <0xe2 0x00 0x00>;
+			pinctrl-names = "default";
+			pinctrl-0 = <0xe3>;
+			phandle = <0x235>;
+
+			ports {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				port@0 {
+					reg = <0x00>;
+
+					endpoint {
+						remote-endpoint = <0xe4>;
+						phandle = <0xe0>;
+					};
+				};
+			};
+		};
+	};
+
+	dsi@fde30000 {
+		compatible = "rockchip,rk3588-mipi-dsi2";
+		reg = <0x00 0xfde30000 0x00 0x10000>;
+		interrupts = <0x00 0xa8 0x04>;
+		clocks = <0x02 0x279 0x02 0x27b>;
+		clock-names = "pclk\0sys_clk";
+		resets = <0x02 0x355>;
+		reset-names = "apb";
+		power-domains = <0x5b 0x18>;
+		phys = <0x2d>;
+		phy-names = "dcphy";
+		rockchip,grf = <0xcc>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x236>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				phandle = <0x237>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xe5>;
+					status = "disabled";
+					phandle = <0xd9>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0x3a>;
+					status = "disabled";
+					phandle = <0xdb>;
+				};
+			};
+
+			port@1 {
+				reg = <0x01>;
+
+				endpoint {
+					remote-endpoint = <0xe6>;
+					phandle = <0xe9>;
+				};
+			};
+		};
+
+		panel@0 {
+			status = "disabled";
+			compatible = "innolux,afj101-ba2131";
+			reg = <0x00>;
+			backlight = <0xe7>;
+			reset-gpios = <0xe2 0x0b 0x01>;
+			enable-gpios = <0xe2 0x01 0x00>;
+			pinctrl-names = "default";
+			pinctrl-0 = <0xe8>;
+			phandle = <0x238>;
+
+			ports {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				port@0 {
+					reg = <0x00>;
+
+					endpoint {
+						remote-endpoint = <0xe9>;
+						phandle = <0xe6>;
+					};
+				};
+			};
+		};
+	};
+
+	hdcp@fde40000 {
+		compatible = "rockchip,rk3588-hdcp";
+		reg = <0x00 0xfde40000 0x00 0x80>;
+		interrupts = <0x00 0x9f 0x04>;
+		clocks = <0x02 0x1ed 0x02 0x1ef 0x02 0x1ee 0x02 0x1ec 0x02 0x1f1 0x02 0x1f2>;
+		clock-names = "aclk\0pclk\0hclk\0hclk_key\0aclk_trng\0pclk_trng";
+		resets = <0x02 0x37f 0x02 0x37d 0x02 0x37c 0x02 0x37b 0x02 0x381>;
+		reset-names = "hdcp\0h_hdcp\0a_hdcp\0hdcp_key\0trng";
+		power-domains = <0x5b 0x19>;
+		rockchip,vo-grf = <0xea>;
+		status = "disabled";
+		phandle = <0x239>;
+	};
+
+	dp@fde50000 {
+		compatible = "rockchip,rk3588-dp";
+		reg = <0x00 0xfde50000 0x00 0x4000>;
+		interrupts = <0x00 0xa1 0x04>;
+		clocks = <0x02 0x1e6 0x02 0x2cc 0x02 0x1fb 0x02 0x207 0x04>;
+		clock-names = "apb\0aux\0i2s\0spdif\0hclk";
+		assigned-clocks = <0x02 0x2cc>;
+		assigned-clock-rates = <0xf42400>;
+		resets = <0x02 0x388>;
+		phys = <0xeb>;
+		power-domains = <0x5b 0x19>;
+		#sound-dai-cells = <0x01>;
+		status = "okay";
+		phandle = <0x19b>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				phandle = <0x23a>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xec>;
+					status = "disabled";
+					phandle = <0xcf>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0x38>;
+					status = "okay";
+					phandle = <0xd2>;
+				};
+
+				endpoint@2 {
+					reg = <0x02>;
+					remote-endpoint = <0xed>;
+					status = "disabled";
+					phandle = <0xd5>;
+				};
+			};
+		};
+	};
+
+	hdcp@fde70000 {
+		compatible = "rockchip,rk3588-hdcp";
+		reg = <0x00 0xfde70000 0x00 0x80>;
+		interrupts = <0x00 0xa0 0x04>;
+		clocks = <0x02 0x217 0x02 0x219 0x02 0x218 0x02 0x216 0x02 0x228 0x02 0x229>;
+		clock-names = "aclk\0pclk\0hclk\0hclk_key\0aclk_trng\0pclk_trng";
+		resets = <0x02 0x3c8 0x02 0x3c6 0x02 0x3c5 0x02 0x3c4 0x02 0x3ca>;
+		reset-names = "hdcp\0h_hdcp\0a_hdcp\0hdcp_key\0trng";
+		power-domains = <0x5b 0x1a>;
+		rockchip,vo-grf = <0xcd>;
+		status = "disabled";
+		phandle = <0x23b>;
+	};
+
+	hdmi@fde80000 {
+		compatible = "rockchip,rk3588-dw-hdmi";
+		reg = <0x00 0xfde80000 0x00 0x20000>;
+		interrupts = <0x00 0xa9 0x04 0x00 0xaa 0x04 0x00 0xab 0x04 0x00 0xac 0x04 0x00 0x168 0x04>;
+		clocks = <0x02 0x221 0x02 0x265 0x02 0x222 0x02 0x223 0x02 0x246 0x02 0x274 0x02 0x275 0x02 0x276 0x02 0x277 0x05 0x36>;
+		clock-names = "pclk\0hpd\0earc\0hdmitx_ref\0aud\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0hclk_vo1\0link_clk";
+		resets = <0x02 0x3d0 0x02 0x49c>;
+		reset-names = "ref\0hdp";
+		power-domains = <0x5b 0x1a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0xee 0xef 0xf0 0xf1>;
+		reg-io-width = <0x04>;
+		rockchip,grf = <0xc4>;
+		rockchip,vo1_grf = <0xcd>;
+		phys = <0xf2>;
+		phy-names = "hdmi";
+		#sound-dai-cells = <0x00>;
+		status = "okay";
+		enable-gpios = <0xf3 0x0e 0x00>;
+		cec-enable;
+		phandle = <0x19d>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				phandle = <0x23c>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0x3c>;
+					status = "okay";
+					phandle = <0xd1>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xf4>;
+					status = "disabled";
+					phandle = <0xd4>;
+				};
+
+				endpoint@2 {
+					reg = <0x02>;
+					remote-endpoint = <0xf5>;
+					status = "disabled";
+					phandle = <0xd7>;
+				};
+			};
+		};
+	};
+
+	edp@fdec0000 {
+		compatible = "rockchip,rk3588-edp";
+		reg = <0x00 0xfdec0000 0x00 0x1000>;
+		interrupts = <0x00 0xa3 0x04>;
+		clocks = <0x02 0x211 0x02 0x210 0x02 0x212 0x05>;
+		clock-names = "dp\0pclk\0spdif\0hclk";
+		resets = <0x02 0x3e1 0x02 0x3e0>;
+		reset-names = "dp\0apb";
+		phys = <0xf6>;
+		phy-names = "dp";
+		power-domains = <0x5b 0x1a>;
+		rockchip,grf = <0xcd>;
+		status = "disabled";
+		phandle = <0x23d>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				phandle = <0x23e>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xf7>;
+					status = "disabled";
+					phandle = <0xd0>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xf8>;
+					status = "disabled";
+					phandle = <0xd3>;
+				};
+
+				endpoint@2 {
+					reg = <0x02>;
+					remote-endpoint = <0x3b>;
+					status = "disabled";
+					phandle = <0xd6>;
+				};
+			};
+		};
+	};
+
+	qos@fdf35000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf35000 0x00 0x20>;
+		phandle = <0x7c>;
+	};
+
+	qos@fdf35200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf35200 0x00 0x20>;
+		phandle = <0x7d>;
+	};
+
+	qos@fdf35400 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf35400 0x00 0x20>;
+		phandle = <0x7e>;
+	};
+
+	qos@fdf35600 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf35600 0x00 0x20>;
+		phandle = <0x7f>;
+	};
+
+	qos@fdf36000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf36000 0x00 0x20>;
+		phandle = <0x9f>;
+	};
+
+	qos@fdf39000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf39000 0x00 0x20>;
+		phandle = <0xa4>;
+	};
+
+	qos@fdf3d800 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf3d800 0x00 0x20>;
+		phandle = <0xa5>;
+	};
+
+	qos@fdf3e000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf3e000 0x00 0x20>;
+		phandle = <0xa1>;
+	};
+
+	qos@fdf3e200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf3e200 0x00 0x20>;
+		phandle = <0xa0>;
+	};
+
+	qos@fdf3e400 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf3e400 0x00 0x20>;
+		phandle = <0xa2>;
+	};
+
+	qos@fdf3e600 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf3e600 0x00 0x20>;
+		phandle = <0xa3>;
+	};
+
+	qos@fdf40000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf40000 0x00 0x20>;
+		phandle = <0x9d>;
+	};
+
+	qos@fdf40200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf40200 0x00 0x20>;
+		phandle = <0x9e>;
+	};
+
+	qos@fdf40400 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf40400 0x00 0x20>;
+		phandle = <0x97>;
+	};
+
+	qos@fdf40500 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf40500 0x00 0x20>;
+		phandle = <0x98>;
+	};
+
+	qos@fdf40600 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf40600 0x00 0x20>;
+		phandle = <0x99>;
+	};
+
+	qos@fdf40800 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf40800 0x00 0x20>;
+		phandle = <0x9a>;
+	};
+
+	qos@fdf41000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf41000 0x00 0x20>;
+		phandle = <0x9b>;
+	};
+
+	qos@fdf41100 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf41100 0x00 0x20>;
+		phandle = <0x9c>;
+	};
+
+	qos@fdf60000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf60000 0x00 0x20>;
+		phandle = <0x82>;
+	};
+
+	qos@fdf60200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf60200 0x00 0x20>;
+		phandle = <0x83>;
+	};
+
+	qos@fdf60400 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf60400 0x00 0x20>;
+		phandle = <0x84>;
+	};
+
+	qos@fdf61000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf61000 0x00 0x20>;
+		phandle = <0x85>;
+	};
+
+	qos@fdf61200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf61200 0x00 0x20>;
+		phandle = <0x86>;
+	};
+
+	qos@fdf61400 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf61400 0x00 0x20>;
+		phandle = <0x87>;
+	};
+
+	qos@fdf62000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf62000 0x00 0x20>;
+		phandle = <0x80>;
+	};
+
+	qos@fdf63000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf63000 0x00 0x20>;
+		phandle = <0x81>;
+	};
+
+	qos@fdf64000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf64000 0x00 0x20>;
+		phandle = <0x90>;
+	};
+
+	qos@fdf66000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf66000 0x00 0x20>;
+		phandle = <0x88>;
+	};
+
+	qos@fdf66200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf66200 0x00 0x20>;
+		phandle = <0x89>;
+	};
+
+	qos@fdf66400 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf66400 0x00 0x20>;
+		phandle = <0x8a>;
+	};
+
+	qos@fdf66600 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf66600 0x00 0x20>;
+		phandle = <0x8b>;
+	};
+
+	qos@fdf66800 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf66800 0x00 0x20>;
+		phandle = <0x8c>;
+	};
+
+	qos@fdf66a00 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf66a00 0x00 0x20>;
+		phandle = <0x8d>;
+	};
+
+	qos@fdf66c00 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf66c00 0x00 0x20>;
+		phandle = <0x8e>;
+	};
+
+	qos@fdf66e00 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf66e00 0x00 0x20>;
+		phandle = <0x8f>;
+	};
+
+	qos@fdf67000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf67000 0x00 0x20>;
+		phandle = <0x91>;
+	};
+
+	qos@fdf67200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf67200 0x00 0x20>;
+		phandle = <0x23f>;
+	};
+
+	qos@fdf70000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf70000 0x00 0x20>;
+		phandle = <0x7a>;
+	};
+
+	qos@fdf71000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf71000 0x00 0x20>;
+		phandle = <0x7b>;
+	};
+
+	qos@fdf72000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf72000 0x00 0x20>;
+		phandle = <0x77>;
+	};
+
+	qos@fdf72200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf72200 0x00 0x20>;
+		phandle = <0x78>;
+	};
+
+	qos@fdf72400 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf72400 0x00 0x20>;
+		phandle = <0x79>;
+	};
+
+	qos@fdf80000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf80000 0x00 0x20>;
+		phandle = <0x94>;
+	};
+
+	qos@fdf81000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf81000 0x00 0x20>;
+		phandle = <0x95>;
+	};
+
+	qos@fdf81200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf81200 0x00 0x20>;
+		phandle = <0x96>;
+	};
+
+	qos@fdf82000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf82000 0x00 0x20>;
+		phandle = <0x92>;
+	};
+
+	qos@fdf82200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf82200 0x00 0x20>;
+		phandle = <0x93>;
+	};
+
+	dfi@fe060000 {
+		compatible = "rockchip,rk3588-dfi";
+		reg = <0x00 0xfe060000 0x00 0x10000>;
+		rockchip,pmu_grf = <0xf9>;
+		status = "okay";
+		phandle = <0x3e>;
+	};
+
+	pcie@fe180000 {
+		compatible = "rockchip,rk3588-pcie\0snps,dw-pcie";
+		#address-cells = <0x03>;
+		#size-cells = <0x02>;
+		bus-range = <0x30 0x3f>;
+		clocks = <0x02 0x151 0x02 0x156 0x02 0x14c 0x02 0x15c 0x02 0x161 0x02 0x2c5>;
+		clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe";
+		device_type = "pci";
+		interrupts = <0x00 0xf8 0x04 0x00 0xf7 0x04 0x00 0xf6 0x04 0x00 0xf5 0x04 0x00 0xf4 0x04>;
+		interrupt-names = "sys\0pmc\0msg\0legacy\0err";
+		#interrupt-cells = <0x01>;
+		interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+		interrupt-map = <0x00 0x00 0x00 0x01 0xfa 0x00 0x00 0x00 0x00 0x02 0xfa 0x01 0x00 0x00 0x00 0x03 0xfa 0x02 0x00 0x00 0x00 0x04 0xfa 0x03>;
+		linux,pci-domain = <0x03>;
+		num-ib-windows = <0x08>;
+		num-ob-windows = <0x08>;
+		num-viewport = <0x04>;
+		max-link-speed = <0x02>;
+		msi-map = <0x3000 0xfb 0x3000 0x1000>;
+		num-lanes = <0x01>;
+		phys = <0x69 0x02>;
+		phy-names = "pcie-phy";
+		ranges = <0x800 0x00 0xf3000000 0x00 0xf3000000 0x00 0x100000 0x81000000 0x00 0xf3100000 0x00 0xf3100000 0x00 0x100000 0x82000000 0x00 0xf3200000 0x00 0xf3200000 0x00 0xe00000 0xc3000000 0x09 0xc0000000 0x09 0xc0000000 0x00 0x40000000>;
+		reg = <0x00 0xfe180000 0x00 0x10000 0x0a 0x40c00000 0x00 0x400000>;
+		reg-names = "pcie-apb\0pcie-dbi";
+		resets = <0x02 0x210 0x02 0x21f>;
+		reset-names = "pcie\0periph";
+		rockchip,pipe-grf = <0x6e>;
+		status = "disabled";
+		phandle = <0x240>;
+
+		legacy-interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0x00>;
+			#interrupt-cells = <0x01>;
+			interrupt-parent = <0x01>;
+			interrupts = <0x00 0xf5 0x01>;
+			phandle = <0xfa>;
+		};
+	};
+
+	pcie@fe190000 {
+		compatible = "rockchip,rk3588-pcie\0snps,dw-pcie";
+		#address-cells = <0x03>;
+		#size-cells = <0x02>;
+		bus-range = <0x40 0x4f>;
+		clocks = <0x02 0x152 0x02 0x157 0x02 0x14d 0x02 0x15d 0x02 0x162 0x02 0x182>;
+		clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe";
+		device_type = "pci";
+		interrupts = <0x00 0xfd 0x04 0x00 0xfc 0x04 0x00 0xfb 0x04 0x00 0xfa 0x04 0x00 0xf9 0x04>;
+		interrupt-names = "sys\0pmc\0msg\0legacy\0err";
+		#interrupt-cells = <0x01>;
+		interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+		interrupt-map = <0x00 0x00 0x00 0x01 0xfc 0x00 0x00 0x00 0x00 0x02 0xfc 0x01 0x00 0x00 0x00 0x03 0xfc 0x02 0x00 0x00 0x00 0x04 0xfc 0x03>;
+		linux,pci-domain = <0x04>;
+		num-ib-windows = <0x08>;
+		num-ob-windows = <0x08>;
+		num-viewport = <0x04>;
+		max-link-speed = <0x02>;
+		msi-map = <0x4000 0xfb 0x4000 0x1000>;
+		num-lanes = <0x01>;
+		phys = <0xfd 0x02>;
+		phy-names = "pcie-phy";
+		ranges = <0x800 0x00 0xf4000000 0x00 0xf4000000 0x00 0x100000 0x81000000 0x00 0xf4100000 0x00 0xf4100000 0x00 0x100000 0x82000000 0x00 0xf4200000 0x00 0xf4200000 0x00 0xe00000 0xc3000000 0x0a 0x00 0x0a 0x00 0x00 0x40000000>;
+		reg = <0x00 0xfe190000 0x00 0x10000 0x0a 0x41000000 0x00 0x400000>;
+		reg-names = "pcie-apb\0pcie-dbi";
+		resets = <0x02 0x211 0x02 0x220>;
+		reset-names = "pcie\0periph";
+		rockchip,pipe-grf = <0x6e>;
+		status = "okay";
+		reset-gpios = <0xfe 0x19 0x00>;
+		rockchip,skip-scan-in-resume;
+		vpcie3v3-supply = <0xff>;
+		phandle = <0x241>;
+
+		legacy-interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0x00>;
+			#interrupt-cells = <0x01>;
+			interrupt-parent = <0x01>;
+			interrupts = <0x00 0xfa 0x01>;
+			phandle = <0xfc>;
+		};
+	};
+
+	ethernet@fe1c0000 {
+		compatible = "rockchip,rk3588-gmac\0snps,dwmac-4.20a";
+		reg = <0x00 0xfe1c0000 0x00 0x10000>;
+		interrupts = <0x00 0xea 0x04 0x00 0xe9 0x04>;
+		interrupt-names = "macirq\0eth_wake_irq";
+		rockchip,grf = <0xc4>;
+		rockchip,php_grf = <0x6e>;
+		clocks = <0x02 0x144 0x02 0x145 0x02 0x168 0x02 0x16d 0x02 0x143>;
+		clock-names = "stmmaceth\0clk_mac_ref\0pclk_mac\0aclk_mac\0ptp_ref";
+		resets = <0x02 0x20b>;
+		reset-names = "stmmaceth";
+		power-domains = <0x5b 0x21>;
+		snps,mixed-burst;
+		snps,tso;
+		snps,axi-config = <0x100>;
+		snps,mtl-rx-config = <0x101>;
+		snps,mtl-tx-config = <0x102>;
+		status = "okay";
+		phy-mode = "rgmii-rxid";
+		clock_in_out = "output";
+		snps,reset-gpio = <0xfe 0x0a 0x01>;
+		snps,reset-active-low;
+		snps,reset-delays-us = <0x00 0x4e20 0x186a0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x103 0x104 0x105 0x106 0x107>;
+		tx_delay = <0x42>;
+		phy-handle = <0x108>;
+		phandle = <0x242>;
+
+		mdio {
+			compatible = "snps,dwmac-mdio";
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			phandle = <0x243>;
+
+			phy@1 {
+				compatible = "ethernet-phy-ieee802.3-c22";
+				reg = <0x01>;
+				phandle = <0x108>;
+			};
+		};
+
+		stmmac-axi-config {
+			snps,wr_osr_lmt = <0x04>;
+			snps,rd_osr_lmt = <0x08>;
+			snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+			phandle = <0x100>;
+		};
+
+		rx-queues-config {
+			snps,rx-queues-to-use = <0x02>;
+			phandle = <0x101>;
+
+			queue0 {
+			};
+
+			queue1 {
+			};
+		};
+
+		tx-queues-config {
+			snps,tx-queues-to-use = <0x02>;
+			phandle = <0x102>;
+
+			queue0 {
+			};
+
+			queue1 {
+			};
+		};
+	};
+
+	sata@fe210000 {
+		compatible = "rockchip,rk-ahci\0snps,dwc-ahci";
+		reg = <0x00 0xfe210000 0x00 0x1000>;
+		clocks = <0x02 0x171 0x02 0x16e 0x02 0x174 0x02 0x163 0x02 0x17e>;
+		clock-names = "sata\0pmalive\0rxoob\0ref\0asic";
+		interrupts = <0x00 0x111 0x04>;
+		interrupt-names = "hostc";
+		phys = <0xfd 0x01>;
+		phy-names = "sata-phy";
+		ports-implemented = <0x01>;
+		status = "disabled";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x109>;
+		phandle = <0x244>;
+	};
+
+	sata@fe230000 {
+		compatible = "rockchip,rk-ahci\0snps,dwc-ahci";
+		reg = <0x00 0xfe230000 0x00 0x1000>;
+		clocks = <0x02 0x173 0x02 0x170 0x02 0x176 0x02 0x165 0x02 0x180>;
+		clock-names = "sata\0pmalive\0rxoob\0ref\0asic";
+		interrupts = <0x00 0x113 0x04>;
+		interrupt-names = "hostc";
+		phys = <0x69 0x01>;
+		phy-names = "sata-phy";
+		ports-implemented = <0x01>;
+		status = "disabled";
+		phandle = <0x245>;
+	};
+
+	spi@fe2b0000 {
+		compatible = "rockchip,sfc";
+		reg = <0x00 0xfe2b0000 0x00 0x4000>;
+		interrupts = <0x00 0xce 0x04>;
+		clocks = <0x02 0x13d 0x02 0x13e>;
+		clock-names = "clk_sfc\0hclk_sfc";
+		assigned-clocks = <0x02 0x13d>;
+		assigned-clock-rates = <0x5f5e100>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+		max-freq = <0x5f5e100>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x10a>;
+		phandle = <0x246>;
+
+		spi-flash@0 {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			compatible = "jedec,spi-nor";
+			reg = <0x00>;
+			spi-max-frequency = <0x5f5e100>;
+			spi-tx-bus-width = <0x01>;
+			spi-rx-bus-width = <0x04>;
+			status = "okay";
+			phandle = <0x247>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <0x01>;
+				#size-cells = <0x01>;
+
+				uboot@0 {
+					label = "uboot";
+					reg = <0x00 0x200000>;
+				};
+
+				dtb@200000 {
+					label = "dtb";
+					reg = <0x200000 0x40000>;
+				};
+
+				firmware@240000 {
+					label = "firmware";
+					reg = <0x240000 0xdc0000>;
+				};
+			};
+		};
+	};
+
+	mmc@fe2c0000 {
+		compatible = "rockchip,rk3588-dw-mshc\0rockchip,rk3288-dw-mshc";
+		reg = <0x00 0xfe2c0000 0x00 0x4000>;
+		interrupts = <0x00 0xcb 0x04>;
+		clocks = <0x0e 0x17 0x0e 0x09 0x02 0x2c2 0x02 0x2c3>;
+		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
+		fifo-depth = <0x100>;
+		max-frequency = <0x8f0d180>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x10b 0x10c 0x10d 0x10e>;
+		power-domains = <0x5b 0x28>;
+		status = "okay";
+		no-sdio;
+		no-mmc;
+		bus-width = <0x04>;
+		cap-mmc-highspeed;
+		cap-sd-highspeed;
+		disable-wp;
+		sd-uhs-sdr104;
+		vmmc-supply = <0x10f>;
+		vqmmc-supply = <0x110>;
+		phandle = <0x248>;
+	};
+
+	mmc@fe2d0000 {
+		compatible = "rockchip,rk3588-dw-mshc\0rockchip,rk3288-dw-mshc";
+		reg = <0x00 0xfe2d0000 0x00 0x4000>;
+		interrupts = <0x00 0xcc 0x04>;
+		clocks = <0x02 0x199 0x02 0x19a 0x02 0x2c0 0x02 0x2c1>;
+		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
+		fifo-depth = <0x100>;
+		max-frequency = <0xbebc200>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x111>;
+		power-domains = <0x5b 0x25>;
+		status = "disabled";
+		phandle = <0x249>;
+	};
+
+	mmc@fe2e0000 {
+		compatible = "rockchip,rk3588-dwcmshc\0rockchip,dwcmshc-sdhci";
+		reg = <0x00 0xfe2e0000 0x00 0x10000>;
+		interrupts = <0x00 0xcd 0x04>;
+		assigned-clocks = <0x02 0x13b 0x02 0x13c 0x02 0x13a>;
+		assigned-clock-rates = <0xbebc200 0x16e3600 0xbebc200>;
+		clocks = <0x02 0x13a 0x02 0x138 0x02 0x139 0x02 0x13b 0x02 0x13c>;
+		clock-names = "core\0bus\0axi\0block\0timer";
+		resets = <0x02 0x1f6 0x02 0x1f4 0x02 0x1f5 0x02 0x1f7 0x02 0x1f8>;
+		reset-names = "core\0bus\0axi\0block\0timer";
+		max-frequency = <0xbebc200>;
+		status = "disabled";
+		bus-width = <0x08>;
+		no-sdio;
+		no-sd;
+		non-removable;
+		mmc-hs400-1_8v;
+		mmc-hs400-enhanced-strobe;
+		phandle = <0x24a>;
+	};
+
+	crypto@fe370000 {
+		compatible = "rockchip,rk3588-crypto";
+		reg = <0x00 0xfe370000 0x00 0x2000>;
+		interrupts = <0x00 0xd1 0x04>;
+		clocks = <0x0e 0x0b 0x0e 0x0c 0x0e 0x14 0x0e 0x15>;
+		clock-names = "aclk\0hclk\0sclk\0pka";
+		resets = <0x112 0x0f>;
+		reset-names = "crypto-rst";
+		status = "disabled";
+		phandle = <0x24b>;
+	};
+
+	rng@fe378000 {
+		compatible = "rockchip,trngv1";
+		reg = <0x00 0xfe378000 0x00 0x200>;
+		interrupts = <0x00 0x190 0x04>;
+		clocks = <0x0e 0x0c>;
+		clock-names = "hclk_trng";
+		resets = <0x112 0x30>;
+		reset-names = "reset";
+		status = "okay";
+		phandle = <0x24c>;
+	};
+
+	i2s@fe470000 {
+		compatible = "rockchip,rk3588-i2s-tdm";
+		reg = <0x00 0xfe470000 0x00 0x1000>;
+		interrupts = <0x00 0xb4 0x04>;
+		clocks = <0x02 0x33 0x02 0x37 0x02 0x30>;
+		clock-names = "mclk_tx\0mclk_rx\0hclk";
+		assigned-clocks = <0x02 0x31 0x02 0x35>;
+		assigned-clock-parents = <0x02 0x05 0x02 0x05>;
+		dmas = <0x71 0x00 0x71 0x01>;
+		dma-names = "tx\0rx";
+		power-domains = <0x5b 0x26>;
+		resets = <0x02 0x77 0x02 0x7a>;
+		reset-names = "tx-m\0rx-m";
+		rockchip,clk-trcm = <0x01>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x113 0x114 0x115 0x116>;
+		#sound-dai-cells = <0x00>;
+		status = "okay";
+		phandle = <0x24d>;
+	};
+
+	i2s@fe480000 {
+		compatible = "rockchip,rk3588-i2s-tdm";
+		reg = <0x00 0xfe480000 0x00 0x1000>;
+		interrupts = <0x00 0xb5 0x04>;
+		clocks = <0x02 0x28c 0x02 0x290 0x02 0x288>;
+		clock-names = "mclk_tx\0mclk_rx\0hclk";
+		dmas = <0x71 0x02 0x71 0x03>;
+		dma-names = "tx\0rx";
+		resets = <0x02 0xc002a 0x02 0xc002d>;
+		reset-names = "tx-m\0rx-m";
+		rockchip,clk-trcm = <0x01>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x117 0x118 0x119 0x11a>;
+		#sound-dai-cells = <0x00>;
+		status = "okay";
+		rockchip,i2s-tx-route = <0x03 0x02 0x01 0x00>;
+		rockchip,i2s-rx-route = <0x01 0x03 0x02 0x00>;
+		phandle = <0x1a4>;
+	};
+
+	i2s@fe490000 {
+		compatible = "rockchip,rk3588-i2s\0rockchip,rk3066-i2s";
+		reg = <0x00 0xfe490000 0x00 0x1000>;
+		interrupts = <0x00 0xb6 0x04>;
+		clocks = <0x02 0x27 0x02 0x22>;
+		clock-names = "i2s_clk\0i2s_hclk";
+		assigned-clocks = <0x02 0x24>;
+		assigned-clock-parents = <0x02 0x05>;
+		dmas = <0xdd 0x00 0xdd 0x01>;
+		dma-names = "tx\0rx";
+		power-domains = <0x5b 0x26>;
+		rockchip,clk-trcm = <0x01>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x11b 0x11c 0x11d 0x11e>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x24e>;
+	};
+
+	i2s@fe4a0000 {
+		compatible = "rockchip,rk3588-i2s\0rockchip,rk3066-i2s";
+		reg = <0x00 0xfe4a0000 0x00 0x1000>;
+		interrupts = <0x00 0xb7 0x04>;
+		clocks = <0x02 0x2d 0x02 0x23>;
+		clock-names = "i2s_clk\0i2s_hclk";
+		assigned-clocks = <0x02 0x2a>;
+		assigned-clock-parents = <0x02 0x05>;
+		dmas = <0xdd 0x02 0xdd 0x03>;
+		dma-names = "tx\0rx";
+		power-domains = <0x5b 0x26>;
+		rockchip,clk-trcm = <0x01>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x11f 0x120 0x121 0x122>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x24f>;
+	};
+
+	pdm@fe4b0000 {
+		compatible = "rockchip,rk3588-pdm";
+		reg = <0x00 0xfe4b0000 0x00 0x1000>;
+		clocks = <0x02 0x29f 0x02 0x29e>;
+		clock-names = "pdm_clk\0pdm_hclk";
+		dmas = <0x71 0x04>;
+		dma-names = "rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x123 0x124 0x125 0x126 0x127 0x128>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x250>;
+	};
+
+	pdm@fe4c0000 {
+		compatible = "rockchip,rk3588-pdm";
+		reg = <0x00 0xfe4c0000 0x00 0x1000>;
+		clocks = <0x02 0x3b 0x02 0x3a>;
+		clock-names = "pdm_clk\0pdm_hclk";
+		assigned-clocks = <0x02 0x3b>;
+		assigned-clock-parents = <0x02 0x05>;
+		dmas = <0xdd 0x04>;
+		dma-names = "rx";
+		power-domains = <0x5b 0x26>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x129 0x12a 0x12b 0x12c 0x12d 0x12e>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x251>;
+	};
+
+	vad@fe4d0000 {
+		compatible = "rockchip,rk3588-vad";
+		reg = <0x00 0xfe4d0000 0x00 0x1000>;
+		reg-names = "vad";
+		clocks = <0x02 0x2a0>;
+		clock-names = "hclk";
+		interrupts = <0x00 0xca 0x04>;
+		rockchip,audio-src = <0x00>;
+		rockchip,det-channel = <0x00>;
+		rockchip,mode = <0x00>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x252>;
+	};
+
+	spdif-tx@fe4e0000 {
+		compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif";
+		reg = <0x00 0xfe4e0000 0x00 0x1000>;
+		interrupts = <0x00 0xc1 0x04>;
+		dmas = <0x71 0x05>;
+		dma-names = "tx";
+		clock-names = "mclk\0hclk";
+		clocks = <0x02 0x41 0x02 0x3e>;
+		assigned-clocks = <0x02 0x3f>;
+		assigned-clock-parents = <0x02 0x05>;
+		power-domains = <0x5b 0x26>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x12f>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x253>;
+	};
+
+	spdif-tx@fe4f0000 {
+		compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif";
+		reg = <0x00 0xfe4f0000 0x00 0x1000>;
+		interrupts = <0x00 0xc2 0x04>;
+		dmas = <0xdd 0x05>;
+		dma-names = "tx";
+		clock-names = "mclk\0hclk";
+		clocks = <0x02 0x47 0x02 0x44>;
+		assigned-clocks = <0x02 0x45>;
+		assigned-clock-parents = <0x02 0x05>;
+		power-domains = <0x5b 0x26>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x130>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x19e>;
+	};
+
+	codec-digital@fe500000 {
+		compatible = "rockchip,rk3588-codec-digital\0rockchip,codec-digital-v1";
+		reg = <0x00 0xfe500000 0x00 0x1000>;
+		clocks = <0x02 0x29 0x02 0x2f>;
+		clock-names = "dac\0pclk";
+		power-domains = <0x5b 0x26>;
+		resets = <0x02 0x84>;
+		reset-names = "reset";
+		rockchip,grf = <0xc4>;
+		rockchip,pwm-output-mode;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x131>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x254>;
+	};
+
+	hwspinlock@fe5a0000 {
+		compatible = "rockchip,hwspinlock";
+		reg = <0x00 0xfe5a0000 0x00 0x100>;
+		#hwlock-cells = <0x01>;
+		phandle = <0x255>;
+	};
+
+	interrupt-controller@fe600000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <0x03>;
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+		interrupt-controller;
+		reg = <0x00 0xfe600000 0x00 0x10000 0x00 0xfe680000 0x00 0x100000>;
+		interrupts = <0x01 0x09 0x04>;
+		phandle = <0x01>;
+
+		msi-controller@fe640000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <0x01>;
+			reg = <0x00 0xfe640000 0x00 0x20000>;
+			phandle = <0xfb>;
+		};
+
+		msi-controller@fe660000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <0x01>;
+			reg = <0x00 0xfe660000 0x00 0x20000>;
+			phandle = <0x256>;
+		};
+	};
+
+	dma-controller@fea10000 {
+		compatible = "arm,pl330\0arm,primecell";
+		reg = <0x00 0xfea10000 0x00 0x4000>;
+		interrupts = <0x00 0x56 0x04 0x00 0x57 0x04>;
+		clocks = <0x02 0x78>;
+		clock-names = "apb_pclk";
+		#dma-cells = <0x01>;
+		arm,pl330-periph-burst;
+		phandle = <0x71>;
+	};
+
+	dma-controller@fea30000 {
+		compatible = "arm,pl330\0arm,primecell";
+		reg = <0x00 0xfea30000 0x00 0x4000>;
+		interrupts = <0x00 0x58 0x04 0x00 0x59 0x04>;
+		clocks = <0x02 0x79>;
+		clock-names = "apb_pclk";
+		#dma-cells = <0x01>;
+		arm,pl330-periph-burst;
+		phandle = <0xdd>;
+	};
+
+	can@fea50000 {
+		compatible = "rockchip,can-2.0";
+		reg = <0x00 0xfea50000 0x00 0x1000>;
+		interrupts = <0x00 0x155 0x04>;
+		clocks = <0x02 0x70 0x02 0x6f>;
+		clock-names = "baudclk\0apb_pclk";
+		resets = <0x02 0xb9 0x02 0xb8>;
+		reset-names = "can\0can-apb";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x132>;
+		tx-fifo-depth = <0x01>;
+		rx-fifo-depth = <0x06>;
+		status = "disabled";
+		phandle = <0x257>;
+	};
+
+	can@fea60000 {
+		compatible = "rockchip,can-2.0";
+		reg = <0x00 0xfea60000 0x00 0x1000>;
+		interrupts = <0x00 0x156 0x04>;
+		clocks = <0x02 0x72 0x02 0x71>;
+		clock-names = "baudclk\0apb_pclk";
+		resets = <0x02 0xbb 0x02 0xba>;
+		reset-names = "can\0can-apb";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x133>;
+		tx-fifo-depth = <0x01>;
+		rx-fifo-depth = <0x06>;
+		status = "disabled";
+		assigned-clocks = <0x02 0x72>;
+		assigned-clock-rates = <0xbebc200>;
+		phandle = <0x258>;
+	};
+
+	can@fea70000 {
+		compatible = "rockchip,can-2.0";
+		reg = <0x00 0xfea70000 0x00 0x1000>;
+		interrupts = <0x00 0x157 0x04>;
+		clocks = <0x02 0x74 0x02 0x73>;
+		clock-names = "baudclk\0apb_pclk";
+		resets = <0x02 0xbd 0x02 0xbc>;
+		reset-names = "can\0can-apb";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x134>;
+		tx-fifo-depth = <0x01>;
+		rx-fifo-depth = <0x06>;
+		status = "disabled";
+		assigned-clocks = <0x02 0x74>;
+		assigned-clock-rates = <0xbebc200>;
+		phandle = <0x259>;
+	};
+
+	decompress@fea80000 {
+		compatible = "rockchip,hw-decompress";
+		reg = <0x00 0xfea80000 0x00 0x1000>;
+		interrupts = <0x00 0x55 0x04>;
+		clocks = <0x02 0x75 0x02 0x77 0x02 0x76>;
+		clock-names = "aclk\0dclk\0pclk";
+		resets = <0x02 0x118>;
+		reset-names = "dresetn";
+		status = "disabled";
+		phandle = <0x25a>;
+	};
+
+	i2c@fea90000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfea90000 0x00 0x1000>;
+		clocks = <0x02 0x8d 0x02 0x85>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x13e 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x135>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x25b>;
+	};
+
+	i2c@feaa0000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfeaa0000 0x00 0x1000>;
+		clocks = <0x02 0x8e 0x02 0x86>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x13f 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x136>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+		phandle = <0x25c>;
+
+		touchscreen@14 {
+			compatible = "goodix,gt9271";
+			reg = <0x14>;
+			interrupt-parent = <0xe2>;
+			interrupts = <0x07 0x08>;
+			irq-gpios = <0xe2 0x07 0x08>;
+			reset-gpios = <0xe2 0x04 0x00>;
+			touchscreen-inverted-x;
+			touchscreen-swapped-x-y;
+			touchscreen-size-x = <0x500>;
+			touchscreen-size-y = <0x320>;
+			status = "okay";
+			phandle = <0x25d>;
+		};
+
+		vm149c@c {
+			compatible = "silicon touch,vm149c";
+			status = "disabled";
+			reg = <0x0c>;
+			rockchip,camera-module-index = <0x01>;
+			rockchip,camera-module-facing = "front";
+			phandle = <0x138>;
+		};
+
+		ov13850@10 {
+			compatible = "ovti,ov13850";
+			status = "disabled";
+			reg = <0x10>;
+			clocks = <0x02 0x103>;
+			clock-names = "xvclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <0x137>;
+			rockchip,grf = <0xc4>;
+			reset-gpios = <0xe2 0x06 0x00>;
+			pwdn-gpios = <0xfe 0x15 0x00>;
+			rockchip,camera-module-index = <0x01>;
+			rockchip,camera-module-facing = "front";
+			rockchip,camera-module-name = "CMK-CT0116";
+			rockchip,camera-module-lens-name = "default";
+			lens-focus = <0x138>;
+			phandle = <0x25e>;
+
+			port {
+
+				endpoint {
+					remote-endpoint = <0x139>;
+					data-lanes = <0x01 0x02>;
+					phandle = <0x2e>;
+				};
+			};
+		};
+
+		dw9714@c {
+			compatible = "dongwoon,dw9714";
+			status = "disabled";
+			reg = <0x0c>;
+			rockchip,camera-module-index = <0x00>;
+			rockchip,vcm-start-current = <0x0a>;
+			rockchip,vcm-rated-current = <0x55>;
+			rockchip,vcm-step-mode = <0x05>;
+			rockchip,camera-module-facing = "front";
+			phandle = <0x13a>;
+		};
+
+		ov13855@36 {
+			compatible = "ovti,ov13855";
+			status = "disabled";
+			reg = <0x36>;
+			clocks = <0x02 0x103>;
+			clock-names = "xvclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <0x137>;
+			rockchip,grf = <0xc4>;
+			reset-gpios = <0xe2 0x06 0x00>;
+			pwdn-gpios = <0xfe 0x15 0x00>;
+			rockchip,camera-module-index = <0x01>;
+			rockchip,camera-module-facing = "front";
+			rockchip,camera-module-name = "CMK-OT2016-FV1";
+			rockchip,camera-module-lens-name = "default";
+			lens-focus = <0x13a>;
+			phandle = <0x25f>;
+
+			port {
+
+				endpoint {
+					remote-endpoint = <0x13b>;
+					data-lanes = <0x01 0x02>;
+					phandle = <0x2f>;
+				};
+			};
+		};
+
+		rk8602@42 {
+			compatible = "rockchip,rk8602";
+			reg = <0x42>;
+			vin-supply = <0x70>;
+			regulator-compatible = "rk860x-reg";
+			regulator-name = "vdd_npu_s0";
+			regulator-min-microvolt = <0x86470>;
+			regulator-max-microvolt = <0xe7ef0>;
+			regulator-ramp-delay = <0x8fc>;
+			rockchip,suspend-voltage-selector = <0x01>;
+			regulator-boot-on;
+			regulator-always-on;
+			phandle = <0xa8>;
+
+			regulator-state-mem {
+				regulator-off-in-suspend;
+			};
+		};
+	};
+
+	i2c@feab0000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfeab0000 0x00 0x1000>;
+		clocks = <0x02 0x8f 0x02 0x87>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x140 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x13c>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x260>;
+	};
+
+	i2c@feac0000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfeac0000 0x00 0x1000>;
+		clocks = <0x02 0x90 0x02 0x88>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x141 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x13d>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x261>;
+	};
+
+	i2c@fead0000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfead0000 0x00 0x1000>;
+		clocks = <0x02 0x91 0x02 0x89>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x142 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x13e>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x262>;
+	};
+
+	timer@feae0000 {
+		compatible = "rockchip,rk3588-timer\0rockchip,rk3288-timer";
+		reg = <0x00 0xfeae0000 0x00 0x20>;
+		interrupts = <0x00 0x121 0x04>;
+		clocks = <0x02 0x5c 0x02 0x5f>;
+		clock-names = "pclk\0timer";
+		phandle = <0x263>;
+	};
+
+	watchdog@feaf0000 {
+		compatible = "snps,dw-wdt";
+		reg = <0x00 0xfeaf0000 0x00 0x100>;
+		clocks = <0x02 0x6c 0x02 0x6b>;
+		clock-names = "tclk\0pclk";
+		interrupts = <0x00 0x13b 0x04>;
+		status = "okay";
+		phandle = <0x264>;
+	};
+
+	spi@feb00000 {
+		compatible = "rockchip,rk3066-spi";
+		reg = <0x00 0xfeb00000 0x00 0x1000>;
+		interrupts = <0x00 0x146 0x04>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		clocks = <0x02 0xa3 0x02 0x9e>;
+		clock-names = "spiclk\0apb_pclk";
+		dmas = <0x71 0x0e 0x71 0x0f>;
+		dma-names = "tx\0rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x13f 0x140 0x141>;
+		num-cs = <0x02>;
+		status = "disabled";
+		phandle = <0x265>;
+	};
+
+	spi@feb10000 {
+		compatible = "rockchip,rk3066-spi";
+		reg = <0x00 0xfeb10000 0x00 0x1000>;
+		interrupts = <0x00 0x147 0x04>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		clocks = <0x02 0xa4 0x02 0x9f>;
+		clock-names = "spiclk\0apb_pclk";
+		dmas = <0x71 0x10 0x71 0x11>;
+		dma-names = "tx\0rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x142 0x143 0x144>;
+		num-cs = <0x02>;
+		status = "disabled";
+		phandle = <0x266>;
+	};
+
+	spi@feb20000 {
+		compatible = "rockchip,rk3066-spi";
+		reg = <0x00 0xfeb20000 0x00 0x1000>;
+		interrupts = <0x00 0x148 0x04>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		clocks = <0x02 0xa5 0x02 0xa0>;
+		clock-names = "spiclk\0apb_pclk";
+		dmas = <0xdd 0x0f 0xdd 0x10>;
+		dma-names = "tx\0rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x145 0x146>;
+		num-cs = <0x01>;
+		status = "okay";
+		assigned-clocks = <0x02 0xa5>;
+		assigned-clock-rates = <0xbebc200>;
+		phandle = <0x267>;
+
+		rk806single@0 {
+			compatible = "rockchip,rk806";
+			spi-max-frequency = <0xf4240>;
+			reg = <0x00>;
+			interrupt-parent = <0x147>;
+			interrupts = <0x07 0x08>;
+			pinctrl-names = "default\0pmic-power-off";
+			pinctrl-0 = <0x148 0x149 0x14a 0x14b>;
+			pinctrl-1 = <0x14c>;
+			low_voltage_threshold = <0xbb8>;
+			shutdown_voltage_threshold = <0xa8c>;
+			shutdown_temperture_threshold = <0xa0>;
+			hotdie_temperture_threshold = <0x73>;
+			pmic-reset-func = <0x01>;
+			vcc1-supply = <0x70>;
+			vcc2-supply = <0x70>;
+			vcc3-supply = <0x70>;
+			vcc4-supply = <0x70>;
+			vcc5-supply = <0x70>;
+			vcc6-supply = <0x70>;
+			vcc7-supply = <0x70>;
+			vcc8-supply = <0x70>;
+			vcc9-supply = <0x70>;
+			vcc10-supply = <0x70>;
+			vcc11-supply = <0x14d>;
+			vcc12-supply = <0x70>;
+			vcc13-supply = <0x14e>;
+			vcc14-supply = <0x14e>;
+			vcca-supply = <0x70>;
+			phandle = <0x268>;
+
+			pwrkey {
+				status = "okay";
+			};
+
+			pinctrl_rk806 {
+				gpio-controller;
+				#gpio-cells = <0x02>;
+				phandle = <0x269>;
+
+				rk806_dvs1_null {
+					pins = "gpio_pwrctrl2";
+					function = "pin_fun0";
+					phandle = <0x149>;
+				};
+
+				rk806_dvs1_slp {
+					pins = "gpio_pwrctrl1";
+					function = "pin_fun1";
+					phandle = <0x26a>;
+				};
+
+				rk806_dvs1_pwrdn {
+					pins = "gpio_pwrctrl1";
+					function = "pin_fun2";
+					phandle = <0x14c>;
+				};
+
+				rk806_dvs1_rst {
+					pins = "gpio_pwrctrl1";
+					function = "pin_fun3";
+					phandle = <0x26b>;
+				};
+
+				rk806_dvs2_null {
+					pins = "gpio_pwrctrl2";
+					function = "pin_fun0";
+					phandle = <0x14a>;
+				};
+
+				rk806_dvs2_slp {
+					pins = "gpio_pwrctrl2";
+					function = "pin_fun1";
+					phandle = <0x26c>;
+				};
+
+				rk806_dvs2_pwrdn {
+					pins = "gpio_pwrctrl2";
+					function = "pin_fun2";
+					phandle = <0x26d>;
+				};
+
+				rk806_dvs2_rst {
+					pins = "gpio_pwrctrl2";
+					function = "pin_fun3";
+					phandle = <0x26e>;
+				};
+
+				rk806_dvs2_dvs {
+					pins = "gpio_pwrctrl2";
+					function = "pin_fun4";
+					phandle = <0x26f>;
+				};
+
+				rk806_dvs2_gpio {
+					pins = "gpio_pwrctrl2";
+					function = "pin_fun5";
+					phandle = <0x270>;
+				};
+
+				rk806_dvs3_null {
+					pins = "gpio_pwrctrl3";
+					function = "pin_fun0";
+					phandle = <0x14b>;
+				};
+
+				rk806_dvs3_slp {
+					pins = "gpio_pwrctrl3";
+					function = "pin_fun1";
+					phandle = <0x271>;
+				};
+
+				rk806_dvs3_pwrdn {
+					pins = "gpio_pwrctrl3";
+					function = "pin_fun2";
+					phandle = <0x272>;
+				};
+
+				rk806_dvs3_rst {
+					pins = "gpio_pwrctrl3";
+					function = "pin_fun3";
+					phandle = <0x273>;
+				};
+
+				rk806_dvs3_dvs {
+					pins = "gpio_pwrctrl3";
+					function = "pin_fun4";
+					phandle = <0x274>;
+				};
+
+				rk806_dvs3_gpio {
+					pins = "gpio_pwrctrl3";
+					function = "pin_fun5";
+					phandle = <0x275>;
+				};
+			};
+
+			regulators {
+
+				DCDC_REG1 {
+					regulator-boot-on;
+					regulator-min-microvolt = <0x86470>;
+					regulator-max-microvolt = <0xe7ef0>;
+					regulator-ramp-delay = <0x30d4>;
+					regulator-name = "vdd_gpu_s0";
+					regulator-enable-ramp-delay = <0x190>;
+					phandle = <0x5d>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				DCDC_REG2 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x86470>;
+					regulator-max-microvolt = <0xe7ef0>;
+					regulator-ramp-delay = <0x30d4>;
+					regulator-name = "vdd_cpu_lit_s0";
+					phandle = <0x12>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				DCDC_REG3 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xa4cb8>;
+					regulator-max-microvolt = <0xb71b0>;
+					regulator-ramp-delay = <0x30d4>;
+					regulator-name = "vdd_log_s0";
+					phandle = <0x41>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+						regulator-suspend-microvolt = <0xb71b0>;
+						regulator-on-in-suspend;
+					};
+				};
+
+				DCDC_REG4 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x86470>;
+					regulator-max-microvolt = <0xe7ef0>;
+					regulator-init-microvolt = <0xb71b0>;
+					regulator-ramp-delay = <0x30d4>;
+					regulator-name = "vdd_vdenc_s0";
+					phandle = <0x276>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				DCDC_REG5 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xa4cb8>;
+					regulator-max-microvolt = <0xdbba0>;
+					regulator-ramp-delay = <0x30d4>;
+					regulator-name = "vdd_ddr_s0";
+					phandle = <0x40>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+						regulator-suspend-microvolt = <0xcf850>;
+					};
+				};
+
+				DCDC_REG6 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-name = "vdd2_ddr_s3";
+					phandle = <0x277>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+					};
+				};
+
+				DCDC_REG7 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1e8480>;
+					regulator-max-microvolt = <0x1e8480>;
+					regulator-name = "vdd_2v0_pldo_s3";
+					phandle = <0x14d>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0x1e8480>;
+					};
+				};
+
+				DCDC_REG8 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x325aa0>;
+					regulator-max-microvolt = <0x325aa0>;
+					regulator-name = "vcc_3v3_s3";
+					phandle = <0x1b0>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0x325aa0>;
+					};
+				};
+
+				DCDC_REG9 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-name = "vddq_ddr_s0";
+					phandle = <0x278>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				DCDC_REG10 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x1b7740>;
+					regulator-name = "vcc_1v8_s3";
+					phandle = <0x279>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0x1b7740>;
+					};
+				};
+
+				PLDO_REG1 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x1b7740>;
+					regulator-name = "avcc_1v8_s0";
+					phandle = <0x1a3>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				PLDO_REG2 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x1b7740>;
+					regulator-name = "vcc_1v8_s0";
+					phandle = <0x16a>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+						regulator-suspend-microvolt = <0x1b7740>;
+					};
+				};
+
+				PLDO_REG3 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x124f80>;
+					regulator-max-microvolt = <0x124f80>;
+					regulator-name = "avdd_1v2_s0";
+					phandle = <0x27a>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				PLDO_REG4 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x325aa0>;
+					regulator-max-microvolt = <0x325aa0>;
+					regulator-name = "vcc_3v3_s0";
+					phandle = <0x27b>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				PLDO_REG5 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x325aa0>;
+					regulator-name = "vccio_sd_s0";
+					phandle = <0x110>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				PLDO_REG6 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x1b7740>;
+					regulator-name = "pldo6_s3";
+					phandle = <0x27c>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0x1b7740>;
+					};
+				};
+
+				NLDO_REG1 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xb71b0>;
+					regulator-max-microvolt = <0xb71b0>;
+					regulator-name = "vdd_0v75_s3";
+					phandle = <0x27d>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0xb71b0>;
+					};
+				};
+
+				NLDO_REG2 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xcf850>;
+					regulator-max-microvolt = <0xcf850>;
+					regulator-name = "vdd_ddr_pll_s0";
+					phandle = <0x27e>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+						regulator-suspend-microvolt = <0xcf850>;
+					};
+				};
+
+				NLDO_REG3 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xcc77c>;
+					regulator-max-microvolt = <0xcc77c>;
+					regulator-name = "avdd_0v75_s0";
+					phandle = <0x27f>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				NLDO_REG4 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xcf850>;
+					regulator-max-microvolt = <0xcf850>;
+					regulator-name = "vdd_0v85_s0";
+					phandle = <0x1a2>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				NLDO_REG5 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xb71b0>;
+					regulator-max-microvolt = <0xb71b0>;
+					regulator-name = "vdd_0v75_s0";
+					phandle = <0x280>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+			};
+		};
+	};
+
+	spi@feb30000 {
+		compatible = "rockchip,rk3066-spi";
+		reg = <0x00 0xfeb30000 0x00 0x1000>;
+		interrupts = <0x00 0x149 0x04>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		clocks = <0x02 0xa6 0x02 0xa1>;
+		clock-names = "spiclk\0apb_pclk";
+		dmas = <0xdd 0x11 0xdd 0x12>;
+		dma-names = "tx\0rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x14f 0x150 0x151>;
+		num-cs = <0x02>;
+		status = "disabled";
+		phandle = <0x281>;
+	};
+
+	serial@feb40000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfeb40000 0x00 0x100>;
+		interrupts = <0x00 0x14c 0x04>;
+		clocks = <0x02 0xb7 0x02 0xab>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0x71 0x08 0x71 0x09>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x152>;
+		status = "disabled";
+		phandle = <0x282>;
+	};
+
+	serial@feb50000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfeb50000 0x00 0x100>;
+		interrupts = <0x00 0x14d 0x04>;
+		clocks = <0x02 0xbb 0x02 0xac>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0x71 0x0a 0x71 0x0b>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x153>;
+		status = "disabled";
+		phandle = <0x283>;
+	};
+
+	serial@feb60000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfeb60000 0x00 0x100>;
+		interrupts = <0x00 0x14e 0x04>;
+		clocks = <0x02 0xbf 0x02 0xad>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0x71 0x0c 0x71 0x0d>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x154>;
+		status = "disabled";
+		phandle = <0x284>;
+	};
+
+	serial@feb70000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfeb70000 0x00 0x100>;
+		interrupts = <0x00 0x14f 0x04>;
+		clocks = <0x02 0xc3 0x02 0xae>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0xdd 0x09 0xdd 0x0a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x155>;
+		status = "disabled";
+		phandle = <0x285>;
+	};
+
+	serial@feb80000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfeb80000 0x00 0x100>;
+		interrupts = <0x00 0x150 0x04>;
+		clocks = <0x02 0xc7 0x02 0xaf>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0xdd 0x0b 0xdd 0x0c>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x156>;
+		status = "disabled";
+		phandle = <0x286>;
+	};
+
+	serial@feb90000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfeb90000 0x00 0x100>;
+		interrupts = <0x00 0x151 0x04>;
+		clocks = <0x02 0xcb 0x02 0xb0>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0xdd 0x0d 0xdd 0x0e>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x157>;
+		status = "disabled";
+		phandle = <0x287>;
+	};
+
+	serial@feba0000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfeba0000 0x00 0x100>;
+		interrupts = <0x00 0x152 0x04>;
+		clocks = <0x02 0xcf 0x02 0xb1>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0xde 0x07 0xde 0x08>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x158>;
+		status = "disabled";
+		phandle = <0x288>;
+	};
+
+	serial@febb0000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfebb0000 0x00 0x100>;
+		interrupts = <0x00 0x153 0x04>;
+		clocks = <0x02 0xd3 0x02 0xb2>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0xde 0x09 0xde 0x0a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x159>;
+		status = "disabled";
+		phandle = <0x289>;
+	};
+
+	serial@febc0000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfebc0000 0x00 0x100>;
+		interrupts = <0x00 0x154 0x04>;
+		clocks = <0x02 0xd7 0x02 0xb3>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0xde 0x0b 0xde 0x0c>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x15a 0x15b>;
+		status = "okay";
+		phandle = <0x28a>;
+	};
+
+	pwm@febd0000 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebd0000 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x15c>;
+		clocks = <0x02 0x54 0x02 0x53>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+		phandle = <0x28b>;
+	};
+
+	pwm@febd0010 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebd0010 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x15d>;
+		clocks = <0x02 0x54 0x02 0x53>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+		phandle = <0x28c>;
+	};
+
+	pwm@febd0020 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebd0020 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x15e>;
+		clocks = <0x02 0x54 0x02 0x53>;
+		clock-names = "pwm\0pclk";
+		status = "okay";
+		phandle = <0x199>;
+	};
+
+	pwm@febd0030 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebd0030 0x00 0x10>;
+		interrupts = <0x00 0x15a 0x04 0x00 0x15b 0x04>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x15f>;
+		clocks = <0x02 0x54 0x02 0x53>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+		phandle = <0x28d>;
+	};
+
+	pwm@febe0000 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebe0000 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x160>;
+		clocks = <0x02 0x57 0x02 0x56>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+		phandle = <0x28e>;
+	};
+
+	pwm@febe0010 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebe0010 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x161>;
+		clocks = <0x02 0x57 0x02 0x56>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+		phandle = <0x28f>;
+	};
+
+	pwm@febe0020 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebe0020 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x162>;
+		clocks = <0x02 0x57 0x02 0x56>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+		phandle = <0x290>;
+	};
+
+	pwm@febe0030 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebe0030 0x00 0x10>;
+		interrupts = <0x00 0x15c 0x04 0x00 0x15d 0x04>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x163>;
+		clocks = <0x02 0x57 0x02 0x56>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+		phandle = <0x291>;
+	};
+
+	pwm@febf0000 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebf0000 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x164>;
+		clocks = <0x02 0x5a 0x02 0x59>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+		phandle = <0x292>;
+	};
+
+	pwm@febf0010 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebf0010 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x165>;
+		clocks = <0x02 0x5a 0x02 0x59>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+		phandle = <0x293>;
+	};
+
+	pwm@febf0020 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebf0020 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x166>;
+		clocks = <0x02 0x5a 0x02 0x59>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+		phandle = <0x294>;
+	};
+
+	pwm@febf0030 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebf0030 0x00 0x10>;
+		interrupts = <0x00 0x15e 0x04 0x00 0x15f 0x04>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x167>;
+		clocks = <0x02 0x5a 0x02 0x59>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+		phandle = <0x295>;
+	};
+
+	tsadc@fec00000 {
+		compatible = "rockchip,rk3588-tsadc";
+		reg = <0x00 0xfec00000 0x00 0x400>;
+		interrupts = <0x00 0x18d 0x04>;
+		clocks = <0x02 0xaa 0x02 0xa9>;
+		clock-names = "tsadc\0apb_pclk";
+		assigned-clocks = <0x02 0xaa>;
+		assigned-clock-rates = <0x1e8480>;
+		resets = <0x02 0xc1 0x02 0xc0>;
+		reset-names = "tsadc\0tsadc-apb";
+		#thermal-sensor-cells = <0x01>;
+		rockchip,hw-tshut-temp = <0x1d4c0>;
+		rockchip,hw-tshut-mode = <0x00>;
+		rockchip,hw-tshut-polarity = <0x00>;
+		pinctrl-names = "gpio\0otpout";
+		pinctrl-0 = <0x168>;
+		pinctrl-1 = <0x169>;
+		status = "okay";
+		phandle = <0x58>;
+	};
+
+	saradc@fec10000 {
+		compatible = "rockchip,rk3588-saradc";
+		reg = <0x00 0xfec10000 0x00 0x10000>;
+		interrupts = <0x00 0x18e 0x04>;
+		#io-channel-cells = <0x01>;
+		clocks = <0x02 0x9d 0x02 0x9c>;
+		clock-names = "saradc\0apb_pclk";
+		resets = <0x02 0xbe>;
+		reset-names = "saradc-apb";
+		status = "okay";
+		vref-supply = <0x16a>;
+		phandle = <0x197>;
+	};
+
+	mailbox@fec60000 {
+		compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox";
+		reg = <0x00 0xfec60000 0x00 0x200>;
+		interrupts = <0x00 0x3d 0x04 0x00 0x3e 0x04 0x00 0x3f 0x04 0x00 0x40 0x04>;
+		clocks = <0x02 0x4c>;
+		clock-names = "pclk_mailbox";
+		#mbox-cells = <0x01>;
+		status = "disabled";
+		phandle = <0x296>;
+	};
+
+	mailbox@fec70000 {
+		compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox";
+		reg = <0x00 0xfec70000 0x00 0x200>;
+		interrupts = <0x00 0x45 0x04 0x00 0x46 0x04 0x00 0x47 0x04 0x00 0x48 0x04>;
+		clocks = <0x02 0x4d>;
+		clock-names = "pclk_mailbox";
+		#mbox-cells = <0x01>;
+		status = "disabled";
+		phandle = <0x297>;
+	};
+
+	i2c@fec80000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfec80000 0x00 0x1000>;
+		clocks = <0x02 0x92 0x02 0x8a>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x143 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x16b>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+		phandle = <0x298>;
+
+		es8388@10 {
+			status = "okay";
+			#sound-dai-cells = <0x00>;
+			compatible = "everest,es8388\0everest,es8323";
+			reg = <0x10>;
+			clocks = <0x02 0x291>;
+			clock-names = "mclk";
+			assigned-clocks = <0x02 0x291>;
+			assigned-clock-rates = <0xbb8000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <0x16c>;
+			phandle = <0x1a5>;
+		};
+
+		fusb302@22 {
+			compatible = "fcs,fusb302";
+			reg = <0x22>;
+			interrupt-parent = <0x147>;
+			interrupts = <0x1b 0x08>;
+			pinctrl-names = "default";
+			pinctrl-0 = <0x16d>;
+			vbus-supply = <0x16e>;
+			status = "okay";
+			phandle = <0x299>;
+
+			ports {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				port@0 {
+					reg = <0x00>;
+
+					endpoint@0 {
+						remote-endpoint = <0x16f>;
+						phandle = <0x62>;
+					};
+				};
+			};
+
+			connector {
+				compatible = "usb-c-connector";
+				label = "USB-C";
+				data-role = "dual";
+				power-role = "dual";
+				try-power-role = "sink";
+				op-sink-microwatt = <0xf4240>;
+				sink-pdos = <0x4019064>;
+				source-pdos = <0x401912c>;
+				phandle = <0x29a>;
+
+				altmodes {
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+
+					altmode@0 {
+						reg = <0x00>;
+						svid = <0xff01>;
+						vdo = <0xffffffff>;
+					};
+				};
+
+				ports {
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+
+					port@0 {
+						reg = <0x00>;
+
+						endpoint {
+							remote-endpoint = <0x170>;
+							phandle = <0x184>;
+						};
+					};
+
+					port@1 {
+						reg = <0x01>;
+
+						endpoint {
+							remote-endpoint = <0x171>;
+							phandle = <0x185>;
+						};
+					};
+				};
+			};
+		};
+
+		hym8563@51 {
+			compatible = "haoyu,hym8563";
+			reg = <0x51>;
+			#clock-cells = <0x00>;
+			clock-frequency = <0x8000>;
+			clock-output-names = "hym8563";
+			pinctrl-names = "default";
+			pinctrl-0 = <0x172>;
+			interrupt-parent = <0x147>;
+			interrupts = <0x08 0x08>;
+			wakeup-source;
+			phandle = <0x1a7>;
+		};
+	};
+
+	i2c@fec90000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfec90000 0x00 0x1000>;
+		clocks = <0x02 0x93 0x02 0x8b>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x144 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x173>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+		phandle = <0x29b>;
+
+		touchscreen@14 {
+			compatible = "goodix,gt9271";
+			reg = <0x14>;
+			interrupt-parent = <0xe2>;
+			interrupts = <0x0d 0x08>;
+			irq-gpios = <0xe2 0x0d 0x08>;
+			reset-gpios = <0xe2 0x0c 0x00>;
+			touchscreen-inverted-x;
+			touchscreen-swapped-x-y;
+			touchscreen-size-x = <0x500>;
+			touchscreen-size-y = <0x320>;
+			status = "okay";
+			phandle = <0x29c>;
+		};
+
+		vm149c-p1@c {
+			compatible = "silicon touch,vm149c";
+			status = "disabled";
+			reg = <0x0c>;
+			rockchip,camera-module-index = <0x01>;
+			rockchip,camera-module-facing = "back";
+			phandle = <0x175>;
+		};
+
+		ov13850-1@10 {
+			compatible = "ovti,ov13850";
+			status = "disabled";
+			reg = <0x10>;
+			clocks = <0x02 0x102>;
+			clock-names = "xvclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <0x174>;
+			reset-gpios = <0xfe 0x14 0x00>;
+			pwdn-gpios = <0xfe 0x16 0x00>;
+			rockchip,camera-module-index = <0x00>;
+			rockchip,camera-module-facing = "back";
+			rockchip,camera-module-name = "CMK-CT0116";
+			rockchip,camera-module-lens-name = "default";
+			lens-focus = <0x175>;
+			phandle = <0x29d>;
+
+			port {
+
+				endpoint {
+					remote-endpoint = <0x176>;
+					data-lanes = <0x01 0x02>;
+					phandle = <0x32>;
+				};
+			};
+		};
+
+		dw9714-p1@c {
+			compatible = "dongwoon,dw9714";
+			status = "disabled";
+			reg = <0x0c>;
+			rockchip,camera-module-index = <0x00>;
+			rockchip,vcm-start-current = <0x0a>;
+			rockchip,vcm-rated-current = <0x55>;
+			rockchip,vcm-step-mode = <0x05>;
+			rockchip,camera-module-facing = "back";
+			phandle = <0x177>;
+		};
+
+		ov13855-1@36 {
+			compatible = "ovti,ov13855";
+			status = "disabled";
+			reg = <0x36>;
+			clocks = <0x02 0x102>;
+			clock-names = "xvclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <0x174>;
+			reset-gpios = <0xfe 0x14 0x00>;
+			pwdn-gpios = <0xfe 0x16 0x00>;
+			rockchip,camera-module-index = <0x00>;
+			rockchip,camera-module-facing = "back";
+			rockchip,camera-module-name = "CMK-OT2016-FV1";
+			rockchip,camera-module-lens-name = "default";
+			lens-focus = <0x177>;
+			phandle = <0x29e>;
+
+			port {
+
+				endpoint {
+					remote-endpoint = <0x178>;
+					data-lanes = <0x01 0x02>;
+					phandle = <0x33>;
+				};
+			};
+		};
+
+		vm149c-p2@c {
+			compatible = "silicon touch,vm149c";
+			status = "disabled";
+			reg = <0x0c>;
+			rockchip,camera-module-index = <0x01>;
+			rockchip,camera-module-facing = "back";
+			phandle = <0x179>;
+		};
+
+		ov13850-2@10 {
+			compatible = "ovti,ov13850";
+			status = "disabled";
+			reg = <0x10>;
+			clocks = <0x02 0x103>;
+			clock-names = "xvclk";
+			power-domains = <0x5b 0x1b>;
+			pinctrl-names = "default";
+			pinctrl-0 = <0x137>;
+			rockchip,grf = <0xc4>;
+			reset-gpios = <0xe2 0x0a 0x00>;
+			pwdn-gpios = <0xfe 0x11 0x00>;
+			rockchip,camera-module-index = <0x00>;
+			rockchip,camera-module-facing = "back";
+			rockchip,camera-module-name = "CMK-CT0116";
+			rockchip,camera-module-lens-name = "default";
+			lens-focus = <0x179>;
+			phandle = <0x29f>;
+
+			port {
+
+				endpoint {
+					remote-endpoint = <0x17a>;
+					data-lanes = <0x01 0x02>;
+					phandle = <0x2a>;
+				};
+			};
+		};
+
+		dw9714-p2@c {
+			compatible = "dongwoon,dw9714";
+			status = "disabled";
+			reg = <0x0c>;
+			rockchip,camera-module-index = <0x00>;
+			rockchip,vcm-start-current = <0x0a>;
+			rockchip,vcm-rated-current = <0x55>;
+			rockchip,vcm-step-mode = <0x05>;
+			rockchip,camera-module-facing = "back";
+			phandle = <0x17b>;
+		};
+
+		ov13855-2@36 {
+			compatible = "ovti,ov13855";
+			status = "disabled";
+			reg = <0x36>;
+			clocks = <0x02 0x103>;
+			clock-names = "xvclk";
+			power-domains = <0x5b 0x1b>;
+			pinctrl-names = "default";
+			pinctrl-0 = <0x137>;
+			rockchip,grf = <0xc4>;
+			reset-gpios = <0xe2 0x0a 0x00>;
+			pwdn-gpios = <0xfe 0x11 0x00>;
+			rockchip,camera-module-index = <0x00>;
+			rockchip,camera-module-facing = "back";
+			rockchip,camera-module-name = "CMK-OT2016-FV1";
+			rockchip,camera-module-lens-name = "default";
+			lens-focus = <0x17b>;
+			phandle = <0x2a0>;
+
+			port {
+
+				endpoint {
+					remote-endpoint = <0x17c>;
+					data-lanes = <0x01 0x02>;
+					phandle = <0x2b>;
+				};
+			};
+		};
+	};
+
+	i2c@feca0000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfeca0000 0x00 0x1000>;
+		clocks = <0x02 0x94 0x02 0x8c>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x145 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x17d>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x2a1>;
+	};
+
+	spi@fecb0000 {
+		compatible = "rockchip,rk3066-spi";
+		reg = <0x00 0xfecb0000 0x00 0x1000>;
+		interrupts = <0x00 0x14a 0x04>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		clocks = <0x02 0xa7 0x02 0xa2>;
+		clock-names = "spiclk\0apb_pclk";
+		dmas = <0xde 0x0d 0xde 0x0e>;
+		dma-names = "tx\0rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x17e 0x17f>;
+		num-cs = <0x02>;
+		status = "disabled";
+		assigned-clocks = <0x02 0xa7>;
+		assigned-clock-rates = <0xbebc200>;
+		phandle = <0x2a2>;
+
+		spi_dev@1 {
+			compatible = "rockchip,spidev";
+			reg = <0x01>;
+			spi-max-frequency = <0x2faf080>;
+		};
+	};
+
+	otp@fecc0000 {
+		compatible = "rockchip,rk3588-otp";
+		reg = <0x00 0xfecc0000 0x00 0x400>;
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+		clocks = <0x02 0x96 0x02 0x95 0x02 0x97 0x02 0x99>;
+		clock-names = "otpc\0apb\0arb\0phy";
+		resets = <0x02 0x12a 0x02 0x129 0x02 0x12b>;
+		reset-names = "otpc\0apb\0arb";
+		phandle = <0x2a3>;
+
+		cpu-code@2 {
+			reg = <0x02 0x02>;
+			phandle = <0x28>;
+		};
+
+		specification-serial-number@6 {
+			reg = <0x06 0x01>;
+			bits = <0x00 0x05>;
+			phandle = <0x20>;
+		};
+
+		id@7 {
+			reg = <0x07 0x10>;
+			phandle = <0x26>;
+		};
+
+		cpu-version@1c {
+			reg = <0x1c 0x01>;
+			bits = <0x03 0x03>;
+			phandle = <0x27>;
+		};
+
+		cpub0-leakage@17 {
+			reg = <0x17 0x01>;
+			phandle = <0x22>;
+		};
+
+		cpub1-leakage@18 {
+			reg = <0x18 0x01>;
+			phandle = <0x24>;
+		};
+
+		cpul-leakage@19 {
+			reg = <0x19 0x01>;
+			phandle = <0x1f>;
+		};
+
+		log-leakage@1a {
+			reg = <0x1a 0x01>;
+			phandle = <0x42>;
+		};
+
+		gpu-leakage@1b {
+			reg = <0x1b 0x01>;
+			phandle = <0x5e>;
+		};
+
+		npu-leakage@28 {
+			reg = <0x28 0x01>;
+			phandle = <0xa9>;
+		};
+
+		codec-leakage@29 {
+			reg = <0x29 0x01>;
+			phandle = <0x2a4>;
+		};
+	};
+
+	mailbox@fece0000 {
+		compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox";
+		reg = <0x00 0xfece0000 0x00 0x200>;
+		interrupts = <0x00 0x4d 0x04 0x00 0x4e 0x04 0x00 0x4f 0x04 0x00 0x50 0x04>;
+		clocks = <0x02 0x4e>;
+		clock-names = "pclk_mailbox";
+		#mbox-cells = <0x01>;
+		status = "disabled";
+		phandle = <0x2a5>;
+	};
+
+	dma-controller@fed10000 {
+		compatible = "arm,pl330\0arm,primecell";
+		reg = <0x00 0xfed10000 0x00 0x4000>;
+		interrupts = <0x00 0x5a 0x04 0x00 0x5b 0x04>;
+		clocks = <0x02 0x7a>;
+		clock-names = "apb_pclk";
+		#dma-cells = <0x01>;
+		arm,pl330-periph-burst;
+		phandle = <0xde>;
+	};
+
+	phy@fed60000 {
+		compatible = "rockchip,rk3588-hdptx-phy";
+		reg = <0x00 0xfed60000 0x00 0x2000>;
+		clocks = <0x02 0x2b5 0x02 0x267>;
+		clock-names = "ref\0apb";
+		resets = <0x02 0x485 0x02 0xc003b 0x02 0xc003c 0x02 0xc003d>;
+		reset-names = "apb\0init\0cmn\0lane";
+		rockchip,grf = <0x180>;
+		#phy-cells = <0x00>;
+		status = "disabled";
+		phandle = <0xf6>;
+	};
+
+	hdmiphy@fed60000 {
+		compatible = "rockchip,rk3588-hdptx-phy-hdmi";
+		reg = <0x00 0xfed60000 0x00 0x2000>;
+		clocks = <0x02 0x2b5 0x02 0x267>;
+		clock-names = "ref\0apb";
+		resets = <0x02 0x48e 0x02 0x485 0x02 0xc003b 0x02 0xc003c 0x02 0xc003d 0x02 0x48c 0x02 0x48d>;
+		reset-names = "phy\0apb\0init\0cmn\0lane\0ropll\0lcpll";
+		rockchip,grf = <0x180>;
+		#phy-cells = <0x00>;
+		status = "okay";
+		phandle = <0xf2>;
+
+		clk-port {
+			#clock-cells = <0x00>;
+			status = "okay";
+			phandle = <0x36>;
+		};
+	};
+
+	phy@fed80000 {
+		compatible = "rockchip,rk3588-usbdp-phy";
+		reg = <0x00 0xfed80000 0x00 0x10000>;
+		rockchip,u2phy-grf = <0x181>;
+		rockchip,usb-grf = <0x6d>;
+		rockchip,usbdpphy-grf = <0x182>;
+		rockchip,vo-grf = <0xea>;
+		clocks = <0x02 0x2b6 0x02 0x27f 0x02 0x269 0x183>;
+		clock-names = "refclk\0immortal\0pclk\0utmi";
+		resets = <0x02 0x28 0x02 0x29 0x02 0x2a 0x02 0x2b 0x02 0x482>;
+		reset-names = "init\0cmn\0lane\0pcs_apb\0pma_apb";
+		status = "okay";
+		orientation-switch;
+		svid = <0xff01>;
+		sbu1-dc-gpios = <0xf3 0x05 0x00>;
+		sbu2-dc-gpios = <0xf3 0x07 0x00>;
+		phandle = <0x2a6>;
+
+		dp-port {
+			#phy-cells = <0x00>;
+			status = "okay";
+			phandle = <0xeb>;
+		};
+
+		u3-port {
+			#phy-cells = <0x00>;
+			status = "okay";
+			phandle = <0x61>;
+		};
+
+		port {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			endpoint@0 {
+				reg = <0x00>;
+				remote-endpoint = <0x184>;
+				phandle = <0x170>;
+			};
+
+			endpoint@1 {
+				reg = <0x01>;
+				remote-endpoint = <0x185>;
+				phandle = <0x171>;
+			};
+		};
+	};
+
+	phy@feda0000 {
+		compatible = "rockchip,rk3588-mipi-dcphy";
+		reg = <0x00 0xfeda0000 0x00 0x10000>;
+		rockchip,grf = <0x186>;
+		clocks = <0x02 0x108 0x02 0x2b6>;
+		clock-names = "pclk\0ref";
+		resets = <0x02 0xc0043 0x02 0x3e 0x02 0x3f 0x02 0xc0044>;
+		reset-names = "m_phy\0apb\0grf\0s_phy";
+		#phy-cells = <0x00>;
+		status = "okay";
+		phandle = <0x29>;
+	};
+
+	phy@fedb0000 {
+		compatible = "rockchip,rk3588-mipi-dcphy";
+		reg = <0x00 0xfedb0000 0x00 0x10000>;
+		rockchip,grf = <0x187>;
+		clocks = <0x02 0x109 0x02 0x2b6>;
+		clock-names = "pclk\0ref";
+		resets = <0x02 0xc0045 0x02 0x43 0x02 0x44 0x02 0xc0046>;
+		reset-names = "m_phy\0apb\0grf\0s_phy";
+		#phy-cells = <0x00>;
+		status = "okay";
+		phandle = <0x2d>;
+	};
+
+	csi2-dphy0-hw@fedc0000 {
+		compatible = "rockchip,rk3588-csi2-dphy-hw";
+		reg = <0x00 0xfedc0000 0x00 0x8000>;
+		clocks = <0x02 0x10c>;
+		clock-names = "pclk";
+		resets = <0x02 0x17 0x02 0x16>;
+		reset-names = "srst_csiphy0\0srst_p_csiphy0";
+		rockchip,grf = <0x188>;
+		rockchip,sys_grf = <0xc4>;
+		status = "disabled";
+		phandle = <0x31>;
+	};
+
+	phy@fee00000 {
+		compatible = "rockchip,rk3588-naneng-combphy";
+		reg = <0x00 0xfee00000 0x00 0x100>;
+		#phy-cells = <0x01>;
+		clocks = <0x02 0x2bd 0x02 0x185 0x02 0x166>;
+		clock-names = "refclk\0apbclk\0phpclk";
+		assigned-clocks = <0x02 0x2bd>;
+		assigned-clock-rates = <0x5f5e100>;
+		resets = <0x02 0x20005 0x02 0x4d6>;
+		reset-names = "combphy-apb\0combphy";
+		rockchip,pipe-grf = <0x6e>;
+		rockchip,pipe-phy-grf = <0x189>;
+		status = "okay";
+		phandle = <0xfd>;
+	};
+
+	phy@fee20000 {
+		compatible = "rockchip,rk3588-naneng-combphy";
+		reg = <0x00 0xfee20000 0x00 0x100>;
+		#phy-cells = <0x01>;
+		clocks = <0x02 0x2bf 0x02 0x187 0x02 0x166>;
+		clock-names = "refclk\0apbclk\0phpclk";
+		assigned-clocks = <0x02 0x2bf>;
+		assigned-clock-rates = <0x5f5e100>;
+		resets = <0x02 0x20007 0x02 0x4d8>;
+		reset-names = "combphy-apb\0combphy";
+		rockchip,pipe-grf = <0x6e>;
+		rockchip,pipe-phy-grf = <0x18a>;
+		rockchip,pcie1ln-sel-bits = <0x100 0x01 0x01 0x00>;
+		status = "okay";
+		phandle = <0x69>;
+	};
+
+	sram@ff001000 {
+		compatible = "mmio-sram";
+		reg = <0x00 0xff001000 0x00 0xef000>;
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+		ranges = <0x00 0x00 0xff001000 0xef000>;
+		phandle = <0x2a7>;
+
+		rkvdec-sram@0 {
+			reg = <0x00 0x78000>;
+			phandle = <0xbb>;
+		};
+
+		rkvdec-sram@78000 {
+			reg = <0x78000 0x77000>;
+			phandle = <0xbd>;
+		};
+	};
+
+	pinctrl {
+		compatible = "rockchip,rk3588-pinctrl";
+		rockchip,grf = <0x18b>;
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+		phandle = <0x18c>;
+
+		gpio@fd8a0000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xfd8a0000 0x00 0x100>;
+			interrupts = <0x00 0x115 0x04>;
+			clocks = <0x02 0x284 0x02 0x285>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			gpio-ranges = <0x18c 0x00 0x00 0x20>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0x147>;
+		};
+
+		gpio@fec20000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xfec20000 0x00 0x100>;
+			interrupts = <0x00 0x116 0x04>;
+			clocks = <0x02 0x7d 0x02 0x7e>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			gpio-ranges = <0x18c 0x00 0x20 0x20>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0xe2>;
+		};
+
+		gpio@fec30000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xfec30000 0x00 0x100>;
+			interrupts = <0x00 0x117 0x04>;
+			clocks = <0x02 0x7f 0x02 0x80>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			gpio-ranges = <0x18c 0x00 0x40 0x20>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0x2a8>;
+		};
+
+		gpio@fec40000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xfec40000 0x00 0x100>;
+			interrupts = <0x00 0x118 0x04>;
+			clocks = <0x02 0x81 0x02 0x82>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			gpio-ranges = <0x18c 0x00 0x60 0x20>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0xfe>;
+		};
+
+		gpio@fec50000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xfec50000 0x00 0x100>;
+			interrupts = <0x00 0x119 0x04>;
+			clocks = <0x02 0x83 0x02 0x84>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			gpio-ranges = <0x18c 0x00 0x80 0x20>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0xf3>;
+		};
+
+		pcfg-pull-up {
+			bias-pull-up;
+			phandle = <0x192>;
+		};
+
+		pcfg-pull-down {
+			bias-pull-down;
+			phandle = <0x193>;
+		};
+
+		pcfg-pull-none {
+			bias-disable;
+			phandle = <0x18d>;
+		};
+
+		pcfg-pull-none-drv-level-0 {
+			bias-disable;
+			drive-strength = <0x00>;
+			phandle = <0x2a9>;
+		};
+
+		pcfg-pull-none-drv-level-1 {
+			bias-disable;
+			drive-strength = <0x01>;
+			phandle = <0x2aa>;
+		};
+
+		pcfg-pull-none-drv-level-2 {
+			bias-disable;
+			drive-strength = <0x02>;
+			phandle = <0x196>;
+		};
+
+		pcfg-pull-none-drv-level-3 {
+			bias-disable;
+			drive-strength = <0x03>;
+			phandle = <0x2ab>;
+		};
+
+		pcfg-pull-none-drv-level-4 {
+			bias-disable;
+			drive-strength = <0x04>;
+			phandle = <0x2ac>;
+		};
+
+		pcfg-pull-none-drv-level-5 {
+			bias-disable;
+			drive-strength = <0x05>;
+			phandle = <0x2ad>;
+		};
+
+		pcfg-pull-none-drv-level-6 {
+			bias-disable;
+			drive-strength = <0x06>;
+			phandle = <0x2ae>;
+		};
+
+		pcfg-pull-none-drv-level-7 {
+			bias-disable;
+			drive-strength = <0x07>;
+			phandle = <0x2af>;
+		};
+
+		pcfg-pull-none-drv-level-8 {
+			bias-disable;
+			drive-strength = <0x08>;
+			phandle = <0x2b0>;
+		};
+
+		pcfg-pull-none-drv-level-9 {
+			bias-disable;
+			drive-strength = <0x09>;
+			phandle = <0x2b1>;
+		};
+
+		pcfg-pull-none-drv-level-10 {
+			bias-disable;
+			drive-strength = <0x0a>;
+			phandle = <0x2b2>;
+		};
+
+		pcfg-pull-none-drv-level-11 {
+			bias-disable;
+			drive-strength = <0x0b>;
+			phandle = <0x2b3>;
+		};
+
+		pcfg-pull-none-drv-level-12 {
+			bias-disable;
+			drive-strength = <0x0c>;
+			phandle = <0x2b4>;
+		};
+
+		pcfg-pull-none-drv-level-13 {
+			bias-disable;
+			drive-strength = <0x0d>;
+			phandle = <0x2b5>;
+		};
+
+		pcfg-pull-none-drv-level-14 {
+			bias-disable;
+			drive-strength = <0x0e>;
+			phandle = <0x2b6>;
+		};
+
+		pcfg-pull-none-drv-level-15 {
+			bias-disable;
+			drive-strength = <0x0f>;
+			phandle = <0x2b7>;
+		};
+
+		pcfg-pull-up-drv-level-0 {
+			bias-pull-up;
+			drive-strength = <0x00>;
+			phandle = <0x2b8>;
+		};
+
+		pcfg-pull-up-drv-level-1 {
+			bias-pull-up;
+			drive-strength = <0x01>;
+			phandle = <0x195>;
+		};
+
+		pcfg-pull-up-drv-level-2 {
+			bias-pull-up;
+			drive-strength = <0x02>;
+			phandle = <0x18e>;
+		};
+
+		pcfg-pull-up-drv-level-3 {
+			bias-pull-up;
+			drive-strength = <0x03>;
+			phandle = <0x2b9>;
+		};
+
+		pcfg-pull-up-drv-level-4 {
+			bias-pull-up;
+			drive-strength = <0x04>;
+			phandle = <0x2ba>;
+		};
+
+		pcfg-pull-up-drv-level-5 {
+			bias-pull-up;
+			drive-strength = <0x05>;
+			phandle = <0x2bb>;
+		};
+
+		pcfg-pull-up-drv-level-6 {
+			bias-pull-up;
+			drive-strength = <0x06>;
+			phandle = <0x194>;
+		};
+
+		pcfg-pull-up-drv-level-7 {
+			bias-pull-up;
+			drive-strength = <0x07>;
+			phandle = <0x2bc>;
+		};
+
+		pcfg-pull-up-drv-level-8 {
+			bias-pull-up;
+			drive-strength = <0x08>;
+			phandle = <0x2bd>;
+		};
+
+		pcfg-pull-up-drv-level-9 {
+			bias-pull-up;
+			drive-strength = <0x09>;
+			phandle = <0x2be>;
+		};
+
+		pcfg-pull-up-drv-level-10 {
+			bias-pull-up;
+			drive-strength = <0x0a>;
+			phandle = <0x2bf>;
+		};
+
+		pcfg-pull-up-drv-level-11 {
+			bias-pull-up;
+			drive-strength = <0x0b>;
+			phandle = <0x2c0>;
+		};
+
+		pcfg-pull-up-drv-level-12 {
+			bias-pull-up;
+			drive-strength = <0x0c>;
+			phandle = <0x2c1>;
+		};
+
+		pcfg-pull-up-drv-level-13 {
+			bias-pull-up;
+			drive-strength = <0x0d>;
+			phandle = <0x2c2>;
+		};
+
+		pcfg-pull-up-drv-level-14 {
+			bias-pull-up;
+			drive-strength = <0x0e>;
+			phandle = <0x2c3>;
+		};
+
+		pcfg-pull-up-drv-level-15 {
+			bias-pull-up;
+			drive-strength = <0x0f>;
+			phandle = <0x2c4>;
+		};
+
+		pcfg-pull-down-drv-level-0 {
+			bias-pull-down;
+			drive-strength = <0x00>;
+			phandle = <0x2c5>;
+		};
+
+		pcfg-pull-down-drv-level-1 {
+			bias-pull-down;
+			drive-strength = <0x01>;
+			phandle = <0x2c6>;
+		};
+
+		pcfg-pull-down-drv-level-2 {
+			bias-pull-down;
+			drive-strength = <0x02>;
+			phandle = <0x2c7>;
+		};
+
+		pcfg-pull-down-drv-level-3 {
+			bias-pull-down;
+			drive-strength = <0x03>;
+			phandle = <0x2c8>;
+		};
+
+		pcfg-pull-down-drv-level-4 {
+			bias-pull-down;
+			drive-strength = <0x04>;
+			phandle = <0x2c9>;
+		};
+
+		pcfg-pull-down-drv-level-5 {
+			bias-pull-down;
+			drive-strength = <0x05>;
+			phandle = <0x2ca>;
+		};
+
+		pcfg-pull-down-drv-level-6 {
+			bias-pull-down;
+			drive-strength = <0x06>;
+			phandle = <0x2cb>;
+		};
+
+		pcfg-pull-down-drv-level-7 {
+			bias-pull-down;
+			drive-strength = <0x07>;
+			phandle = <0x2cc>;
+		};
+
+		pcfg-pull-down-drv-level-8 {
+			bias-pull-down;
+			drive-strength = <0x08>;
+			phandle = <0x2cd>;
+		};
+
+		pcfg-pull-down-drv-level-9 {
+			bias-pull-down;
+			drive-strength = <0x09>;
+			phandle = <0x2ce>;
+		};
+
+		pcfg-pull-down-drv-level-10 {
+			bias-pull-down;
+			drive-strength = <0x0a>;
+			phandle = <0x2cf>;
+		};
+
+		pcfg-pull-down-drv-level-11 {
+			bias-pull-down;
+			drive-strength = <0x0b>;
+			phandle = <0x2d0>;
+		};
+
+		pcfg-pull-down-drv-level-12 {
+			bias-pull-down;
+			drive-strength = <0x0c>;
+			phandle = <0x2d1>;
+		};
+
+		pcfg-pull-down-drv-level-13 {
+			bias-pull-down;
+			drive-strength = <0x0d>;
+			phandle = <0x2d2>;
+		};
+
+		pcfg-pull-down-drv-level-14 {
+			bias-pull-down;
+			drive-strength = <0x0e>;
+			phandle = <0x2d3>;
+		};
+
+		pcfg-pull-down-drv-level-15 {
+			bias-pull-down;
+			drive-strength = <0x0f>;
+			phandle = <0x2d4>;
+		};
+
+		pcfg-pull-up-smt {
+			bias-pull-up;
+			input-schmitt-enable;
+			phandle = <0x2d5>;
+		};
+
+		pcfg-pull-down-smt {
+			bias-pull-down;
+			input-schmitt-enable;
+			phandle = <0x2d6>;
+		};
+
+		pcfg-pull-none-smt {
+			bias-disable;
+			input-schmitt-enable;
+			phandle = <0x191>;
+		};
+
+		pcfg-pull-none-drv-level-0-smt {
+			bias-disable;
+			drive-strength = <0x00>;
+			input-schmitt-enable;
+			phandle = <0x2d7>;
+		};
+
+		pcfg-pull-none-drv-level-1-smt {
+			bias-disable;
+			drive-strength = <0x01>;
+			input-schmitt-enable;
+			phandle = <0x190>;
+		};
+
+		pcfg-pull-none-drv-level-2-smt {
+			bias-disable;
+			drive-strength = <0x02>;
+			input-schmitt-enable;
+			phandle = <0x2d8>;
+		};
+
+		pcfg-pull-none-drv-level-3-smt {
+			bias-disable;
+			drive-strength = <0x03>;
+			input-schmitt-enable;
+			phandle = <0x2d9>;
+		};
+
+		pcfg-pull-none-drv-level-4-smt {
+			bias-disable;
+			drive-strength = <0x04>;
+			input-schmitt-enable;
+			phandle = <0x2da>;
+		};
+
+		pcfg-pull-none-drv-level-5-smt {
+			bias-disable;
+			drive-strength = <0x05>;
+			input-schmitt-enable;
+			phandle = <0x18f>;
+		};
+
+		pcfg-output-high {
+			output-high;
+			phandle = <0x2db>;
+		};
+
+		pcfg-output-high-pull-up {
+			output-high;
+			bias-pull-up;
+			phandle = <0x2dc>;
+		};
+
+		pcfg-output-high-pull-down {
+			output-high;
+			bias-pull-down;
+			phandle = <0x2dd>;
+		};
+
+		pcfg-output-high-pull-none {
+			output-high;
+			bias-disable;
+			phandle = <0x2de>;
+		};
+
+		pcfg-output-low {
+			output-low;
+			phandle = <0x2df>;
+		};
+
+		pcfg-output-low-pull-up {
+			output-low;
+			bias-pull-up;
+			phandle = <0x2e0>;
+		};
+
+		pcfg-output-low-pull-down {
+			output-low;
+			bias-pull-down;
+			phandle = <0x2e1>;
+		};
+
+		pcfg-output-low-pull-none {
+			output-low;
+			bias-disable;
+			phandle = <0x2e2>;
+		};
+
+		auddsm {
+
+			auddsm-pins {
+				rockchip,pins = <0x03 0x01 0x04 0x18d 0x03 0x02 0x04 0x18d 0x03 0x03 0x04 0x18d 0x03 0x04 0x04 0x18d>;
+				phandle = <0x131>;
+			};
+		};
+
+		bt1120 {
+
+			bt1120-pins {
+				rockchip,pins = <0x04 0x08 0x02 0x18d 0x04 0x00 0x02 0x18d 0x04 0x01 0x02 0x18d 0x04 0x02 0x02 0x18d 0x04 0x03 0x02 0x18d 0x04 0x04 0x02 0x18d 0x04 0x05 0x02 0x18d 0x04 0x06 0x02 0x18d 0x04 0x07 0x02 0x18d 0x04 0x0a 0x02 0x18d 0x04 0x0b 0x02 0x18d 0x04 0x0c 0x02 0x18d 0x04 0x0d 0x02 0x18d 0x04 0x0e 0x02 0x18d 0x04 0x0f 0x02 0x18d 0x04 0x10 0x02 0x18d 0x04 0x11 0x02 0x18d>;
+				phandle = <0x6a>;
+			};
+		};
+
+		can0 {
+
+			can0m0-pins {
+				rockchip,pins = <0x00 0x10 0x0b 0x18d 0x00 0x0f 0x0b 0x18d>;
+				phandle = <0x132>;
+			};
+
+			can0m1-pins {
+				rockchip,pins = <0x04 0x1d 0x09 0x18d 0x04 0x1c 0x09 0x18d>;
+				phandle = <0x2e3>;
+			};
+		};
+
+		can1 {
+
+			can1m0-pins {
+				rockchip,pins = <0x03 0x0d 0x09 0x18d 0x03 0x0e 0x09 0x18d>;
+				phandle = <0x2e4>;
+			};
+
+			can1m1-pins {
+				rockchip,pins = <0x04 0x0a 0x0c 0x18d 0x04 0x0b 0x0c 0x18d>;
+				phandle = <0x133>;
+			};
+		};
+
+		can2 {
+
+			can2m0-pins {
+				rockchip,pins = <0x03 0x14 0x09 0x18d 0x03 0x15 0x09 0x18d>;
+				phandle = <0x2e5>;
+			};
+
+			can2m1-pins {
+				rockchip,pins = <0x00 0x1c 0x0a 0x18d 0x00 0x1d 0x0a 0x18d>;
+				phandle = <0x134>;
+			};
+		};
+
+		cif {
+
+			cif-clk {
+				rockchip,pins = <0x04 0x0c 0x01 0x18d>;
+				phandle = <0x2e6>;
+			};
+
+			cif-dvp-clk {
+				rockchip,pins = <0x04 0x08 0x01 0x18d 0x04 0x0a 0x01 0x18d 0x04 0x0b 0x01 0x18d>;
+				phandle = <0x2e7>;
+			};
+
+			cif-dvp-bus16 {
+				rockchip,pins = <0x03 0x14 0x01 0x18d 0x03 0x15 0x01 0x18d 0x03 0x16 0x01 0x18d 0x03 0x17 0x01 0x18d 0x03 0x18 0x01 0x18d 0x03 0x19 0x01 0x18d 0x03 0x1a 0x01 0x18d 0x03 0x1b 0x01 0x18d>;
+				phandle = <0x2e8>;
+			};
+
+			cif-dvp-bus8 {
+				rockchip,pins = <0x04 0x00 0x01 0x18d 0x04 0x01 0x01 0x18d 0x04 0x02 0x01 0x18d 0x04 0x03 0x01 0x18d 0x04 0x04 0x01 0x18d 0x04 0x05 0x01 0x18d 0x04 0x06 0x01 0x18d 0x04 0x07 0x01 0x18d>;
+				phandle = <0x2e9>;
+			};
+		};
+
+		clk32k {
+
+			clk32k-in {
+				rockchip,pins = <0x00 0x0a 0x01 0x18d>;
+				phandle = <0x2ea>;
+			};
+
+			clk32k-out0 {
+				rockchip,pins = <0x00 0x0a 0x02 0x18d>;
+				phandle = <0x2eb>;
+			};
+		};
+
+		cpu {
+
+			cpu-pins {
+				rockchip,pins = <0x00 0x19 0x02 0x18d 0x00 0x1d 0x02 0x18d>;
+				phandle = <0x2ec>;
+			};
+		};
+
+		ddrphych0 {
+
+			ddrphych0-pins {
+				rockchip,pins = <0x04 0x00 0x07 0x18d 0x04 0x01 0x07 0x18d 0x04 0x02 0x07 0x18d 0x04 0x03 0x07 0x18d>;
+				phandle = <0x2ed>;
+			};
+		};
+
+		ddrphych1 {
+
+			ddrphych1-pins {
+				rockchip,pins = <0x04 0x04 0x07 0x18d 0x04 0x05 0x07 0x18d 0x04 0x06 0x07 0x18d 0x04 0x07 0x07 0x18d>;
+				phandle = <0x2ee>;
+			};
+		};
+
+		ddrphych2 {
+
+			ddrphych2-pins {
+				rockchip,pins = <0x04 0x08 0x07 0x18d 0x04 0x09 0x07 0x18d 0x04 0x0a 0x07 0x18d 0x04 0x0b 0x07 0x18d>;
+				phandle = <0x2ef>;
+			};
+		};
+
+		ddrphych3 {
+
+			ddrphych3-pins {
+				rockchip,pins = <0x04 0x0c 0x07 0x18d 0x04 0x0d 0x07 0x18d 0x04 0x0e 0x07 0x18d 0x04 0x0f 0x07 0x18d>;
+				phandle = <0x2f0>;
+			};
+		};
+
+		dp0 {
+
+			dp0m0-pins {
+				rockchip,pins = <0x04 0x0c 0x05 0x18d>;
+				phandle = <0x2f1>;
+			};
+
+			dp0m1-pins {
+				rockchip,pins = <0x00 0x14 0x0a 0x18d>;
+				phandle = <0x2f2>;
+			};
+
+			dp0m2-pins {
+				rockchip,pins = <0x01 0x00 0x05 0x18d>;
+				phandle = <0x2f3>;
+			};
+		};
+
+		dp1 {
+
+			dp1m0-pins {
+				rockchip,pins = <0x03 0x1d 0x05 0x18d>;
+				phandle = <0x2f4>;
+			};
+
+			dp1m1-pins {
+				rockchip,pins = <0x00 0x15 0x0a 0x18d>;
+				phandle = <0x2f5>;
+			};
+
+			dp1m2-pins {
+				rockchip,pins = <0x01 0x01 0x05 0x18d>;
+				phandle = <0x2f6>;
+			};
+		};
+
+		emmc {
+
+			emmc-rstnout {
+				rockchip,pins = <0x02 0x03 0x01 0x18d>;
+				phandle = <0x2f7>;
+			};
+
+			emmc-bus8 {
+				rockchip,pins = <0x02 0x18 0x01 0x18e 0x02 0x19 0x01 0x18e 0x02 0x1a 0x01 0x18e 0x02 0x1b 0x01 0x18e 0x02 0x1c 0x01 0x18e 0x02 0x1d 0x01 0x18e 0x02 0x1e 0x01 0x18e 0x02 0x1f 0x01 0x18e>;
+				phandle = <0x2f8>;
+			};
+
+			emmc-clk {
+				rockchip,pins = <0x02 0x01 0x01 0x18e>;
+				phandle = <0x2f9>;
+			};
+
+			emmc-cmd {
+				rockchip,pins = <0x02 0x00 0x01 0x18e>;
+				phandle = <0x2fa>;
+			};
+
+			emmc-data-strobe {
+				rockchip,pins = <0x02 0x02 0x01 0x18d>;
+				phandle = <0x2fb>;
+			};
+		};
+
+		eth1 {
+
+			eth1-pins {
+				rockchip,pins = <0x03 0x06 0x01 0x18d>;
+				phandle = <0x2fc>;
+			};
+		};
+
+		fspi {
+
+			fspim0-pins {
+				rockchip,pins = <0x02 0x00 0x02 0x18e 0x02 0x1e 0x02 0x18e 0x02 0x18 0x02 0x18e 0x02 0x19 0x02 0x18e 0x02 0x1a 0x02 0x18e 0x02 0x1b 0x02 0x18e>;
+				phandle = <0x10a>;
+			};
+
+			fspim0-cs1 {
+				rockchip,pins = <0x02 0x1f 0x02 0x18e>;
+				phandle = <0x2fd>;
+			};
+
+			fspim2-pins {
+				rockchip,pins = <0x03 0x05 0x05 0x18e 0x03 0x14 0x02 0x18e 0x03 0x00 0x05 0x18e 0x03 0x01 0x05 0x18e 0x03 0x02 0x05 0x18e 0x03 0x03 0x05 0x18e>;
+				phandle = <0x2fe>;
+			};
+
+			fspim2-cs1 {
+				rockchip,pins = <0x03 0x15 0x02 0x18e>;
+				phandle = <0x2ff>;
+			};
+		};
+
+		gmac1 {
+
+			gmac1-miim {
+				rockchip,pins = <0x03 0x12 0x01 0x18d 0x03 0x13 0x01 0x18d>;
+				phandle = <0x103>;
+			};
+
+			gmac1-clkinout {
+				rockchip,pins = <0x03 0x0e 0x01 0x18d>;
+				phandle = <0x300>;
+			};
+
+			gmac1-rx-bus2 {
+				rockchip,pins = <0x03 0x07 0x01 0x18d 0x03 0x08 0x01 0x18d 0x03 0x09 0x01 0x18d>;
+				phandle = <0x105>;
+			};
+
+			gmac1-tx-bus2 {
+				rockchip,pins = <0x03 0x0b 0x01 0x18d 0x03 0x0c 0x01 0x18d 0x03 0x0d 0x01 0x18d>;
+				phandle = <0x104>;
+			};
+
+			gmac1-rgmii-clk {
+				rockchip,pins = <0x03 0x05 0x01 0x18d 0x03 0x04 0x01 0x18d>;
+				phandle = <0x106>;
+			};
+
+			gmac1-rgmii-bus {
+				rockchip,pins = <0x03 0x02 0x01 0x18d 0x03 0x03 0x01 0x18d 0x03 0x00 0x01 0x18d 0x03 0x01 0x01 0x18d>;
+				phandle = <0x107>;
+			};
+
+			gmac1-ppsclk {
+				rockchip,pins = <0x03 0x11 0x01 0x18d>;
+				phandle = <0x301>;
+			};
+
+			gmac1-ppstrig {
+				rockchip,pins = <0x03 0x10 0x01 0x18d>;
+				phandle = <0x302>;
+			};
+
+			gmac1-ptp-ref-clk {
+				rockchip,pins = <0x03 0x0f 0x01 0x18d>;
+				phandle = <0x303>;
+			};
+
+			gmac1-txer {
+				rockchip,pins = <0x03 0x0a 0x01 0x18d>;
+				phandle = <0x304>;
+			};
+		};
+
+		gpu {
+
+			gpu-pins {
+				rockchip,pins = <0x00 0x15 0x02 0x18d>;
+				phandle = <0x305>;
+			};
+		};
+
+		hdmi {
+
+			hdmim0-rx-cec {
+				rockchip,pins = <0x04 0x0d 0x05 0x18d>;
+				phandle = <0x306>;
+			};
+
+			hdmim0-rx-hpdin {
+				rockchip,pins = <0x04 0x0e 0x05 0x18d>;
+				phandle = <0x307>;
+			};
+
+			hdmim0-rx-scl {
+				rockchip,pins = <0x00 0x1a 0x0b 0x18d>;
+				phandle = <0x308>;
+			};
+
+			hdmim0-rx-sda {
+				rockchip,pins = <0x00 0x19 0x0b 0x18d>;
+				phandle = <0x309>;
+			};
+
+			hdmim0-tx0-cec {
+				rockchip,pins = <0x04 0x11 0x05 0x18d>;
+				phandle = <0xee>;
+			};
+
+			hdmim0-tx0-hpd {
+				rockchip,pins = <0x01 0x05 0x05 0x18d>;
+				phandle = <0xef>;
+			};
+
+			hdmim0-tx0-scl {
+				rockchip,pins = <0x04 0x0f 0x05 0x18f>;
+				phandle = <0xf0>;
+			};
+
+			hdmim0-tx0-sda {
+				rockchip,pins = <0x04 0x10 0x05 0x190>;
+				phandle = <0xf1>;
+			};
+
+			hdmim0-tx1-hpd {
+				rockchip,pins = <0x01 0x06 0x05 0x18d>;
+				phandle = <0x30a>;
+			};
+
+			hdmim1-rx {
+				rockchip,pins = <0x03 0x19 0x05 0x18d 0x03 0x1a 0x05 0x191 0x03 0x1b 0x05 0x191 0x03 0x1c 0x05 0x18d>;
+				phandle = <0x30b>;
+			};
+
+			hdmim1-rx-cec {
+				rockchip,pins = <0x03 0x19 0x05 0x18d>;
+				phandle = <0x30c>;
+			};
+
+			hdmim1-rx-hpdin {
+				rockchip,pins = <0x03 0x1c 0x05 0x18d>;
+				phandle = <0x30d>;
+			};
+
+			hdmim1-rx-scl {
+				rockchip,pins = <0x03 0x1a 0x05 0x191>;
+				phandle = <0x30e>;
+			};
+
+			hdmim1-rx-sda {
+				rockchip,pins = <0x03 0x1b 0x05 0x191>;
+				phandle = <0x30f>;
+			};
+
+			hdmim1-tx0-cec {
+				rockchip,pins = <0x00 0x19 0x0d 0x18d>;
+				phandle = <0x310>;
+			};
+
+			hdmim1-tx0-hpd {
+				rockchip,pins = <0x03 0x1c 0x03 0x18d>;
+				phandle = <0x311>;
+			};
+
+			hdmim1-tx0-scl {
+				rockchip,pins = <0x00 0x1d 0x0b 0x18f>;
+				phandle = <0x312>;
+			};
+
+			hdmim1-tx0-sda {
+				rockchip,pins = <0x00 0x1c 0x0b 0x190>;
+				phandle = <0x313>;
+			};
+
+			hdmim1-tx1-cec {
+				rockchip,pins = <0x00 0x1a 0x0d 0x18d>;
+				phandle = <0x314>;
+			};
+
+			hdmim1-tx1-hpd {
+				rockchip,pins = <0x03 0x0f 0x05 0x18d>;
+				phandle = <0x315>;
+			};
+
+			hdmim1-tx1-scl {
+				rockchip,pins = <0x03 0x16 0x05 0x18f>;
+				phandle = <0x316>;
+			};
+
+			hdmim1-tx1-sda {
+				rockchip,pins = <0x03 0x15 0x05 0x190>;
+				phandle = <0x317>;
+			};
+
+			hdmim2-rx-cec {
+				rockchip,pins = <0x01 0x0f 0x05 0x18d>;
+				phandle = <0x318>;
+			};
+
+			hdmim2-rx-hpdin {
+				rockchip,pins = <0x01 0x0e 0x05 0x18d>;
+				phandle = <0x319>;
+			};
+
+			hdmim2-rx-scl {
+				rockchip,pins = <0x01 0x1e 0x05 0x18d>;
+				phandle = <0x31a>;
+			};
+
+			hdmim2-rx-sda {
+				rockchip,pins = <0x01 0x1f 0x05 0x18d>;
+				phandle = <0x31b>;
+			};
+
+			hdmim2-tx0-scl {
+				rockchip,pins = <0x03 0x17 0x05 0x18f>;
+				phandle = <0x31c>;
+			};
+
+			hdmim2-tx0-sda {
+				rockchip,pins = <0x03 0x18 0x05 0x190>;
+				phandle = <0x31d>;
+			};
+
+			hdmim2-tx1-cec {
+				rockchip,pins = <0x03 0x14 0x05 0x18d>;
+				phandle = <0x31e>;
+			};
+
+			hdmim2-tx1-scl {
+				rockchip,pins = <0x01 0x04 0x05 0x18f>;
+				phandle = <0x31f>;
+			};
+
+			hdmim2-tx1-sda {
+				rockchip,pins = <0x01 0x03 0x05 0x190>;
+				phandle = <0x320>;
+			};
+
+			hdmi-debug0 {
+				rockchip,pins = <0x01 0x07 0x07 0x18d>;
+				phandle = <0x321>;
+			};
+
+			hdmi-debug1 {
+				rockchip,pins = <0x01 0x08 0x07 0x18d>;
+				phandle = <0x322>;
+			};
+
+			hdmi-debug2 {
+				rockchip,pins = <0x01 0x09 0x07 0x18d>;
+				phandle = <0x323>;
+			};
+
+			hdmi-debug3 {
+				rockchip,pins = <0x01 0x0a 0x07 0x18d>;
+				phandle = <0x324>;
+			};
+
+			hdmi-debug4 {
+				rockchip,pins = <0x01 0x0b 0x07 0x18d>;
+				phandle = <0x325>;
+			};
+
+			hdmi-debug5 {
+				rockchip,pins = <0x01 0x0c 0x07 0x18d>;
+				phandle = <0x326>;
+			};
+
+			hdmi-debug6 {
+				rockchip,pins = <0x01 0x00 0x07 0x18d>;
+				phandle = <0x327>;
+			};
+		};
+
+		i2c0 {
+
+			i2c0m0-xfer {
+				rockchip,pins = <0x00 0x0b 0x02 0x191 0x00 0x06 0x02 0x191>;
+				phandle = <0x328>;
+			};
+
+			i2c0m2-xfer {
+				rockchip,pins = <0x00 0x19 0x03 0x191 0x00 0x1a 0x03 0x191>;
+				phandle = <0x6f>;
+			};
+		};
+
+		i2c1 {
+
+			i2c1m0-xfer {
+				rockchip,pins = <0x00 0x0d 0x09 0x191 0x00 0x0e 0x09 0x191>;
+				phandle = <0x329>;
+			};
+
+			i2c1m1-xfer {
+				rockchip,pins = <0x00 0x08 0x02 0x191 0x00 0x09 0x02 0x191>;
+				phandle = <0x32a>;
+			};
+
+			i2c1m2-xfer {
+				rockchip,pins = <0x00 0x1c 0x09 0x191 0x00 0x1d 0x09 0x191>;
+				phandle = <0x135>;
+			};
+
+			i2c1m3-xfer {
+				rockchip,pins = <0x02 0x1c 0x09 0x191 0x02 0x1d 0x09 0x191>;
+				phandle = <0x32b>;
+			};
+
+			i2c1m4-xfer {
+				rockchip,pins = <0x01 0x1a 0x09 0x191 0x01 0x1b 0x09 0x191>;
+				phandle = <0x32c>;
+			};
+		};
+
+		i2c2 {
+
+			i2c2m0-xfer {
+				rockchip,pins = <0x00 0x0f 0x09 0x191 0x00 0x10 0x09 0x191>;
+				phandle = <0x136>;
+			};
+
+			i2c2m2-xfer {
+				rockchip,pins = <0x02 0x03 0x09 0x191 0x02 0x02 0x09 0x191>;
+				phandle = <0x32d>;
+			};
+
+			i2c2m3-xfer {
+				rockchip,pins = <0x01 0x15 0x09 0x191 0x01 0x14 0x09 0x191>;
+				phandle = <0x32e>;
+			};
+
+			i2c2m4-xfer {
+				rockchip,pins = <0x01 0x01 0x09 0x191 0x01 0x00 0x09 0x191>;
+				phandle = <0x32f>;
+			};
+		};
+
+		i2c3 {
+
+			i2c3m0-xfer {
+				rockchip,pins = <0x01 0x11 0x09 0x191 0x01 0x10 0x09 0x191>;
+				phandle = <0x13c>;
+			};
+
+			i2c3m1-xfer {
+				rockchip,pins = <0x03 0x0f 0x09 0x191 0x03 0x10 0x09 0x191>;
+				phandle = <0x330>;
+			};
+
+			i2c3m2-xfer {
+				rockchip,pins = <0x04 0x04 0x09 0x191 0x04 0x05 0x09 0x191>;
+				phandle = <0x331>;
+			};
+
+			i2c3m4-xfer {
+				rockchip,pins = <0x04 0x18 0x09 0x191 0x04 0x19 0x09 0x191>;
+				phandle = <0x332>;
+			};
+		};
+
+		i2c4 {
+
+			i2c4m0-xfer {
+				rockchip,pins = <0x03 0x06 0x09 0x191 0x03 0x05 0x09 0x191>;
+				phandle = <0x13d>;
+			};
+
+			i2c4m2-xfer {
+				rockchip,pins = <0x00 0x15 0x09 0x191 0x00 0x14 0x09 0x191>;
+				phandle = <0x333>;
+			};
+
+			i2c4m3-xfer {
+				rockchip,pins = <0x01 0x03 0x09 0x191 0x01 0x02 0x09 0x191>;
+				phandle = <0x334>;
+			};
+
+			i2c4m4-xfer {
+				rockchip,pins = <0x01 0x17 0x09 0x191 0x01 0x16 0x09 0x191>;
+				phandle = <0x335>;
+			};
+		};
+
+		i2c5 {
+
+			i2c5m0-xfer {
+				rockchip,pins = <0x03 0x17 0x09 0x191 0x03 0x18 0x09 0x191>;
+				phandle = <0x336>;
+			};
+
+			i2c5m1-xfer {
+				rockchip,pins = <0x04 0x0e 0x09 0x191 0x04 0x0f 0x09 0x191>;
+				phandle = <0x337>;
+			};
+
+			i2c5m2-xfer {
+				rockchip,pins = <0x04 0x06 0x09 0x191 0x04 0x07 0x09 0x191>;
+				phandle = <0x338>;
+			};
+
+			i2c5m3-xfer {
+				rockchip,pins = <0x01 0x0e 0x09 0x191 0x01 0x0f 0x09 0x191>;
+				phandle = <0x13e>;
+			};
+		};
+
+		i2c6 {
+
+			i2c6m0-xfer {
+				rockchip,pins = <0x00 0x18 0x09 0x191 0x00 0x17 0x09 0x191>;
+				phandle = <0x339>;
+			};
+
+			i2c6m1-xfer {
+				rockchip,pins = <0x01 0x13 0x09 0x191 0x01 0x12 0x09 0x191>;
+				phandle = <0x33a>;
+			};
+
+			i2c6m3-xfer {
+				rockchip,pins = <0x04 0x09 0x09 0x191 0x04 0x08 0x09 0x191>;
+				phandle = <0x16b>;
+			};
+
+			i2c6m4-xfer {
+				rockchip,pins = <0x03 0x01 0x09 0x191 0x03 0x00 0x09 0x191>;
+				phandle = <0x33b>;
+			};
+		};
+
+		i2c7 {
+
+			i2c7m0-xfer {
+				rockchip,pins = <0x01 0x18 0x09 0x191 0x01 0x19 0x09 0x191>;
+				phandle = <0x173>;
+			};
+
+			i2c7m2-xfer {
+				rockchip,pins = <0x03 0x1a 0x09 0x191 0x03 0x1b 0x09 0x191>;
+				phandle = <0x33c>;
+			};
+
+			i2c7m3-xfer {
+				rockchip,pins = <0x04 0x0a 0x09 0x191 0x04 0x0b 0x09 0x191>;
+				phandle = <0x33d>;
+			};
+		};
+
+		i2c8 {
+
+			i2c8m0-xfer {
+				rockchip,pins = <0x04 0x1a 0x09 0x191 0x04 0x1b 0x09 0x191>;
+				phandle = <0x17d>;
+			};
+
+			i2c8m2-xfer {
+				rockchip,pins = <0x01 0x1e 0x09 0x191 0x01 0x1f 0x09 0x191>;
+				phandle = <0x33e>;
+			};
+
+			i2c8m3-xfer {
+				rockchip,pins = <0x04 0x10 0x09 0x191 0x04 0x11 0x09 0x191>;
+				phandle = <0x33f>;
+			};
+
+			i2c8m4-xfer {
+				rockchip,pins = <0x03 0x12 0x09 0x191 0x03 0x13 0x09 0x191>;
+				phandle = <0x340>;
+			};
+		};
+
+		i2s0 {
+
+			i2s0-lrck {
+				rockchip,pins = <0x01 0x15 0x01 0x18d>;
+				phandle = <0x113>;
+			};
+
+			i2s0-mclk {
+				rockchip,pins = <0x01 0x12 0x01 0x18d>;
+				phandle = <0x341>;
+			};
+
+			i2s0-sclk {
+				rockchip,pins = <0x01 0x13 0x01 0x18d>;
+				phandle = <0x114>;
+			};
+
+			i2s0-sdi0 {
+				rockchip,pins = <0x01 0x1c 0x02 0x18d>;
+				phandle = <0x115>;
+			};
+
+			i2s0-sdi1 {
+				rockchip,pins = <0x01 0x1b 0x02 0x18d>;
+				phandle = <0x342>;
+			};
+
+			i2s0-sdi2 {
+				rockchip,pins = <0x01 0x1a 0x02 0x18d>;
+				phandle = <0x343>;
+			};
+
+			i2s0-sdi3 {
+				rockchip,pins = <0x01 0x19 0x02 0x18d>;
+				phandle = <0x344>;
+			};
+
+			i2s0-sdo0 {
+				rockchip,pins = <0x01 0x17 0x01 0x18d>;
+				phandle = <0x116>;
+			};
+
+			i2s0-sdo1 {
+				rockchip,pins = <0x01 0x18 0x01 0x18d>;
+				phandle = <0x345>;
+			};
+
+			i2s0-sdo2 {
+				rockchip,pins = <0x01 0x19 0x01 0x18d>;
+				phandle = <0x346>;
+			};
+
+			i2s0-sdo3 {
+				rockchip,pins = <0x01 0x1a 0x01 0x18d>;
+				phandle = <0x347>;
+			};
+		};
+
+		i2s1 {
+
+			i2s1m0-lrck {
+				rockchip,pins = <0x04 0x02 0x03 0x18d>;
+				phandle = <0x118>;
+			};
+
+			i2s1m0-mclk {
+				rockchip,pins = <0x04 0x00 0x03 0x18d>;
+				phandle = <0x16c>;
+			};
+
+			i2s1m0-sclk {
+				rockchip,pins = <0x04 0x01 0x03 0x18d>;
+				phandle = <0x117>;
+			};
+
+			i2s1m0-sdi0 {
+				rockchip,pins = <0x04 0x05 0x03 0x18d>;
+				phandle = <0x348>;
+			};
+
+			i2s1m0-sdi1 {
+				rockchip,pins = <0x04 0x06 0x03 0x18d>;
+				phandle = <0x119>;
+			};
+
+			i2s1m0-sdi2 {
+				rockchip,pins = <0x04 0x07 0x03 0x18d>;
+				phandle = <0x349>;
+			};
+
+			i2s1m0-sdi3 {
+				rockchip,pins = <0x04 0x08 0x03 0x18d>;
+				phandle = <0x34a>;
+			};
+
+			i2s1m0-sdo0 {
+				rockchip,pins = <0x04 0x09 0x03 0x18d>;
+				phandle = <0x34b>;
+			};
+
+			i2s1m0-sdo1 {
+				rockchip,pins = <0x04 0x0a 0x03 0x18d>;
+				phandle = <0x34c>;
+			};
+
+			i2s1m0-sdo2 {
+				rockchip,pins = <0x04 0x0b 0x03 0x18d>;
+				phandle = <0x34d>;
+			};
+
+			i2s1m0-sdo3 {
+				rockchip,pins = <0x04 0x0c 0x03 0x18d>;
+				phandle = <0x11a>;
+			};
+
+			i2s1m1-lrck {
+				rockchip,pins = <0x00 0x0f 0x01 0x18d>;
+				phandle = <0x34e>;
+			};
+
+			i2s1m1-mclk {
+				rockchip,pins = <0x00 0x0d 0x01 0x18d>;
+				phandle = <0x34f>;
+			};
+
+			i2s1m1-sclk {
+				rockchip,pins = <0x00 0x0e 0x01 0x18d>;
+				phandle = <0x350>;
+			};
+
+			i2s1m1-sdi0 {
+				rockchip,pins = <0x00 0x15 0x01 0x18d>;
+				phandle = <0x351>;
+			};
+
+			i2s1m1-sdi1 {
+				rockchip,pins = <0x00 0x16 0x01 0x18d>;
+				phandle = <0x352>;
+			};
+
+			i2s1m1-sdi2 {
+				rockchip,pins = <0x00 0x17 0x01 0x18d>;
+				phandle = <0x353>;
+			};
+
+			i2s1m1-sdi3 {
+				rockchip,pins = <0x00 0x18 0x01 0x18d>;
+				phandle = <0x354>;
+			};
+
+			i2s1m1-sdo0 {
+				rockchip,pins = <0x00 0x19 0x01 0x18d>;
+				phandle = <0x355>;
+			};
+
+			i2s1m1-sdo1 {
+				rockchip,pins = <0x00 0x1a 0x01 0x18d>;
+				phandle = <0x356>;
+			};
+
+			i2s1m1-sdo2 {
+				rockchip,pins = <0x00 0x1c 0x01 0x18d>;
+				phandle = <0x357>;
+			};
+
+			i2s1m1-sdo3 {
+				rockchip,pins = <0x00 0x1d 0x01 0x18d>;
+				phandle = <0x358>;
+			};
+		};
+
+		i2s2 {
+
+			i2s2m1-lrck {
+				rockchip,pins = <0x03 0x0e 0x03 0x18d>;
+				phandle = <0x11b>;
+			};
+
+			i2s2m1-mclk {
+				rockchip,pins = <0x03 0x0c 0x03 0x18d>;
+				phandle = <0x359>;
+			};
+
+			i2s2m1-sclk {
+				rockchip,pins = <0x03 0x0d 0x03 0x18d>;
+				phandle = <0x11c>;
+			};
+
+			i2s2m1-sdi {
+				rockchip,pins = <0x03 0x0a 0x03 0x18d>;
+				phandle = <0x11d>;
+			};
+
+			i2s2m1-sdo {
+				rockchip,pins = <0x03 0x0b 0x03 0x18d>;
+				phandle = <0x11e>;
+			};
+		};
+
+		i2s3 {
+
+			i2s3-lrck {
+				rockchip,pins = <0x03 0x02 0x03 0x18d>;
+				phandle = <0x11f>;
+			};
+
+			i2s3-mclk {
+				rockchip,pins = <0x03 0x00 0x03 0x18d>;
+				phandle = <0x35a>;
+			};
+
+			i2s3-sclk {
+				rockchip,pins = <0x03 0x01 0x03 0x18d>;
+				phandle = <0x120>;
+			};
+
+			i2s3-sdi {
+				rockchip,pins = <0x03 0x04 0x03 0x18d>;
+				phandle = <0x121>;
+			};
+
+			i2s3-sdo {
+				rockchip,pins = <0x03 0x03 0x03 0x18d>;
+				phandle = <0x122>;
+			};
+		};
+
+		jtag {
+
+			jtagm0-pins {
+				rockchip,pins = <0x04 0x1a 0x05 0x18d 0x04 0x1b 0x05 0x18d>;
+				phandle = <0x35b>;
+			};
+
+			jtagm1-pins {
+				rockchip,pins = <0x04 0x18 0x05 0x18d 0x04 0x19 0x05 0x18d>;
+				phandle = <0x35c>;
+			};
+
+			jtagm2-pins {
+				rockchip,pins = <0x00 0x0d 0x02 0x18d 0x00 0x0e 0x02 0x18d>;
+				phandle = <0x35d>;
+			};
+		};
+
+		litcpu {
+
+			litcpu-pins {
+				rockchip,pins = <0x00 0x1b 0x01 0x18d>;
+				phandle = <0x35e>;
+			};
+		};
+
+		mcu {
+
+			mcum0-pins {
+				rockchip,pins = <0x04 0x1c 0x05 0x18d 0x04 0x1d 0x05 0x18d>;
+				phandle = <0x35f>;
+			};
+
+			mcum1-pins {
+				rockchip,pins = <0x03 0x1c 0x06 0x18d 0x03 0x1d 0x06 0x18d>;
+				phandle = <0x360>;
+			};
+		};
+
+		mipi {
+
+			mipim0-camera0-clk {
+				rockchip,pins = <0x04 0x09 0x01 0x18d>;
+				phandle = <0x361>;
+			};
+
+			mipim0-camera1-clk {
+				rockchip,pins = <0x01 0x0e 0x02 0x18d>;
+				phandle = <0x362>;
+			};
+
+			mipim0-camera2-clk {
+				rockchip,pins = <0x01 0x0f 0x02 0x18d>;
+				phandle = <0x363>;
+			};
+
+			mipim0-camera3-clk {
+				rockchip,pins = <0x01 0x1e 0x02 0x18d>;
+				phandle = <0x174>;
+			};
+
+			mipim0-camera4-clk {
+				rockchip,pins = <0x01 0x1f 0x02 0x18d>;
+				phandle = <0x137>;
+			};
+
+			mipim1-camera0-clk {
+				rockchip,pins = <0x03 0x05 0x04 0x18d>;
+				phandle = <0x364>;
+			};
+
+			mipim1-camera1-clk {
+				rockchip,pins = <0x03 0x06 0x04 0x18d>;
+				phandle = <0x365>;
+			};
+
+			mipim1-camera2-clk {
+				rockchip,pins = <0x03 0x07 0x04 0x18d>;
+				phandle = <0x366>;
+			};
+
+			mipim1-camera3-clk {
+				rockchip,pins = <0x03 0x08 0x04 0x18d>;
+				phandle = <0x367>;
+			};
+
+			mipim1-camera4-clk {
+				rockchip,pins = <0x03 0x09 0x04 0x18d>;
+				phandle = <0x368>;
+			};
+
+			mipi-te0 {
+				rockchip,pins = <0x03 0x12 0x02 0x18d>;
+				phandle = <0x369>;
+			};
+
+			mipi-te1 {
+				rockchip,pins = <0x03 0x13 0x02 0x18d>;
+				phandle = <0x36a>;
+			};
+		};
+
+		npu {
+
+			npu-pins {
+				rockchip,pins = <0x00 0x16 0x02 0x18d>;
+				phandle = <0x36b>;
+			};
+		};
+
+		pcie20x1 {
+
+			pcie20x1m0-pins {
+				rockchip,pins = <0x03 0x17 0x04 0x18d 0x03 0x19 0x04 0x18d 0x03 0x18 0x04 0x18d>;
+				phandle = <0x36c>;
+			};
+
+			pcie20x1m1-pins {
+				rockchip,pins = <0x04 0x0f 0x04 0x18d 0x04 0x11 0x04 0x18d 0x04 0x10 0x04 0x18d>;
+				phandle = <0x36d>;
+			};
+
+			pcie20x1-2-button-rstn {
+				rockchip,pins = <0x04 0x0b 0x04 0x18d>;
+				phandle = <0x36e>;
+			};
+		};
+
+		pcie30phy {
+
+			pcie30phy-pins {
+				rockchip,pins = <0x01 0x14 0x04 0x18d 0x01 0x19 0x04 0x18d>;
+				phandle = <0x36f>;
+			};
+		};
+
+		pcie30x1 {
+
+			pcie30x1m0-pins {
+				rockchip,pins = <0x00 0x10 0x0c 0x18d 0x00 0x15 0x0c 0x18d 0x00 0x14 0x0c 0x18d 0x00 0x0d 0x0c 0x18d 0x00 0x0f 0x0c 0x18d 0x00 0x0e 0x0c 0x18d>;
+				phandle = <0x370>;
+			};
+
+			pcie30x1m1-pins {
+				rockchip,pins = <0x04 0x03 0x04 0x18d 0x04 0x05 0x04 0x18d 0x04 0x04 0x04 0x18d 0x04 0x00 0x04 0x18d 0x04 0x02 0x04 0x18d 0x04 0x01 0x04 0x18d>;
+				phandle = <0x371>;
+			};
+
+			pcie30x1m2-pins {
+				rockchip,pins = <0x01 0x0d 0x04 0x18d 0x01 0x0c 0x04 0x18d 0x01 0x0b 0x04 0x18d 0x01 0x00 0x04 0x18d 0x01 0x07 0x04 0x18d 0x01 0x01 0x04 0x18d>;
+				phandle = <0x372>;
+			};
+
+			pcie30x1-0-button-rstn {
+				rockchip,pins = <0x04 0x09 0x04 0x18d>;
+				phandle = <0x373>;
+			};
+
+			pcie30x1-1-button-rstn {
+				rockchip,pins = <0x04 0x0a 0x04 0x18d>;
+				phandle = <0x374>;
+			};
+		};
+
+		pcie30x2 {
+
+			pcie30x2m0-pins {
+				rockchip,pins = <0x00 0x19 0x0c 0x18d 0x00 0x1c 0x0c 0x18d 0x00 0x1a 0x0c 0x18d>;
+				phandle = <0x375>;
+			};
+
+			pcie30x2m1-pins {
+				rockchip,pins = <0x04 0x06 0x04 0x18d 0x04 0x08 0x04 0x18d 0x04 0x07 0x04 0x18d>;
+				phandle = <0x376>;
+			};
+
+			pcie30x2m2-pins {
+				rockchip,pins = <0x03 0x1a 0x04 0x18d 0x03 0x1c 0x04 0x18d 0x03 0x1b 0x04 0x18d>;
+				phandle = <0x377>;
+			};
+
+			pcie30x2m3-pins {
+				rockchip,pins = <0x01 0x1f 0x04 0x18d 0x01 0x0f 0x04 0x18d 0x01 0x0e 0x04 0x18d>;
+				phandle = <0x378>;
+			};
+
+			pcie30x2-button-rstn {
+				rockchip,pins = <0x03 0x11 0x04 0x18d>;
+				phandle = <0x379>;
+			};
+		};
+
+		pcie30x4 {
+
+			pcie30x4m0-pins {
+				rockchip,pins = <0x00 0x16 0x0c 0x18d 0x00 0x18 0x0c 0x18d 0x00 0x17 0x0c 0x18d>;
+				phandle = <0x37a>;
+			};
+
+			pcie30x4m1-pins {
+				rockchip,pins = <0x04 0x0c 0x04 0x18d 0x04 0x0e 0x04 0x18d 0x04 0x0d 0x04 0x18d>;
+				phandle = <0x37b>;
+			};
+
+			pcie30x4m2-pins {
+				rockchip,pins = <0x03 0x14 0x04 0x18d 0x03 0x16 0x04 0x18d 0x03 0x15 0x04 0x18d>;
+				phandle = <0x37c>;
+			};
+
+			pcie30x4m3-pins {
+				rockchip,pins = <0x01 0x08 0x04 0x18d 0x01 0x0a 0x04 0x18d 0x01 0x09 0x04 0x18d>;
+				phandle = <0x37d>;
+			};
+
+			pcie30x4-button-rstn {
+				rockchip,pins = <0x03 0x1d 0x04 0x18d>;
+				phandle = <0x37e>;
+			};
+		};
+
+		pdm0 {
+
+			pdm0m0-clk {
+				rockchip,pins = <0x01 0x16 0x03 0x18d>;
+				phandle = <0x123>;
+			};
+
+			pdm0m0-clk1 {
+				rockchip,pins = <0x01 0x14 0x03 0x18d>;
+				phandle = <0x124>;
+			};
+
+			pdm0m0-sdi0 {
+				rockchip,pins = <0x01 0x1d 0x03 0x18d>;
+				phandle = <0x125>;
+			};
+
+			pdm0m0-sdi1 {
+				rockchip,pins = <0x01 0x19 0x03 0x18d>;
+				phandle = <0x126>;
+			};
+
+			pdm0m0-sdi2 {
+				rockchip,pins = <0x01 0x1a 0x03 0x18d>;
+				phandle = <0x127>;
+			};
+
+			pdm0m0-sdi3 {
+				rockchip,pins = <0x01 0x1b 0x03 0x18d>;
+				phandle = <0x128>;
+			};
+
+			pdm0m1-clk {
+				rockchip,pins = <0x00 0x10 0x02 0x18d>;
+				phandle = <0x37f>;
+			};
+
+			pdm0m1-clk1 {
+				rockchip,pins = <0x00 0x14 0x02 0x18d>;
+				phandle = <0x380>;
+			};
+
+			pdm0m1-sdi0 {
+				rockchip,pins = <0x00 0x17 0x02 0x18d>;
+				phandle = <0x381>;
+			};
+
+			pdm0m1-sdi1 {
+				rockchip,pins = <0x00 0x18 0x02 0x18d>;
+				phandle = <0x382>;
+			};
+
+			pdm0m1-sdi2 {
+				rockchip,pins = <0x00 0x1c 0x02 0x18d>;
+				phandle = <0x383>;
+			};
+
+			pdm0m1-sdi3 {
+				rockchip,pins = <0x00 0x1e 0x02 0x18d>;
+				phandle = <0x384>;
+			};
+		};
+
+		pdm1 {
+
+			pdm1m0-clk {
+				rockchip,pins = <0x04 0x1d 0x02 0x18d>;
+				phandle = <0x129>;
+			};
+
+			pdm1m0-clk1 {
+				rockchip,pins = <0x04 0x1c 0x02 0x18d>;
+				phandle = <0x12a>;
+			};
+
+			pdm1m0-sdi0 {
+				rockchip,pins = <0x04 0x1b 0x02 0x18d>;
+				phandle = <0x12b>;
+			};
+
+			pdm1m0-sdi1 {
+				rockchip,pins = <0x04 0x1a 0x02 0x18d>;
+				phandle = <0x12c>;
+			};
+
+			pdm1m0-sdi2 {
+				rockchip,pins = <0x04 0x19 0x02 0x18d>;
+				phandle = <0x12d>;
+			};
+
+			pdm1m0-sdi3 {
+				rockchip,pins = <0x04 0x18 0x02 0x18d>;
+				phandle = <0x12e>;
+			};
+
+			pdm1m1-clk {
+				rockchip,pins = <0x01 0x0c 0x02 0x18d>;
+				phandle = <0x385>;
+			};
+
+			pdm1m1-clk1 {
+				rockchip,pins = <0x01 0x0b 0x02 0x18d>;
+				phandle = <0x386>;
+			};
+
+			pdm1m1-sdi0 {
+				rockchip,pins = <0x01 0x07 0x02 0x18d>;
+				phandle = <0x387>;
+			};
+
+			pdm1m1-sdi1 {
+				rockchip,pins = <0x01 0x08 0x02 0x18d>;
+				phandle = <0x388>;
+			};
+
+			pdm1m1-sdi2 {
+				rockchip,pins = <0x01 0x09 0x02 0x18d>;
+				phandle = <0x389>;
+			};
+
+			pdm1m1-sdi3 {
+				rockchip,pins = <0x01 0x0a 0x02 0x18d>;
+				phandle = <0x38a>;
+			};
+		};
+
+		pmic {
+
+			pmic-pins {
+				rockchip,pins = <0x00 0x07 0x00 0x192 0x00 0x02 0x01 0x193 0x00 0x03 0x01 0x18d 0x00 0x11 0x01 0x18d 0x00 0x12 0x01 0x18d 0x00 0x13 0x01 0x18d 0x00 0x1e 0x01 0x18d>;
+				phandle = <0x148>;
+			};
+		};
+
+		pmu {
+
+			pmu-pins {
+				rockchip,pins = <0x00 0x05 0x03 0x18d>;
+				phandle = <0x38b>;
+			};
+		};
+
+		pwm0 {
+
+			pwm0m0-pins {
+				rockchip,pins = <0x00 0x0f 0x03 0x18d>;
+				phandle = <0x38c>;
+			};
+
+			pwm0m1-pins {
+				rockchip,pins = <0x01 0x1a 0x0b 0x18d>;
+				phandle = <0x73>;
+			};
+
+			pwm0m2-pins {
+				rockchip,pins = <0x01 0x02 0x0b 0x18d>;
+				phandle = <0x38d>;
+			};
+		};
+
+		pwm1 {
+
+			pwm1m0-pins {
+				rockchip,pins = <0x00 0x10 0x03 0x18d>;
+				phandle = <0x38e>;
+			};
+
+			pwm1m1-pins {
+				rockchip,pins = <0x01 0x1b 0x0b 0x18d>;
+				phandle = <0x74>;
+			};
+
+			pwm1m2-pins {
+				rockchip,pins = <0x01 0x03 0x0b 0x18d>;
+				phandle = <0x38f>;
+			};
+		};
+
+		pwm2 {
+
+			pwm2m0-pins {
+				rockchip,pins = <0x00 0x14 0x03 0x18d>;
+				phandle = <0x75>;
+			};
+
+			pwm2m1-pins {
+				rockchip,pins = <0x03 0x09 0x0b 0x18d>;
+				phandle = <0x390>;
+			};
+		};
+
+		pwm3 {
+
+			pwm3m0-pins {
+				rockchip,pins = <0x00 0x1c 0x03 0x18d>;
+				phandle = <0x391>;
+			};
+
+			pwm3m1-pins {
+				rockchip,pins = <0x03 0x0a 0x0b 0x18d>;
+				phandle = <0x392>;
+			};
+
+			pwm3m2-pins {
+				rockchip,pins = <0x01 0x12 0x0b 0x18d>;
+				phandle = <0x76>;
+			};
+
+			pwm3m3-pins {
+				rockchip,pins = <0x01 0x07 0x0b 0x18d>;
+				phandle = <0x393>;
+			};
+		};
+
+		pwm4 {
+
+			pwm4m0-pins {
+				rockchip,pins = <0x00 0x15 0x0b 0x18d>;
+				phandle = <0x15c>;
+			};
+		};
+
+		pwm5 {
+
+			pwm5m0-pins {
+				rockchip,pins = <0x00 0x09 0x03 0x18d>;
+				phandle = <0x15d>;
+			};
+
+			pwm5m1-pins {
+				rockchip,pins = <0x00 0x16 0x0b 0x18d>;
+				phandle = <0x394>;
+			};
+		};
+
+		pwm6 {
+
+			pwm6m0-pins {
+				rockchip,pins = <0x00 0x17 0x0b 0x18d>;
+				phandle = <0x15e>;
+			};
+
+			pwm6m1-pins {
+				rockchip,pins = <0x04 0x11 0x0b 0x18d>;
+				phandle = <0x395>;
+			};
+		};
+
+		pwm7 {
+
+			pwm7m0-pins {
+				rockchip,pins = <0x00 0x18 0x0b 0x18d>;
+				phandle = <0x15f>;
+			};
+
+			pwm7m1-pins {
+				rockchip,pins = <0x04 0x1c 0x0b 0x18d>;
+				phandle = <0x396>;
+			};
+
+			pwm7m2-pins {
+				rockchip,pins = <0x01 0x13 0x0b 0x18d>;
+				phandle = <0x397>;
+			};
+		};
+
+		pwm8 {
+
+			pwm8m0-pins {
+				rockchip,pins = <0x03 0x07 0x0b 0x18d>;
+				phandle = <0x160>;
+			};
+
+			pwm8m1-pins {
+				rockchip,pins = <0x04 0x18 0x0b 0x18d>;
+				phandle = <0x398>;
+			};
+
+			pwm8m2-pins {
+				rockchip,pins = <0x03 0x18 0x0b 0x18d>;
+				phandle = <0x399>;
+			};
+		};
+
+		pwm9 {
+
+			pwm9m0-pins {
+				rockchip,pins = <0x03 0x08 0x0b 0x18d>;
+				phandle = <0x161>;
+			};
+
+			pwm9m1-pins {
+				rockchip,pins = <0x04 0x19 0x0b 0x18d>;
+				phandle = <0x39a>;
+			};
+
+			pwm9m2-pins {
+				rockchip,pins = <0x03 0x19 0x0b 0x18d>;
+				phandle = <0x39b>;
+			};
+		};
+
+		pwm10 {
+
+			pwm10m0-pins {
+				rockchip,pins = <0x03 0x00 0x0b 0x18d>;
+				phandle = <0x162>;
+			};
+
+			pwm10m1-pins {
+				rockchip,pins = <0x04 0x1b 0x0b 0x18d>;
+				phandle = <0x39c>;
+			};
+
+			pwm10m2-pins {
+				rockchip,pins = <0x03 0x1b 0x0b 0x18d>;
+				phandle = <0x39d>;
+			};
+		};
+
+		pwm11 {
+
+			pwm11m0-pins {
+				rockchip,pins = <0x03 0x01 0x0b 0x18d>;
+				phandle = <0x163>;
+			};
+
+			pwm11m1-pins {
+				rockchip,pins = <0x04 0x0c 0x0b 0x18d>;
+				phandle = <0x39e>;
+			};
+
+			pwm11m2-pins {
+				rockchip,pins = <0x01 0x14 0x0b 0x18d>;
+				phandle = <0x39f>;
+			};
+
+			pwm11m3-pins {
+				rockchip,pins = <0x03 0x1d 0x0b 0x18d>;
+				phandle = <0x3a0>;
+			};
+		};
+
+		pwm12 {
+
+			pwm12m0-pins {
+				rockchip,pins = <0x03 0x0d 0x0b 0x18d>;
+				phandle = <0x164>;
+			};
+
+			pwm12m1-pins {
+				rockchip,pins = <0x04 0x0d 0x0b 0x18d>;
+				phandle = <0x3a1>;
+			};
+		};
+
+		pwm13 {
+
+			pwm13m0-pins {
+				rockchip,pins = <0x03 0x0e 0x0b 0x18d>;
+				phandle = <0x3a2>;
+			};
+
+			pwm13m1-pins {
+				rockchip,pins = <0x04 0x0e 0x0b 0x18d>;
+				phandle = <0x3a3>;
+			};
+
+			pwm13m2-pins {
+				rockchip,pins = <0x01 0x0f 0x0b 0x18d>;
+				phandle = <0x165>;
+			};
+		};
+
+		pwm14 {
+
+			pwm14m0-pins {
+				rockchip,pins = <0x03 0x12 0x0b 0x18d>;
+				phandle = <0x3a4>;
+			};
+
+			pwm14m1-pins {
+				rockchip,pins = <0x04 0x0a 0x0b 0x18d>;
+				phandle = <0x166>;
+			};
+
+			pwm14m2-pins {
+				rockchip,pins = <0x01 0x1e 0x0b 0x18d>;
+				phandle = <0x3a5>;
+			};
+		};
+
+		pwm15 {
+
+			pwm15m0-pins {
+				rockchip,pins = <0x03 0x13 0x0b 0x18d>;
+				phandle = <0x3a6>;
+			};
+
+			pwm15m1-pins {
+				rockchip,pins = <0x04 0x0b 0x0b 0x18d>;
+				phandle = <0x3a7>;
+			};
+
+			pwm15m2-pins {
+				rockchip,pins = <0x01 0x16 0x0b 0x18d>;
+				phandle = <0x167>;
+			};
+
+			pwm15m3-pins {
+				rockchip,pins = <0x01 0x1f 0x0b 0x18d>;
+				phandle = <0x3a8>;
+			};
+		};
+
+		refclk {
+
+			refclk-pins {
+				rockchip,pins = <0x00 0x00 0x01 0x18d>;
+				phandle = <0x3a9>;
+			};
+		};
+
+		sata {
+
+			sata-pins {
+				rockchip,pins = <0x00 0x16 0x0d 0x18d 0x00 0x1c 0x0d 0x18d 0x00 0x1d 0x0d 0x18d>;
+				phandle = <0x3aa>;
+			};
+
+			sata-reset {
+				rockchip,pins = <0x03 0x19 0x00 0x192>;
+				phandle = <0x109>;
+			};
+		};
+
+		sata0 {
+
+			sata0m0-pins {
+				rockchip,pins = <0x04 0x0e 0x06 0x18d>;
+				phandle = <0x3ab>;
+			};
+
+			sata0m1-pins {
+				rockchip,pins = <0x01 0x0b 0x06 0x18d>;
+				phandle = <0x3ac>;
+			};
+		};
+
+		sata1 {
+
+			sata1m0-pins {
+				rockchip,pins = <0x04 0x0d 0x06 0x18d>;
+				phandle = <0x3ad>;
+			};
+
+			sata1m1-pins {
+				rockchip,pins = <0x01 0x01 0x06 0x18d>;
+				phandle = <0x3ae>;
+			};
+		};
+
+		sata2 {
+
+			sata2m0-pins {
+				rockchip,pins = <0x04 0x09 0x06 0x18d>;
+				phandle = <0x3af>;
+			};
+
+			sata2m1-pins {
+				rockchip,pins = <0x01 0x0f 0x06 0x18d>;
+				phandle = <0x3b0>;
+			};
+		};
+
+		sdio {
+
+			sdiom1-pins {
+				rockchip,pins = <0x03 0x05 0x02 0x18d 0x03 0x04 0x02 0x192 0x03 0x00 0x02 0x192 0x03 0x01 0x02 0x192 0x03 0x02 0x02 0x192 0x03 0x03 0x02 0x192>;
+				phandle = <0x111>;
+			};
+		};
+
+		sdmmc {
+
+			sdmmc-bus4 {
+				rockchip,pins = <0x04 0x18 0x01 0x18e 0x04 0x19 0x01 0x18e 0x04 0x1a 0x01 0x18e 0x04 0x1b 0x01 0x18e>;
+				phandle = <0x10e>;
+			};
+
+			sdmmc-clk {
+				rockchip,pins = <0x04 0x1d 0x01 0x18e>;
+				phandle = <0x10b>;
+			};
+
+			sdmmc-cmd {
+				rockchip,pins = <0x04 0x1c 0x01 0x18e>;
+				phandle = <0x10c>;
+			};
+
+			sdmmc-det {
+				rockchip,pins = <0x00 0x04 0x01 0x192>;
+				phandle = <0x10d>;
+			};
+
+			sdmmc-pwren {
+				rockchip,pins = <0x00 0x05 0x02 0x18d>;
+				phandle = <0x3b1>;
+			};
+		};
+
+		spdif0 {
+
+			spdif0m0-tx {
+				rockchip,pins = <0x01 0x0e 0x03 0x18d>;
+				phandle = <0x12f>;
+			};
+
+			spdif0m1-tx {
+				rockchip,pins = <0x04 0x0c 0x06 0x18d>;
+				phandle = <0x3b2>;
+			};
+		};
+
+		spdif1 {
+
+			spdif1m0-tx {
+				rockchip,pins = <0x01 0x0f 0x03 0x18d>;
+				phandle = <0x130>;
+			};
+
+			spdif1m1-tx {
+				rockchip,pins = <0x04 0x09 0x02 0x18d>;
+				phandle = <0x3b3>;
+			};
+
+			spdif1m2-tx {
+				rockchip,pins = <0x04 0x11 0x03 0x18d>;
+				phandle = <0x3b4>;
+			};
+		};
+
+		spi0 {
+
+			spi0m0-pins {
+				rockchip,pins = <0x00 0x16 0x08 0x194 0x00 0x17 0x08 0x194 0x00 0x10 0x08 0x194>;
+				phandle = <0x141>;
+			};
+
+			spi0m0-cs0 {
+				rockchip,pins = <0x00 0x19 0x08 0x194>;
+				phandle = <0x13f>;
+			};
+
+			spi0m0-cs1 {
+				rockchip,pins = <0x00 0x0f 0x08 0x194>;
+				phandle = <0x140>;
+			};
+
+			spi0m1-pins {
+				rockchip,pins = <0x04 0x02 0x08 0x194 0x04 0x00 0x08 0x194 0x04 0x01 0x08 0x194>;
+				phandle = <0x3b5>;
+			};
+
+			spi0m1-cs0 {
+				rockchip,pins = <0x04 0x0a 0x08 0x194>;
+				phandle = <0x3b6>;
+			};
+
+			spi0m1-cs1 {
+				rockchip,pins = <0x04 0x09 0x08 0x194>;
+				phandle = <0x3b7>;
+			};
+
+			spi0m2-pins {
+				rockchip,pins = <0x01 0x0b 0x08 0x194 0x01 0x09 0x08 0x194 0x01 0x0a 0x08 0x194>;
+				phandle = <0x3b8>;
+			};
+
+			spi0m2-cs0 {
+				rockchip,pins = <0x01 0x0c 0x08 0x194>;
+				phandle = <0x3b9>;
+			};
+
+			spi0m2-cs1 {
+				rockchip,pins = <0x01 0x0d 0x08 0x194>;
+				phandle = <0x3ba>;
+			};
+
+			spi0m3-pins {
+				rockchip,pins = <0x03 0x1b 0x08 0x194 0x03 0x19 0x08 0x194 0x03 0x1a 0x08 0x194>;
+				phandle = <0x3bb>;
+			};
+
+			spi0m3-cs0 {
+				rockchip,pins = <0x03 0x1c 0x08 0x194>;
+				phandle = <0x3bc>;
+			};
+
+			spi0m3-cs1 {
+				rockchip,pins = <0x03 0x1d 0x08 0x194>;
+				phandle = <0x3bd>;
+			};
+		};
+
+		spi1 {
+
+			spi1m1-pins {
+				rockchip,pins = <0x03 0x11 0x08 0x194 0x03 0x10 0x08 0x194 0x03 0x0f 0x08 0x194>;
+				phandle = <0x144>;
+			};
+
+			spi1m1-cs0 {
+				rockchip,pins = <0x03 0x12 0x08 0x194>;
+				phandle = <0x142>;
+			};
+
+			spi1m1-cs1 {
+				rockchip,pins = <0x03 0x13 0x08 0x194>;
+				phandle = <0x143>;
+			};
+
+			spi1m2-pins {
+				rockchip,pins = <0x01 0x1a 0x08 0x194 0x01 0x18 0x08 0x194 0x01 0x19 0x08 0x194>;
+				phandle = <0x3be>;
+			};
+
+			spi1m2-cs0 {
+				rockchip,pins = <0x01 0x1b 0x08 0x194>;
+				phandle = <0x3bf>;
+			};
+
+			spi1m2-cs1 {
+				rockchip,pins = <0x01 0x1d 0x08 0x194>;
+				phandle = <0x3c0>;
+			};
+		};
+
+		spi2 {
+
+			spi2m0-pins {
+				rockchip,pins = <0x01 0x06 0x08 0x194 0x01 0x04 0x08 0x194 0x01 0x05 0x08 0x194>;
+				phandle = <0x3c1>;
+			};
+
+			spi2m0-cs0 {
+				rockchip,pins = <0x01 0x07 0x08 0x194>;
+				phandle = <0x3c2>;
+			};
+
+			spi2m0-cs1 {
+				rockchip,pins = <0x01 0x08 0x08 0x194>;
+				phandle = <0x3c3>;
+			};
+
+			spi2m1-pins {
+				rockchip,pins = <0x04 0x06 0x08 0x194 0x04 0x04 0x08 0x194 0x04 0x05 0x08 0x194>;
+				phandle = <0x3c4>;
+			};
+
+			spi2m1-cs0 {
+				rockchip,pins = <0x04 0x07 0x08 0x194>;
+				phandle = <0x3c5>;
+			};
+
+			spi2m1-cs1 {
+				rockchip,pins = <0x04 0x08 0x08 0x194>;
+				phandle = <0x3c6>;
+			};
+
+			spi2m2-pins {
+				rockchip,pins = <0x00 0x05 0x01 0x195 0x00 0x0b 0x01 0x195 0x00 0x06 0x01 0x195>;
+				phandle = <0x146>;
+			};
+
+			spi2m2-cs0 {
+				rockchip,pins = <0x00 0x09 0x01 0x195>;
+				phandle = <0x145>;
+			};
+
+			spi2m2-cs1 {
+				rockchip,pins = <0x00 0x08 0x01 0x195>;
+				phandle = <0x3c7>;
+			};
+		};
+
+		spi3 {
+
+			spi3m1-pins {
+				rockchip,pins = <0x04 0x0f 0x08 0x194 0x04 0x0d 0x08 0x194 0x04 0x0e 0x08 0x194>;
+				phandle = <0x151>;
+			};
+
+			spi3m1-cs0 {
+				rockchip,pins = <0x04 0x10 0x08 0x194>;
+				phandle = <0x14f>;
+			};
+
+			spi3m1-cs1 {
+				rockchip,pins = <0x04 0x11 0x08 0x194>;
+				phandle = <0x150>;
+			};
+
+			spi3m2-pins {
+				rockchip,pins = <0x00 0x1b 0x08 0x194 0x00 0x18 0x08 0x194 0x00 0x1a 0x08 0x194>;
+				phandle = <0x3c8>;
+			};
+
+			spi3m2-cs0 {
+				rockchip,pins = <0x00 0x1c 0x08 0x194>;
+				phandle = <0x3c9>;
+			};
+
+			spi3m2-cs1 {
+				rockchip,pins = <0x00 0x1d 0x08 0x194>;
+				phandle = <0x3ca>;
+			};
+
+			spi3m3-pins {
+				rockchip,pins = <0x03 0x18 0x08 0x194 0x03 0x16 0x08 0x194 0x03 0x17 0x08 0x194>;
+				phandle = <0x3cb>;
+			};
+
+			spi3m3-cs0 {
+				rockchip,pins = <0x03 0x14 0x08 0x194>;
+				phandle = <0x3cc>;
+			};
+
+			spi3m3-cs1 {
+				rockchip,pins = <0x03 0x15 0x08 0x194>;
+				phandle = <0x3cd>;
+			};
+		};
+
+		spi4 {
+
+			spi4m0-pins {
+				rockchip,pins = <0x01 0x12 0x08 0x194 0x01 0x10 0x08 0x194 0x01 0x11 0x08 0x194>;
+				phandle = <0x17f>;
+			};
+
+			spi4m0-cs0 {
+				rockchip,pins = <0x01 0x13 0x08 0x194>;
+				phandle = <0x3ce>;
+			};
+
+			spi4m0-cs1 {
+				rockchip,pins = <0x01 0x14 0x08 0x194>;
+				phandle = <0x17e>;
+			};
+
+			spi4m1-pins {
+				rockchip,pins = <0x03 0x02 0x08 0x194 0x03 0x00 0x08 0x194 0x03 0x01 0x08 0x194>;
+				phandle = <0x3cf>;
+			};
+
+			spi4m1-cs0 {
+				rockchip,pins = <0x03 0x03 0x08 0x194>;
+				phandle = <0x3d0>;
+			};
+
+			spi4m1-cs1 {
+				rockchip,pins = <0x03 0x04 0x08 0x194>;
+				phandle = <0x3d1>;
+			};
+
+			spi4m2-pins {
+				rockchip,pins = <0x01 0x02 0x08 0x194 0x01 0x00 0x08 0x194 0x01 0x01 0x08 0x194>;
+				phandle = <0x3d2>;
+			};
+
+			spi4m2-cs0 {
+				rockchip,pins = <0x01 0x03 0x08 0x194>;
+				phandle = <0x3d3>;
+			};
+		};
+
+		tsadc {
+
+			tsadcm1-shut {
+				rockchip,pins = <0x00 0x02 0x02 0x18d>;
+				phandle = <0x3d4>;
+			};
+
+			tsadc-shut {
+				rockchip,pins = <0x00 0x01 0x02 0x18d>;
+				phandle = <0x169>;
+			};
+
+			tsadc-shut-org {
+				rockchip,pins = <0x00 0x01 0x01 0x18d>;
+				phandle = <0x3d5>;
+			};
+		};
+
+		uart0 {
+
+			uart0m0-xfer {
+				rockchip,pins = <0x00 0x14 0x04 0x192 0x00 0x15 0x04 0x192>;
+				phandle = <0x3d6>;
+			};
+
+			uart0m1-xfer {
+				rockchip,pins = <0x00 0x08 0x04 0x192 0x00 0x09 0x04 0x192>;
+				phandle = <0x3d7>;
+			};
+
+			uart0m2-xfer {
+				rockchip,pins = <0x04 0x04 0x0a 0x192 0x04 0x03 0x0a 0x192>;
+				phandle = <0x72>;
+			};
+
+			uart0-ctsn {
+				rockchip,pins = <0x00 0x19 0x04 0x18d>;
+				phandle = <0x3d8>;
+			};
+
+			uart0-rtsn {
+				rockchip,pins = <0x00 0x16 0x04 0x18d>;
+				phandle = <0x3d9>;
+			};
+		};
+
+		uart1 {
+
+			uart1m1-xfer {
+				rockchip,pins = <0x01 0x0f 0x0a 0x192 0x01 0x0e 0x0a 0x192>;
+				phandle = <0x152>;
+			};
+
+			uart1m1-ctsn {
+				rockchip,pins = <0x01 0x1f 0x0a 0x18d>;
+				phandle = <0x3da>;
+			};
+
+			uart1m1-rtsn {
+				rockchip,pins = <0x01 0x1e 0x0a 0x18d>;
+				phandle = <0x3db>;
+			};
+
+			uart1m2-xfer {
+				rockchip,pins = <0x00 0x1a 0x0a 0x192 0x00 0x19 0x0a 0x192>;
+				phandle = <0x3dc>;
+			};
+
+			uart1m2-ctsn {
+				rockchip,pins = <0x00 0x18 0x0a 0x18d>;
+				phandle = <0x3dd>;
+			};
+
+			uart1m2-rtsn {
+				rockchip,pins = <0x00 0x17 0x0a 0x18d>;
+				phandle = <0x3de>;
+			};
+		};
+
+		uart2 {
+
+			uart2m0-xfer {
+				rockchip,pins = <0x00 0x0e 0x0a 0x192 0x00 0x0d 0x0a 0x192>;
+				phandle = <0x1af>;
+			};
+
+			uart2m1-xfer {
+				rockchip,pins = <0x04 0x19 0x0a 0x192 0x04 0x18 0x0a 0x192>;
+				phandle = <0x153>;
+			};
+
+			uart2m2-xfer {
+				rockchip,pins = <0x03 0x0a 0x0a 0x192 0x03 0x09 0x0a 0x192>;
+				phandle = <0x3df>;
+			};
+
+			uart2-ctsn {
+				rockchip,pins = <0x03 0x0c 0x0a 0x18d>;
+				phandle = <0x3e0>;
+			};
+
+			uart2-rtsn {
+				rockchip,pins = <0x03 0x0b 0x0a 0x18d>;
+				phandle = <0x3e1>;
+			};
+		};
+
+		uart3 {
+
+			uart3m0-xfer {
+				rockchip,pins = <0x01 0x10 0x0a 0x192 0x01 0x11 0x0a 0x192>;
+				phandle = <0x154>;
+			};
+
+			uart3m1-xfer {
+				rockchip,pins = <0x03 0x0e 0x0a 0x192 0x03 0x0d 0x0a 0x192>;
+				phandle = <0x3e2>;
+			};
+
+			uart3m2-xfer {
+				rockchip,pins = <0x04 0x06 0x0a 0x192 0x04 0x05 0x0a 0x192>;
+				phandle = <0x3e3>;
+			};
+
+			uart3-ctsn {
+				rockchip,pins = <0x01 0x13 0x0a 0x18d>;
+				phandle = <0x3e4>;
+			};
+
+			uart3-rtsn {
+				rockchip,pins = <0x01 0x12 0x0a 0x18d>;
+				phandle = <0x3e5>;
+			};
+		};
+
+		uart4 {
+
+			uart4m0-xfer {
+				rockchip,pins = <0x01 0x1b 0x0a 0x192 0x01 0x1a 0x0a 0x192>;
+				phandle = <0x155>;
+			};
+
+			uart4m1-xfer {
+				rockchip,pins = <0x03 0x18 0x0a 0x192 0x03 0x19 0x0a 0x192>;
+				phandle = <0x3e6>;
+			};
+
+			uart4m2-xfer {
+				rockchip,pins = <0x01 0x0a 0x0a 0x192 0x01 0x0b 0x0a 0x192>;
+				phandle = <0x3e7>;
+			};
+
+			uart4-ctsn {
+				rockchip,pins = <0x01 0x17 0x0a 0x18d>;
+				phandle = <0x3e8>;
+			};
+
+			uart4-rtsn {
+				rockchip,pins = <0x01 0x15 0x0a 0x18d>;
+				phandle = <0x3e9>;
+			};
+		};
+
+		uart5 {
+
+			uart5m0-xfer {
+				rockchip,pins = <0x04 0x1c 0x0a 0x192 0x04 0x1d 0x0a 0x192>;
+				phandle = <0x3ea>;
+			};
+
+			uart5m0-ctsn {
+				rockchip,pins = <0x04 0x1a 0x0a 0x18d>;
+				phandle = <0x3eb>;
+			};
+
+			uart5m0-rtsn {
+				rockchip,pins = <0x04 0x1b 0x0a 0x18d>;
+				phandle = <0x3ec>;
+			};
+
+			uart5m1-xfer {
+				rockchip,pins = <0x03 0x15 0x0a 0x192 0x03 0x14 0x0a 0x192>;
+				phandle = <0x156>;
+			};
+
+			uart5m1-ctsn {
+				rockchip,pins = <0x02 0x02 0x0a 0x18d>;
+				phandle = <0x3ed>;
+			};
+
+			uart5m1-rtsn {
+				rockchip,pins = <0x02 0x03 0x0a 0x18d>;
+				phandle = <0x3ee>;
+			};
+
+			uart5m2-xfer {
+				rockchip,pins = <0x02 0x1c 0x0a 0x192 0x02 0x1d 0x0a 0x192>;
+				phandle = <0x3ef>;
+			};
+		};
+
+		uart6 {
+
+			uart6m1-xfer {
+				rockchip,pins = <0x01 0x00 0x0a 0x192 0x01 0x01 0x0a 0x192>;
+				phandle = <0x157>;
+			};
+
+			uart6m1-ctsn {
+				rockchip,pins = <0x01 0x03 0x0a 0x18d>;
+				phandle = <0x3f0>;
+			};
+
+			uart6m1-rtsn {
+				rockchip,pins = <0x01 0x02 0x0a 0x18d>;
+				phandle = <0x3f1>;
+			};
+
+			uart6m2-xfer {
+				rockchip,pins = <0x01 0x19 0x0a 0x192 0x01 0x18 0x0a 0x192>;
+				phandle = <0x3f2>;
+			};
+		};
+
+		uart7 {
+
+			uart7m1-xfer {
+				rockchip,pins = <0x03 0x11 0x0a 0x192 0x03 0x10 0x0a 0x192>;
+				phandle = <0x158>;
+			};
+
+			uart7m1-ctsn {
+				rockchip,pins = <0x03 0x13 0x0a 0x18d>;
+				phandle = <0x3f3>;
+			};
+
+			uart7m1-rtsn {
+				rockchip,pins = <0x03 0x12 0x0a 0x18d>;
+				phandle = <0x3f4>;
+			};
+
+			uart7m2-xfer {
+				rockchip,pins = <0x01 0x0c 0x0a 0x192 0x01 0x0d 0x0a 0x192>;
+				phandle = <0x3f5>;
+			};
+		};
+
+		uart8 {
+
+			uart8m0-xfer {
+				rockchip,pins = <0x04 0x09 0x0a 0x192 0x04 0x08 0x0a 0x192>;
+				phandle = <0x3f6>;
+			};
+
+			uart8m0-ctsn {
+				rockchip,pins = <0x04 0x0b 0x0a 0x18d>;
+				phandle = <0x3f7>;
+			};
+
+			uart8m0-rtsn {
+				rockchip,pins = <0x04 0x0a 0x0a 0x18d>;
+				phandle = <0x3f8>;
+			};
+
+			uart8m1-xfer {
+				rockchip,pins = <0x03 0x03 0x0a 0x192 0x03 0x02 0x0a 0x192>;
+				phandle = <0x159>;
+			};
+
+			uart8m1-ctsn {
+				rockchip,pins = <0x03 0x05 0x0a 0x18d>;
+				phandle = <0x3f9>;
+			};
+
+			uart8m1-rtsn {
+				rockchip,pins = <0x03 0x04 0x0a 0x18d>;
+				phandle = <0x3fa>;
+			};
+
+			uart8-xfer {
+				rockchip,pins = <0x04 0x09 0x0a 0x192>;
+				phandle = <0x3fb>;
+			};
+		};
+
+		uart9 {
+
+			uart9m1-xfer {
+				rockchip,pins = <0x04 0x0d 0x0a 0x192 0x04 0x0c 0x0a 0x192>;
+				phandle = <0x3fc>;
+			};
+
+			uart9m1-ctsn {
+				rockchip,pins = <0x04 0x01 0x0a 0x18d>;
+				phandle = <0x3fd>;
+			};
+
+			uart9m1-rtsn {
+				rockchip,pins = <0x04 0x00 0x0a 0x18d>;
+				phandle = <0x3fe>;
+			};
+
+			uart9m2-xfer {
+				rockchip,pins = <0x03 0x1c 0x0a 0x192 0x03 0x1d 0x0a 0x192>;
+				phandle = <0x15a>;
+			};
+
+			uart9m2-ctsn {
+				rockchip,pins = <0x03 0x1b 0x0a 0x18d>;
+				phandle = <0x15b>;
+			};
+
+			uart9m2-rtsn {
+				rockchip,pins = <0x03 0x1a 0x0a 0x18d>;
+				phandle = <0x1a8>;
+			};
+		};
+
+		vop {
+
+			vop-pins {
+				rockchip,pins = <0x01 0x02 0x01 0x18d>;
+				phandle = <0x3ff>;
+			};
+		};
+
+		bt656 {
+
+			bt656-pins {
+				rockchip,pins = <0x04 0x08 0x02 0x196 0x04 0x00 0x02 0x196 0x04 0x01 0x02 0x196 0x04 0x02 0x02 0x196 0x04 0x03 0x02 0x196 0x04 0x04 0x02 0x196 0x04 0x05 0x02 0x196 0x04 0x06 0x02 0x196 0x04 0x07 0x02 0x196>;
+				phandle = <0x400>;
+			};
+		};
+
+		gpio-func {
+
+			tsadc-gpio-func {
+				rockchip,pins = <0x00 0x01 0x00 0x18d>;
+				phandle = <0x168>;
+			};
+
+			leds-gpio {
+				rockchip,pins = <0x01 0x02 0x00 0x18d>;
+				phandle = <0x1b1>;
+			};
+		};
+
+		headphone {
+
+			hp-det {
+				rockchip,pins = <0x01 0x1d 0x00 0x18d>;
+				phandle = <0x1a6>;
+			};
+		};
+
+		hym8563 {
+
+			hym8563-int {
+				rockchip,pins = <0x00 0x08 0x00 0x192>;
+				phandle = <0x172>;
+			};
+		};
+
+		lcd {
+
+			lcd0-rst-gpio {
+				rockchip,pins = <0x01 0x09 0x00 0x18d>;
+				phandle = <0xe3>;
+			};
+
+			lcd1-rst-gpio {
+				rockchip,pins = <0x01 0x0b 0x00 0x18d>;
+				phandle = <0xe8>;
+			};
+		};
+
+		usb-typec {
+
+			usbc0-int {
+				rockchip,pins = <0x00 0x1b 0x00 0x192>;
+				phandle = <0x16d>;
+			};
+
+			typec5v-pwren {
+				rockchip,pins = <0x03 0x10 0x00 0x18d>;
+				phandle = <0x1ae>;
+			};
+		};
+
+		wireless-bluetooth {
+
+			uart9-gpios {
+				rockchip,pins = <0x03 0x1a 0x00 0x18d>;
+				phandle = <0x1aa>;
+			};
+
+			bt-gpio {
+				rockchip,pins = <0x03 0x06 0x00 0x18d 0x00 0x16 0x00 0x192>;
+				phandle = <0x1a9>;
+			};
+		};
+
+		wireless-wlan {
+
+			wifi-host-wake-irq {
+				rockchip,pins = <0x00 0x00 0x00 0x193>;
+				phandle = <0x1ab>;
+			};
+
+			wifi-poweren-gpio {
+				rockchip,pins = <0x00 0x18 0x00 0x192>;
+				phandle = <0x1ac>;
+			};
+		};
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <0x197 0x01>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <0x1b7740>;
+		poll-interval = <0x64>;
+		phandle = <0x401>;
+
+		vol-up-key {
+			label = "volume up";
+			linux,code = <0x73>;
+			press-threshold-microvolt = <0x4268>;
+		};
+
+		vol-down-key {
+			label = "volume down";
+			linux,code = <0x72>;
+			press-threshold-microvolt = <0x65ce8>;
+		};
+
+		menu-key {
+			label = "menu";
+			linux,code = <0x8b>;
+			press-threshold-microvolt = <0xd9490>;
+		};
+
+		back-key {
+			label = "back";
+			linux,code = <0x9e>;
+			press-threshold-microvolt = <0x12d838>;
+		};
+	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		brightness-levels = <0x00 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>;
+		default-brightness-level = <0xc8>;
+		pwms = <0x198 0x00 0x61a8 0x00>;
+		status = "okay";
+		phandle = <0xe1>;
+	};
+
+	backlight_1 {
+		compatible = "pwm-backlight";
+		brightness-levels = <0x00 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>;
+		default-brightness-level = <0xc8>;
+		pwms = <0x199 0x00 0x61a8 0x00>;
+		status = "okay";
+		phandle = <0xe7>;
+	};
+
+	dp0-sound {
+		status = "okay";
+		compatible = "rockchip,hdmi";
+		rockchip,card-name = "rockchip-dp0";
+		rockchip,mclk-fs = <0x200>;
+		rockchip,cpu = <0x19a>;
+		rockchip,codec = <0x19b 0x01>;
+		rockchip,jack-det;
+		phandle = <0x402>;
+	};
+
+	hdmi0-sound {
+		status = "okay";
+		compatible = "rockchip,hdmi";
+		rockchip,mclk-fs = <0x80>;
+		rockchip,card-name = "rockchip-hdmi0";
+		rockchip,cpu = <0x19c>;
+		rockchip,codec = <0x19d>;
+		rockchip,jack-det;
+		phandle = <0x403>;
+	};
+
+	spdif-tx1-dc {
+		status = "disabled";
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0x00>;
+		phandle = <0x19f>;
+	};
+
+	spdif-tx1-sound {
+		status = "disabled";
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "rockchip,spdif-tx1";
+		phandle = <0x404>;
+
+		simple-audio-card,cpu {
+			sound-dai = <0x19e>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <0x19f>;
+		};
+	};
+
+	test-power {
+		status = "okay";
+	};
+
+	vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0xb71b00>;
+		regulator-max-microvolt = <0xb71b00>;
+		phandle = <0x1a0>;
+	};
+
+	vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x4c4b40>;
+		regulator-max-microvolt = <0x4c4b40>;
+		vin-supply = <0x1a0>;
+		phandle = <0x70>;
+	};
+
+	vcc5v0-usbdcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usbdcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x4c4b40>;
+		regulator-max-microvolt = <0x4c4b40>;
+		vin-supply = <0x1a0>;
+		phandle = <0x1a1>;
+	};
+
+	vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x4c4b40>;
+		regulator-max-microvolt = <0x4c4b40>;
+		vin-supply = <0x1a1>;
+		phandle = <0x1ad>;
+	};
+
+	combophy-avdd0v85 {
+		compatible = "regulator-fixed";
+		regulator-name = "combophy_avdd0v85";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <0xcf850>;
+		regulator-max-microvolt = <0xcf850>;
+		vin-supply = <0x1a2>;
+		phandle = <0x405>;
+	};
+
+	combophy-avdd1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "combophy_avdd1v8";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <0x1b7740>;
+		regulator-max-microvolt = <0x1b7740>;
+		vin-supply = <0x1a3>;
+		phandle = <0x406>;
+	};
+
+	es8388-sound {
+		status = "okay";
+		compatible = "rockchip,multicodecs-card";
+		rockchip,card-name = "rockchip-es8388";
+		hp-det-gpio = <0xe2 0x1d 0x00>;
+		io-channels = <0x197 0x03>;
+		io-channel-names = "adc-detect";
+		keyup-threshold-microvolt = <0x1b7740>;
+		poll-interval = <0x64>;
+		rockchip,format = "i2s";
+		rockchip,mclk-fs = <0x100>;
+		rockchip,cpu = <0x1a4>;
+		rockchip,codec = <0x1a5>;
+		rockchip,audio-routing = "Headphone\0LOUT1\0Headphone\0ROUT1\0Headphone\0Headphone Power\0Headphone\0Headphone Power\0LINPUT1\0Main Mic\0LINPUT2\0Main Mic\0RINPUT1\0Headset Mic\0RINPUT2\0Headset Mic";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x1a6>;
+		phandle = <0x407>;
+
+		play-pause-key {
+			label = "playpause";
+			linux,code = <0xa4>;
+			press-threshold-microvolt = <0x7d0>;
+		};
+	};
+
+	wireless-bluetooth {
+		compatible = "bluetooth-platdata";
+		clocks = <0x1a7>;
+		clock-names = "ext_clock";
+		uart_rts_gpios = <0xfe 0x1a 0x01>;
+		pinctrl-names = "default\0rts_gpio";
+		pinctrl-0 = <0x1a8 0x1a9>;
+		pinctrl-1 = <0x1aa>;
+		BT,reset_gpio = <0xfe 0x06 0x00>;
+		BT,wake_gpio = <0x147 0x16 0x00>;
+		status = "okay";
+		phandle = <0x408>;
+	};
+
+	wireless-wlan {
+		compatible = "wlan-platdata";
+		wifi_chip_type = "ap6275p";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x1ab 0x1ac>;
+		WIFI,host_wake_irq = <0x147 0x00 0x00>;
+		WIFI,poweren_gpio = <0x147 0x18 0x00>;
+		status = "okay";
+		phandle = <0x409>;
+	};
+
+	vbus5v0-typec {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus5v0_typec";
+		regulator-min-microvolt = <0x4c4b40>;
+		regulator-max-microvolt = <0x4c4b40>;
+		enable-active-high;
+		gpio = <0xfe 0x10 0x00>;
+		vin-supply = <0x1ad>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x1ae>;
+		phandle = <0x16e>;
+	};
+
+	cspmu@fd10c000 {
+		compatible = "rockchip,cspmu";
+		reg = <0x00 0xfd10c000 0x00 0x1000 0x00 0xfd10d000 0x00 0x1000 0x00 0xfd10e000 0x00 0x1000 0x00 0xfd10f000 0x00 0x1000 0x00 0xfd12c000 0x00 0x1000 0x00 0xfd12d000 0x00 0x1000 0x00 0xfd12e000 0x00 0x1000 0x00 0xfd12f000 0x00 0x1000>;
+		phandle = <0x40a>;
+	};
+
+	debug@fd104000 {
+		compatible = "rockchip,debug";
+		reg = <0x00 0xfd104000 0x00 0x1000 0x00 0xfd105000 0x00 0x1000 0x00 0xfd106000 0x00 0x1000 0x00 0xfd107000 0x00 0x1000 0x00 0xfd124000 0x00 0x1000 0x00 0xfd125000 0x00 0x1000 0x00 0xfd126000 0x00 0x1000 0x00 0xfd127000 0x00 0x1000>;
+		phandle = <0x40b>;
+	};
+
+	fiq-debugger {
+		compatible = "rockchip,fiq-debugger";
+		rockchip,serial-id = <0x02>;
+		rockchip,wake-irq = <0x00>;
+		rockchip,irq-mode-enable = <0x01>;
+		rockchip,baudrate = <0x16e360>;
+		interrupts = <0x00 0x1a7 0x08>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x1af>;
+		status = "okay";
+		phandle = <0x40c>;
+	};
+
+	reserved-memory {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+
+		cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x00 0x800000>;
+			linux,cma-default;
+		};
+
+		drm-logo@00000000 {
+			compatible = "rockchip,drm-logo";
+			reg = <0x00 0x00 0x00 0x00>;
+			phandle = <0x37>;
+		};
+
+		drm-cubic-lut@00000000 {
+			compatible = "rockchip,drm-cubic-lut";
+			reg = <0x00 0x00 0x00 0x00>;
+			phandle = <0x40d>;
+		};
+
+		ramoops@110000 {
+			compatible = "ramoops";
+			reg = <0x00 0x110000 0x00 0xf0000>;
+			record-size = <0x20000>;
+			console-size = <0x80000>;
+			ftrace-size = <0x00>;
+			pmsg-size = <0x50000>;
+			phandle = <0x40e>;
+		};
+	};
+
+	vcc-3v3-sd-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_sd_s0";
+		regulator-min-microvolt = <0x325aa0>;
+		regulator-max-microvolt = <0x325aa0>;
+		gpios = <0xf3 0x0d 0x01>;
+		enable-active-low;
+		vin-supply = <0x1b0>;
+		phandle = <0x10f>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vcc-1v1-nldo-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x10c8e0>;
+		regulator-max-microvolt = <0x10c8e0>;
+		vin-supply = <0x70>;
+		phandle = <0x14e>;
+	};
+
+	vcc3v3-pcie2x1l2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie2x1l2";
+		regulator-min-microvolt = <0x1b7740>;
+		regulator-max-microvolt = <0x1b7740>;
+		enable-active-high;
+		regulator-boot-on;
+		regulator-always-on;
+		gpios = <0x147 0x15 0x00>;
+		startup-delay-us = <0xc350>;
+		vin-supply = <0x70>;
+		phandle = <0xff>;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x1b1>;
+		status = "okay";
+		phandle = <0x40f>;
+
+		led@1 {
+			gpios = <0xe2 0x02 0x00>;
+			label = "status_led";
+			linux,default-trigger = "heartbeat";
+			linux,default-trigger-delay-ms = <0x00>;
+		};
+	};
+
+	__symbols__ {
+		spll = "/clocks/spll";
+		xin32k = "/clocks/xin32k";
+		xin24m = "/clocks/xin24m";
+		hclk_vo1 = "/clocks/hclk_vo1@fd7c08ec";
+		aclk_vdpu_low_pre = "/clocks/aclk_vdpu_low_pre@fd7c08b0";
+		hclk_vo0 = "/clocks/hclk_vo0@fd7c08dc";
+		hclk_usb = "/clocks/hclk_usb@fd7c08a8";
+		hclk_nvm = "/clocks/hclk_nvm@fd7c087c";
+		aclk_usb = "/clocks/aclk_usb@fd7c08a8";
+		hclk_isp1_pre = "/clocks/hclk_isp1_pre@fd7c0868";
+		aclk_isp1_pre = "/clocks/aclk_isp1_pre@fd7c0868";
+		aclk_rkvdec0_pre = "/clocks/aclk_rkvdec0_pre@fd7c08a0";
+		hclk_rkvdec0_pre = "/clocks/hclk_rkvdec0_pre@fd7c08a0";
+		aclk_rkvdec1_pre = "/clocks/aclk_rkvdec1_pre@fd7c08a4";
+		hclk_rkvdec1_pre = "/clocks/hclk_rkvdec1_pre@fd7c08a4";
+		aclk_jpeg_decoder_pre = "/clocks/aclk_jpeg_decoder_pre@fd7c08b0";
+		aclk_rkvenc1_pre = "/clocks/aclk_rkvenc1_pre@fd7c08c0";
+		hclk_rkvenc1_pre = "/clocks/hclk_rkvenc1_pre@fd7c08c0";
+		aclk_hdcp0_pre = "/clocks/aclk_hdcp0_pre@fd7c08dc";
+		aclk_hdcp1_pre = "/clocks/aclk_hdcp1_pre@fd7c08ec";
+		pclk_av1_pre = "/clocks/pclk_av1_pre@fd7c0910";
+		aclk_av1_pre = "/clocks/aclk_av1_pre@fd7c0910";
+		hclk_sdio_pre = "/clocks/hclk_sdio_pre@fd7c092c";
+		pclk_vo0_grf = "/clocks/pclk_vo0_grf@fd7c08dc";
+		pclk_vo1_grf = "/clocks/pclk_vo1_grf@fd7c08ec";
+		cpu_l0 = "/cpus/cpu@0";
+		cpu_l1 = "/cpus/cpu@100";
+		cpu_l2 = "/cpus/cpu@200";
+		cpu_l3 = "/cpus/cpu@300";
+		cpu_b0 = "/cpus/cpu@400";
+		cpu_b1 = "/cpus/cpu@500";
+		cpu_b2 = "/cpus/cpu@600";
+		cpu_b3 = "/cpus/cpu@700";
+		CPU_SLEEP = "/cpus/idle-states/cpu-sleep";
+		l2_cache_l0 = "/cpus/l2-cache-l0";
+		l2_cache_l1 = "/cpus/l2-cache-l1";
+		l2_cache_l2 = "/cpus/l2-cache-l2";
+		l2_cache_l3 = "/cpus/l2-cache-l3";
+		l2_cache_b0 = "/cpus/l2-cache-b0";
+		l2_cache_b1 = "/cpus/l2-cache-b1";
+		l2_cache_b2 = "/cpus/l2-cache-b2";
+		l2_cache_b3 = "/cpus/l2-cache-b3";
+		l3_cache = "/cpus/l3-cache";
+		cluster0_opp_table = "/cluster0-opp-table";
+		cluster1_opp_table = "/cluster1-opp-table";
+		cluster2_opp_table = "/cluster2-opp-table";
+		arm_pmu = "/arm-pmu";
+		csi2_dcphy0 = "/csi2-dcphy0";
+		mipi_in_cam0 = "/csi2-dcphy0/ports/port@0/endpoint@0";
+		mipi_in_cam1 = "/csi2-dcphy0/ports/port@0/endpoint@1";
+		csidcphy0_out = "/csi2-dcphy0/ports/port@1/endpoint@0";
+		csi2_dcphy1 = "/csi2-dcphy1";
+		mipi_in_dcphy0 = "/csi2-dcphy1/ports/port@0/endpoint@0";
+		mipi_in_dcphy1 = "/csi2-dcphy1/ports/port@0/endpoint@1";
+		csidcphy1_out = "/csi2-dcphy1/ports/port@1/endpoint@0";
+		csi2_dphy0 = "/csi2-dphy0";
+		mipi_in_ucam0 = "/csi2-dphy0/ports/port@0/endpoint@0";
+		mipi_in_ucam1 = "/csi2-dphy0/ports/port@0/endpoint@1";
+		csidphy0_out = "/csi2-dphy0/ports/port@1/endpoint@0";
+		csi2_dphy1 = "/csi2-dphy1";
+		csi2_dphy2 = "/csi2-dphy2";
+		display_subsystem = "/display-subsystem";
+		route_dp0 = "/display-subsystem/route/route-dp0";
+		route_dsi0 = "/display-subsystem/route/route-dsi0";
+		route_dsi1 = "/display-subsystem/route/route-dsi1";
+		route_edp0 = "/display-subsystem/route/route-edp0";
+		route_edp1 = "/display-subsystem/route/route-edp1";
+		route_hdmi0 = "/display-subsystem/route/route-hdmi0";
+		route_rgb = "/display-subsystem/route/route-rgb";
+		dmc = "/dmc";
+		dmc_opp_table = "/dmc-opp-table";
+		scmi = "/firmware/scmi";
+		scmi_clk = "/firmware/scmi/protocol@14";
+		scmi_reset = "/firmware/scmi/protocol@16";
+		sdei = "/firmware/sdei";
+		optee = "/firmware/optee";
+		jpege_ccu = "/jpege-ccu";
+		mpp_srv = "/mpp-srv";
+		rkcif_dvp = "/rkcif-dvp";
+		rkcif_dvp_sditf = "/rkcif-dvp-sditf";
+		rkcif_mipi_lvds = "/rkcif-mipi-lvds";
+		cif_mipi_in0 = "/rkcif-mipi-lvds/port/endpoint";
+		rkcif_mipi_lvds_sditf = "/rkcif-mipi-lvds-sditf";
+		mipi_lvds_sditf = "/rkcif-mipi-lvds-sditf/port/endpoint";
+		rkcif_mipi_lvds_sditf_vir1 = "/rkcif-mipi-lvds-sditf-vir1";
+		rkcif_mipi_lvds_sditf_vir2 = "/rkcif-mipi-lvds-sditf-vir2";
+		rkcif_mipi_lvds_sditf_vir3 = "/rkcif-mipi-lvds-sditf-vir3";
+		rkcif_mipi_lvds1 = "/rkcif-mipi-lvds1";
+		cif_mipi_in1 = "/rkcif-mipi-lvds1/port/endpoint";
+		rkcif_mipi_lvds1_sditf = "/rkcif-mipi-lvds1-sditf";
+		mipi1_lvds_sditf = "/rkcif-mipi-lvds1-sditf/port/endpoint";
+		rkcif_mipi_lvds1_sditf_vir1 = "/rkcif-mipi-lvds1-sditf-vir1";
+		rkcif_mipi_lvds1_sditf_vir2 = "/rkcif-mipi-lvds1-sditf-vir2";
+		rkcif_mipi_lvds1_sditf_vir3 = "/rkcif-mipi-lvds1-sditf-vir3";
+		rkcif_mipi_lvds2 = "/rkcif-mipi-lvds2";
+		cif_mipi_in2 = "/rkcif-mipi-lvds2/port/endpoint";
+		rkcif_mipi_lvds2_sditf = "/rkcif-mipi-lvds2-sditf";
+		mipi2_lvds_sditf = "/rkcif-mipi-lvds2-sditf/port/endpoint";
+		rkcif_mipi_lvds2_sditf_vir1 = "/rkcif-mipi-lvds2-sditf-vir1";
+		rkcif_mipi_lvds2_sditf_vir2 = "/rkcif-mipi-lvds2-sditf-vir2";
+		rkcif_mipi_lvds2_sditf_vir3 = "/rkcif-mipi-lvds2-sditf-vir3";
+		rkcif_mipi_lvds3 = "/rkcif-mipi-lvds3";
+		rkcif_mipi_lvds3_sditf = "/rkcif-mipi-lvds3-sditf";
+		rkcif_mipi_lvds3_sditf_vir1 = "/rkcif-mipi-lvds3-sditf-vir1";
+		rkcif_mipi_lvds3_sditf_vir2 = "/rkcif-mipi-lvds3-sditf-vir2";
+		rkcif_mipi_lvds3_sditf_vir3 = "/rkcif-mipi-lvds3-sditf-vir3";
+		rkisp0_vir0 = "/rkisp0-vir0";
+		isp1_in1 = "/rkisp0-vir0/port/endpoint@0";
+		rkisp0_vir1 = "/rkisp0-vir1";
+		isp0_vir1 = "/rkisp0-vir1/port/endpoint@0";
+		rkisp0_vir2 = "/rkisp0-vir2";
+		rkisp0_vir3 = "/rkisp0-vir3";
+		rkisp1_vir0 = "/rkisp1-vir0";
+		isp1_in0 = "/rkisp1-vir0/port/endpoint@0";
+		rkisp1_vir1 = "/rkisp1-vir1";
+		rkisp1_vir2 = "/rkisp1-vir2";
+		rkisp1_vir3 = "/rkisp1-vir3";
+		rkispp0_vir0 = "/rkispp0-vir0";
+		rkispp1_vir0 = "/rkispp1-vir0";
+		rkvenc_ccu = "/rkvenc-ccu";
+		rockchip_suspend = "/rockchip-suspend";
+		rockchip_system_monitor = "/rockchip-system-monitor";
+		thermal_zones = "/thermal-zones";
+		soc_thermal = "/thermal-zones/soc-thermal";
+		threshold = "/thermal-zones/soc-thermal/trips/trip-point-0";
+		target = "/thermal-zones/soc-thermal/trips/trip-point-1";
+		soc_crit = "/thermal-zones/soc-thermal/trips/soc-crit";
+		bigcore0_thermal = "/thermal-zones/bigcore0-thermal";
+		bigcore1_thermal = "/thermal-zones/bigcore1-thermal";
+		little_core_thermal = "/thermal-zones/littlecore-thermal";
+		center_thermal = "/thermal-zones/center-thermal";
+		gpu_thermal = "/thermal-zones/gpu-thermal";
+		npu_thermal = "/thermal-zones/npu-thermal";
+		scmi_shmem = "/sram@10f000/sram@0";
+		gpu = "/gpu@fb000000";
+		gpu_opp_table = "/gpu-opp-table";
+		usbdrd3_0 = "/usbdrd3_0";
+		usbdrd_dwc3_0 = "/usbdrd3_0/usb@fc000000";
+		dwc3_0_role_switch = "/usbdrd3_0/usb@fc000000/port/endpoint@0";
+		usb_host0_ehci = "/usb@fc800000";
+		usb_host0_ohci = "/usb@fc840000";
+		usb_host1_ehci = "/usb@fc880000";
+		usb_host1_ohci = "/usb@fc8c0000";
+		mmu600_pcie = "/iommu@fc900000";
+		mmu600_php = "/iommu@fcb00000";
+		usbhost3_0 = "/usbhost3_0";
+		usbhost_dwc3_0 = "/usbhost3_0/usb@fcd00000";
+		pmu0_grf = "/syscon@fd588000";
+		reboot_mode = "/syscon@fd588000/reboot-mode";
+		pmu1_grf = "/syscon@fd58a000";
+		sys_grf = "/syscon@fd58c000";
+		rgb = "/syscon@fd58c000/rgb";
+		rgb_in_vp3 = "/syscon@fd58c000/rgb/ports/port@0/endpoint@2";
+		bigcore0_grf = "/syscon@fd590000";
+		bigcore1_grf = "/syscon@fd592000";
+		litcore_grf = "/syscon@fd594000";
+		dsu_grf = "/syscon@fd598000";
+		gpu_grf = "/syscon@fd5a0000";
+		npu_grf = "/syscon@fd5a2000";
+		vop_grf = "/syscon@fd5a4000";
+		vo0_grf = "/syscon@fd5a6000";
+		vo1_grf = "/syscon@fd5a8000";
+		usb_grf = "/syscon@fd5ac000";
+		php_grf = "/syscon@fd5b0000";
+		mipidphy0_grf = "/syscon@fd5b4000";
+		mipidphy1_grf = "/syscon@fd5b5000";
+		pipe_phy0_grf = "/syscon@fd5bc000";
+		pipe_phy2_grf = "/syscon@fd5c4000";
+		usbdpphy0_grf = "/syscon@fd5c8000";
+		usb2phy0_grf = "/syscon@fd5d0000";
+		u2phy0 = "/syscon@fd5d0000/usb2-phy@0";
+		u2phy0_otg = "/syscon@fd5d0000/usb2-phy@0/otg-port";
+		usb2phy2_grf = "/syscon@fd5d8000";
+		u2phy2 = "/syscon@fd5d8000/usb2-phy@8000";
+		u2phy2_host = "/syscon@fd5d8000/usb2-phy@8000/host-port";
+		usb2phy3_grf = "/syscon@fd5dc000";
+		u2phy3 = "/syscon@fd5dc000/usb2-phy@c000";
+		u2phy3_host = "/syscon@fd5dc000/usb2-phy@c000/host-port";
+		hdptxphy0_grf = "/syscon@fd5e0000";
+		mipidcphy0_grf = "/syscon@fd5e8000";
+		mipidcphy1_grf = "/syscon@fd5ec000";
+		ioc = "/syscon@fd5f0000";
+		cru = "/clock-controller@fd7c0000";
+		i2c0 = "/i2c@fd880000";
+		vdd_cpu_big0_s0 = "/i2c@fd880000/rk8602@42";
+		vdd_cpu_big0_mem_s0 = "/i2c@fd880000/rk8602@42";
+		vdd_cpu_big1_s0 = "/i2c@fd880000/rk8603@43";
+		vdd_cpu_big1_mem_s0 = "/i2c@fd880000/rk8603@43";
+		uart0 = "/serial@fd890000";
+		pwm0 = "/pwm@fd8b0000";
+		pwm1 = "/pwm@fd8b0010";
+		pwm2 = "/pwm@fd8b0020";
+		pwm3 = "/pwm@fd8b0030";
+		pmu = "/power-management@fd8d8000";
+		power = "/power-management@fd8d8000/power-controller";
+		rknpu = "/npu@fdab0000";
+		npu_opp_table = "/npu-opp-table";
+		rknpu_mmu = "/iommu@fdab9000";
+		vepu = "/vepu@fdb50000";
+		vdpu = "/vdpu@fdb50400";
+		vdpu_mmu = "/iommu@fdb50800";
+		avsd = "/avsd-plus@fdb51000";
+		rga3_core0 = "/rga@fdb60000";
+		rga3_0_mmu = "/iommu@fdb60f00";
+		rga3_core1 = "/rga@fdb70000";
+		rga3_1_mmu = "/iommu@fdb70f00";
+		rga2 = "/rga@fdb80000";
+		jpegd = "/jpegd@fdb90000";
+		jpegd_mmu = "/iommu@fdb90480";
+		jpege0 = "/jpege-core@fdba0000";
+		jpege0_mmu = "/iommu@fdba0800";
+		jpege1 = "/jpege-core@fdba4000";
+		jpege1_mmu = "/iommu@fdba4800";
+		jpege2 = "/jpege-core@fdba8000";
+		jpege2_mmu = "/iommu@fdba8800";
+		jpege3 = "/jpege-core@fdbac000";
+		jpege3_mmu = "/iommu@fdbac800";
+		iep = "/iep@fdbb0000";
+		iep_mmu = "/iommu@fdbb0800";
+		rkvenc0 = "/rkvenc-core@fdbd0000";
+		rkvenc0_mmu = "/iommu@fdbdf000";
+		rkvenc1 = "/rkvenc-core@fdbe0000";
+		rkvenc1_mmu = "/iommu@fdbef000";
+		rkvdec_ccu = "/rkvdec-ccu@fdc30000";
+		rkvdec0 = "/rkvdec-core@fdc38000";
+		rkvdec0_mmu = "/iommu@fdc38700";
+		rkvdec1 = "/rkvdec-core@fdc48000";
+		rkvdec1_mmu = "/iommu@fdc48700";
+		av1d = "/av1d@fdc70000";
+		av1d_mmu = "/iommu@fdca0000";
+		rkisp_unite = "/rkisp-unite@fdcb0000";
+		rkisp0 = "/rkisp@fdcb0000";
+		rkisp_unite_mmu = "/rkisp-unite-mmu@fdcb7f00";
+		isp0_mmu = "/iommu@fdcb7f00";
+		rkisp1 = "/rkisp@fdcc0000";
+		isp1_mmu = "/iommu@fdcc7f00";
+		rkispp0 = "/rkispp@fdcd0000";
+		fec0_mmu = "/iommu@fdcd0f00";
+		rkispp1 = "/rkispp@fdcd8000";
+		fec1_mmu = "/iommu@fdcd8f00";
+		rkcif = "/rkcif@fdce0000";
+		rkcif_mmu = "/iommu@fdce0800";
+		mipi0_csi2 = "/mipi0-csi2@fdd10000";
+		mipi0_csi2_input = "/mipi0-csi2@fdd10000/ports/port@0/endpoint@1";
+		mipi0_csi2_output = "/mipi0-csi2@fdd10000/ports/port@1/endpoint@0";
+		mipi1_csi2 = "/mipi1-csi2@fdd20000";
+		mipi1_csi2_input = "/mipi1-csi2@fdd20000/ports/port@0/endpoint@1";
+		mipi1_csi2_output = "/mipi1-csi2@fdd20000/ports/port@1/endpoint@0";
+		mipi2_csi2 = "/mipi2-csi2@fdd30000";
+		mipi2_csi2_input = "/mipi2-csi2@fdd30000/ports/port@0/endpoint@1";
+		mipi2_csi2_output = "/mipi2-csi2@fdd30000/ports/port@1/endpoint@0";
+		mipi3_csi2 = "/mipi3-csi2@fdd40000";
+		vop = "/vop@fdd90000";
+		vop_out = "/vop@fdd90000/ports";
+		vp0 = "/vop@fdd90000/ports/port@0";
+		vp0_out_dp0 = "/vop@fdd90000/ports/port@0/endpoint@0";
+		vp0_out_edp0 = "/vop@fdd90000/ports/port@0/endpoint@1";
+		vp0_out_hdmi0 = "/vop@fdd90000/ports/port@0/endpoint@2";
+		vp1 = "/vop@fdd90000/ports/port@1";
+		vp1_out_dp0 = "/vop@fdd90000/ports/port@1/endpoint@0";
+		vp1_out_edp0 = "/vop@fdd90000/ports/port@1/endpoint@1";
+		vp1_out_hdmi0 = "/vop@fdd90000/ports/port@1/endpoint@2";
+		vp2 = "/vop@fdd90000/ports/port@2";
+		vp2_out_dp0 = "/vop@fdd90000/ports/port@2/endpoint@0";
+		vp2_out_edp0 = "/vop@fdd90000/ports/port@2/endpoint@1";
+		vp2_out_hdmi0 = "/vop@fdd90000/ports/port@2/endpoint@2";
+		vp2_out_dsi0 = "/vop@fdd90000/ports/port@2/endpoint@3";
+		vp2_out_dsi1 = "/vop@fdd90000/ports/port@2/endpoint@4";
+		vp3 = "/vop@fdd90000/ports/port@3";
+		vp3_out_dsi0 = "/vop@fdd90000/ports/port@3/endpoint@0";
+		vp3_out_dsi1 = "/vop@fdd90000/ports/port@3/endpoint@1";
+		vp3_out_rgb = "/vop@fdd90000/ports/port@3/endpoint@2";
+		vop_mmu = "/iommu@fdd97e00";
+		spdif_tx2 = "/spdif-tx@fddb0000";
+		i2s4_8ch = "/i2s@fddc0000";
+		spdif_tx3 = "/spdif-tx@fdde0000";
+		i2s5_8ch = "/i2s@fddf0000";
+		i2s9_8ch = "/i2s@fddfc000";
+		spdif_rx0 = "/spdif-rx@fde08000";
+		dsi0 = "/dsi@fde20000";
+		dsi0_in = "/dsi@fde20000/ports/port@0";
+		dsi0_in_vp2 = "/dsi@fde20000/ports/port@0/endpoint@0";
+		dsi0_in_vp3 = "/dsi@fde20000/ports/port@0/endpoint@1";
+		dsi_out_panel = "/dsi@fde20000/ports/port@1/endpoint";
+		dsi0_panel = "/dsi@fde20000/panel@0";
+		panel_in_dsi = "/dsi@fde20000/panel@0/ports/port@0/endpoint";
+		dsi1 = "/dsi@fde30000";
+		dsi1_in = "/dsi@fde30000/ports/port@0";
+		dsi1_in_vp2 = "/dsi@fde30000/ports/port@0/endpoint@0";
+		dsi1_in_vp3 = "/dsi@fde30000/ports/port@0/endpoint@1";
+		dsi1_out_panel = "/dsi@fde30000/ports/port@1/endpoint";
+		dsi1_panel = "/dsi@fde30000/panel@0";
+		panel_in_dsi1 = "/dsi@fde30000/panel@0/ports/port@0/endpoint";
+		hdcp0 = "/hdcp@fde40000";
+		dp0 = "/dp@fde50000";
+		dp0_in = "/dp@fde50000/ports/port@0";
+		dp0_in_vp0 = "/dp@fde50000/ports/port@0/endpoint@0";
+		dp0_in_vp1 = "/dp@fde50000/ports/port@0/endpoint@1";
+		dp0_in_vp2 = "/dp@fde50000/ports/port@0/endpoint@2";
+		hdcp1 = "/hdcp@fde70000";
+		hdmi0 = "/hdmi@fde80000";
+		hdmi0_in = "/hdmi@fde80000/ports/port@0";
+		hdmi0_in_vp0 = "/hdmi@fde80000/ports/port@0/endpoint@0";
+		hdmi0_in_vp1 = "/hdmi@fde80000/ports/port@0/endpoint@1";
+		hdmi0_in_vp2 = "/hdmi@fde80000/ports/port@0/endpoint@2";
+		edp0 = "/edp@fdec0000";
+		edp0_in = "/edp@fdec0000/ports/port@0";
+		edp0_in_vp0 = "/edp@fdec0000/ports/port@0/endpoint@0";
+		edp0_in_vp1 = "/edp@fdec0000/ports/port@0/endpoint@1";
+		edp0_in_vp2 = "/edp@fdec0000/ports/port@0/endpoint@2";
+		qos_gpu_m0 = "/qos@fdf35000";
+		qos_gpu_m1 = "/qos@fdf35200";
+		qos_gpu_m2 = "/qos@fdf35400";
+		qos_gpu_m3 = "/qos@fdf35600";
+		qos_rga3_1 = "/qos@fdf36000";
+		qos_sdio = "/qos@fdf39000";
+		qos_sdmmc = "/qos@fdf3d800";
+		qos_usb3_1 = "/qos@fdf3e000";
+		qos_usb3_0 = "/qos@fdf3e200";
+		qos_usb2host_0 = "/qos@fdf3e400";
+		qos_usb2host_1 = "/qos@fdf3e600";
+		qos_fisheye0 = "/qos@fdf40000";
+		qos_fisheye1 = "/qos@fdf40200";
+		qos_isp0_mro = "/qos@fdf40400";
+		qos_isp0_mwo = "/qos@fdf40500";
+		qos_vicap_m0 = "/qos@fdf40600";
+		qos_vicap_m1 = "/qos@fdf40800";
+		qos_isp1_mwo = "/qos@fdf41000";
+		qos_isp1_mro = "/qos@fdf41100";
+		qos_rkvenc0_m0ro = "/qos@fdf60000";
+		qos_rkvenc0_m1ro = "/qos@fdf60200";
+		qos_rkvenc0_m2wo = "/qos@fdf60400";
+		qos_rkvenc1_m0ro = "/qos@fdf61000";
+		qos_rkvenc1_m1ro = "/qos@fdf61200";
+		qos_rkvenc1_m2wo = "/qos@fdf61400";
+		qos_rkvdec0 = "/qos@fdf62000";
+		qos_rkvdec1 = "/qos@fdf63000";
+		qos_av1 = "/qos@fdf64000";
+		qos_iep = "/qos@fdf66000";
+		qos_jpeg_dec = "/qos@fdf66200";
+		qos_jpeg_enc0 = "/qos@fdf66400";
+		qos_jpeg_enc1 = "/qos@fdf66600";
+		qos_jpeg_enc2 = "/qos@fdf66800";
+		qos_jpeg_enc3 = "/qos@fdf66a00";
+		qos_rga2_mro = "/qos@fdf66c00";
+		qos_rga2_mwo = "/qos@fdf66e00";
+		qos_rga3_0 = "/qos@fdf67000";
+		qos_vdpu = "/qos@fdf67200";
+		qos_npu1 = "/qos@fdf70000";
+		qos_npu2 = "/qos@fdf71000";
+		qos_npu0_mwr = "/qos@fdf72000";
+		qos_npu0_mro = "/qos@fdf72200";
+		qos_mcu_npu = "/qos@fdf72400";
+		qos_hdcp0 = "/qos@fdf80000";
+		qos_hdcp1 = "/qos@fdf81000";
+		qos_hdmirx = "/qos@fdf81200";
+		qos_vop_m0 = "/qos@fdf82000";
+		qos_vop_m1 = "/qos@fdf82200";
+		dfi = "/dfi@fe060000";
+		pcie2x1l1 = "/pcie@fe180000";
+		pcie2x1l1_intc = "/pcie@fe180000/legacy-interrupt-controller";
+		pcie2x1l2 = "/pcie@fe190000";
+		pcie2x1l2_intc = "/pcie@fe190000/legacy-interrupt-controller";
+		gmac1 = "/ethernet@fe1c0000";
+		mdio1 = "/ethernet@fe1c0000/mdio";
+		rgmii_phy1 = "/ethernet@fe1c0000/mdio/phy@1";
+		gmac1_stmmac_axi_setup = "/ethernet@fe1c0000/stmmac-axi-config";
+		gmac1_mtl_rx_setup = "/ethernet@fe1c0000/rx-queues-config";
+		gmac1_mtl_tx_setup = "/ethernet@fe1c0000/tx-queues-config";
+		sata0 = "/sata@fe210000";
+		sata2 = "/sata@fe230000";
+		sfc = "/spi@fe2b0000";
+		spi_flash = "/spi@fe2b0000/spi-flash@0";
+		sdmmc = "/mmc@fe2c0000";
+		sdio = "/mmc@fe2d0000";
+		sdhci = "/mmc@fe2e0000";
+		crypto = "/crypto@fe370000";
+		rng = "/rng@fe378000";
+		i2s0_8ch = "/i2s@fe470000";
+		i2s1_8ch = "/i2s@fe480000";
+		i2s2_2ch = "/i2s@fe490000";
+		i2s3_2ch = "/i2s@fe4a0000";
+		pdm0 = "/pdm@fe4b0000";
+		pdm1 = "/pdm@fe4c0000";
+		vad = "/vad@fe4d0000";
+		spdif_tx0 = "/spdif-tx@fe4e0000";
+		spdif_tx1 = "/spdif-tx@fe4f0000";
+		acdcdig_dsm = "/codec-digital@fe500000";
+		hwlock = "/hwspinlock@fe5a0000";
+		gic = "/interrupt-controller@fe600000";
+		its0 = "/interrupt-controller@fe600000/msi-controller@fe640000";
+		its1 = "/interrupt-controller@fe600000/msi-controller@fe660000";
+		dmac0 = "/dma-controller@fea10000";
+		dmac1 = "/dma-controller@fea30000";
+		can0 = "/can@fea50000";
+		can1 = "/can@fea60000";
+		can2 = "/can@fea70000";
+		hw_decompress = "/decompress@fea80000";
+		i2c1 = "/i2c@fea90000";
+		i2c2 = "/i2c@feaa0000";
+		gt9xx_0 = "/i2c@feaa0000/touchscreen@14";
+		vm149cp1 = "/i2c@feaa0000/vm149c@c";
+		ov13850_3 = "/i2c@feaa0000/ov13850@10";
+		ov13850_out1 = "/i2c@feaa0000/ov13850@10/port/endpoint";
+		dw9714 = "/i2c@feaa0000/dw9714@c";
+		ov13855_3 = "/i2c@feaa0000/ov13855@36";
+		ov13855_out1 = "/i2c@feaa0000/ov13855@36/port/endpoint";
+		vdd_npu_s0 = "/i2c@feaa0000/rk8602@42";
+		vdd_npu_mem_s0 = "/i2c@feaa0000/rk8602@42";
+		i2c3 = "/i2c@feab0000";
+		i2c4 = "/i2c@feac0000";
+		i2c5 = "/i2c@fead0000";
+		rktimer = "/timer@feae0000";
+		wdt = "/watchdog@feaf0000";
+		spi0 = "/spi@feb00000";
+		spi1 = "/spi@feb10000";
+		spi2 = "/spi@feb20000";
+		rk806single = "/spi@feb20000/rk806single@0";
+		pinctrl_rk806 = "/spi@feb20000/rk806single@0/pinctrl_rk806";
+		rk806_dvs1_null = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs1_null";
+		rk806_dvs1_slp = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs1_slp";
+		rk806_dvs1_pwrdn = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs1_pwrdn";
+		rk806_dvs1_rst = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs1_rst";
+		rk806_dvs2_null = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_null";
+		rk806_dvs2_slp = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_slp";
+		rk806_dvs2_pwrdn = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_pwrdn";
+		rk806_dvs2_rst = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_rst";
+		rk806_dvs2_dvs = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_dvs";
+		rk806_dvs2_gpio = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_gpio";
+		rk806_dvs3_null = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_null";
+		rk806_dvs3_slp = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_slp";
+		rk806_dvs3_pwrdn = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_pwrdn";
+		rk806_dvs3_rst = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_rst";
+		rk806_dvs3_dvs = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_dvs";
+		rk806_dvs3_gpio = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_gpio";
+		vdd_gpu_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG1";
+		vdd_gpu_mem_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG1";
+		vdd_cpu_lit_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG2";
+		vdd_cpu_lit_mem_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG2";
+		vdd_log_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG3";
+		vdd_vdenc_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG4";
+		vdd_vdenc_mem_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG4";
+		vdd_ddr_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG5";
+		vdd2_ddr_s3 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG6";
+		vcc_2v0_pldo_s3 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG7";
+		vcc_3v3_s3 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG8";
+		vddq_ddr_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG9";
+		vcc_1v8_s3 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG10";
+		avcc_1v8_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG1";
+		vcc_1v8_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG2";
+		avdd_1v2_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG3";
+		vcc_3v3_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG4";
+		vccio_sd_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG5";
+		pldo6_s3 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG6";
+		vdd_0v75_s3 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG1";
+		vdd_ddr_pll_s0 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG2";
+		avdd_0v75_s0 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG3";
+		vdd_0v85_s0 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG4";
+		vdd_0v75_s0 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG5";
+		spi3 = "/spi@feb30000";
+		uart1 = "/serial@feb40000";
+		uart2 = "/serial@feb50000";
+		uart3 = "/serial@feb60000";
+		uart4 = "/serial@feb70000";
+		uart5 = "/serial@feb80000";
+		uart6 = "/serial@feb90000";
+		uart7 = "/serial@feba0000";
+		uart8 = "/serial@febb0000";
+		uart9 = "/serial@febc0000";
+		pwm4 = "/pwm@febd0000";
+		pwm5 = "/pwm@febd0010";
+		pwm6 = "/pwm@febd0020";
+		pwm7 = "/pwm@febd0030";
+		pwm8 = "/pwm@febe0000";
+		pwm9 = "/pwm@febe0010";
+		pwm10 = "/pwm@febe0020";
+		pwm11 = "/pwm@febe0030";
+		pwm12 = "/pwm@febf0000";
+		pwm13 = "/pwm@febf0010";
+		pwm14 = "/pwm@febf0020";
+		pwm15 = "/pwm@febf0030";
+		tsadc = "/tsadc@fec00000";
+		saradc = "/saradc@fec10000";
+		mailbox0 = "/mailbox@fec60000";
+		mailbox1 = "/mailbox@fec70000";
+		i2c6 = "/i2c@fec80000";
+		es8388 = "/i2c@fec80000/es8388@10";
+		usbc0 = "/i2c@fec80000/fusb302@22";
+		usbc0_role_sw = "/i2c@fec80000/fusb302@22/ports/port@0/endpoint@0";
+		usb_con = "/i2c@fec80000/fusb302@22/connector";
+		usbc0_orien_sw = "/i2c@fec80000/fusb302@22/connector/ports/port@0/endpoint";
+		dp_altmode_mux = "/i2c@fec80000/fusb302@22/connector/ports/port@1/endpoint";
+		hym8563 = "/i2c@fec80000/hym8563@51";
+		i2c7 = "/i2c@fec90000";
+		gt9xx_1 = "/i2c@fec90000/touchscreen@14";
+		vm149c_p1 = "/i2c@fec90000/vm149c-p1@c";
+		ov13850_1 = "/i2c@fec90000/ov13850-1@10";
+		ov13850_out2 = "/i2c@fec90000/ov13850-1@10/port/endpoint";
+		dw9714_p1 = "/i2c@fec90000/dw9714-p1@c";
+		ov13855_1 = "/i2c@fec90000/ov13855-1@36";
+		ov13855_out2 = "/i2c@fec90000/ov13855-1@36/port/endpoint";
+		vm149c_p2 = "/i2c@fec90000/vm149c-p2@c";
+		ov13850_2 = "/i2c@fec90000/ov13850-2@10";
+		ov13850_out = "/i2c@fec90000/ov13850-2@10/port/endpoint";
+		dw9714_p2 = "/i2c@fec90000/dw9714-p2@c";
+		ov13855_2 = "/i2c@fec90000/ov13855-2@36";
+		ov13855_out = "/i2c@fec90000/ov13855-2@36/port/endpoint";
+		i2c8 = "/i2c@feca0000";
+		spi4 = "/spi@fecb0000";
+		otp = "/otp@fecc0000";
+		cpu_code = "/otp@fecc0000/cpu-code@2";
+		specification_serial_number = "/otp@fecc0000/specification-serial-number@6";
+		otp_id = "/otp@fecc0000/id@7";
+		otp_cpu_version = "/otp@fecc0000/cpu-version@1c";
+		cpub0_leakage = "/otp@fecc0000/cpub0-leakage@17";
+		cpub1_leakage = "/otp@fecc0000/cpub1-leakage@18";
+		cpul_leakage = "/otp@fecc0000/cpul-leakage@19";
+		log_leakage = "/otp@fecc0000/log-leakage@1a";
+		gpu_leakage = "/otp@fecc0000/gpu-leakage@1b";
+		npu_leakage = "/otp@fecc0000/npu-leakage@28";
+		codec_leakage = "/otp@fecc0000/codec-leakage@29";
+		mailbox2 = "/mailbox@fece0000";
+		dmac2 = "/dma-controller@fed10000";
+		hdptxphy0 = "/phy@fed60000";
+		hdptxphy_hdmi0 = "/hdmiphy@fed60000";
+		hdptxphy_hdmi_clk0 = "/hdmiphy@fed60000/clk-port";
+		usbdp_phy0 = "/phy@fed80000";
+		usbdp_phy0_dp = "/phy@fed80000/dp-port";
+		usbdp_phy0_u3 = "/phy@fed80000/u3-port";
+		usbdp_phy0_orientation_switch = "/phy@fed80000/port/endpoint@0";
+		usbdp_phy0_dp_altmode_mux = "/phy@fed80000/port/endpoint@1";
+		mipi_dcphy0 = "/phy@feda0000";
+		mipi_dcphy1 = "/phy@fedb0000";
+		csi2_dphy0_hw = "/csi2-dphy0-hw@fedc0000";
+		combphy0_ps = "/phy@fee00000";
+		combphy2_psu = "/phy@fee20000";
+		syssram = "/sram@ff001000";
+		rkvdec0_sram = "/sram@ff001000/rkvdec-sram@0";
+		rkvdec1_sram = "/sram@ff001000/rkvdec-sram@78000";
+		pinctrl = "/pinctrl";
+		gpio0 = "/pinctrl/gpio@fd8a0000";
+		gpio1 = "/pinctrl/gpio@fec20000";
+		gpio2 = "/pinctrl/gpio@fec30000";
+		gpio3 = "/pinctrl/gpio@fec40000";
+		gpio4 = "/pinctrl/gpio@fec50000";
+		pcfg_pull_up = "/pinctrl/pcfg-pull-up";
+		pcfg_pull_down = "/pinctrl/pcfg-pull-down";
+		pcfg_pull_none = "/pinctrl/pcfg-pull-none";
+		pcfg_pull_none_drv_level_0 = "/pinctrl/pcfg-pull-none-drv-level-0";
+		pcfg_pull_none_drv_level_1 = "/pinctrl/pcfg-pull-none-drv-level-1";
+		pcfg_pull_none_drv_level_2 = "/pinctrl/pcfg-pull-none-drv-level-2";
+		pcfg_pull_none_drv_level_3 = "/pinctrl/pcfg-pull-none-drv-level-3";
+		pcfg_pull_none_drv_level_4 = "/pinctrl/pcfg-pull-none-drv-level-4";
+		pcfg_pull_none_drv_level_5 = "/pinctrl/pcfg-pull-none-drv-level-5";
+		pcfg_pull_none_drv_level_6 = "/pinctrl/pcfg-pull-none-drv-level-6";
+		pcfg_pull_none_drv_level_7 = "/pinctrl/pcfg-pull-none-drv-level-7";
+		pcfg_pull_none_drv_level_8 = "/pinctrl/pcfg-pull-none-drv-level-8";
+		pcfg_pull_none_drv_level_9 = "/pinctrl/pcfg-pull-none-drv-level-9";
+		pcfg_pull_none_drv_level_10 = "/pinctrl/pcfg-pull-none-drv-level-10";
+		pcfg_pull_none_drv_level_11 = "/pinctrl/pcfg-pull-none-drv-level-11";
+		pcfg_pull_none_drv_level_12 = "/pinctrl/pcfg-pull-none-drv-level-12";
+		pcfg_pull_none_drv_level_13 = "/pinctrl/pcfg-pull-none-drv-level-13";
+		pcfg_pull_none_drv_level_14 = "/pinctrl/pcfg-pull-none-drv-level-14";
+		pcfg_pull_none_drv_level_15 = "/pinctrl/pcfg-pull-none-drv-level-15";
+		pcfg_pull_up_drv_level_0 = "/pinctrl/pcfg-pull-up-drv-level-0";
+		pcfg_pull_up_drv_level_1 = "/pinctrl/pcfg-pull-up-drv-level-1";
+		pcfg_pull_up_drv_level_2 = "/pinctrl/pcfg-pull-up-drv-level-2";
+		pcfg_pull_up_drv_level_3 = "/pinctrl/pcfg-pull-up-drv-level-3";
+		pcfg_pull_up_drv_level_4 = "/pinctrl/pcfg-pull-up-drv-level-4";
+		pcfg_pull_up_drv_level_5 = "/pinctrl/pcfg-pull-up-drv-level-5";
+		pcfg_pull_up_drv_level_6 = "/pinctrl/pcfg-pull-up-drv-level-6";
+		pcfg_pull_up_drv_level_7 = "/pinctrl/pcfg-pull-up-drv-level-7";
+		pcfg_pull_up_drv_level_8 = "/pinctrl/pcfg-pull-up-drv-level-8";
+		pcfg_pull_up_drv_level_9 = "/pinctrl/pcfg-pull-up-drv-level-9";
+		pcfg_pull_up_drv_level_10 = "/pinctrl/pcfg-pull-up-drv-level-10";
+		pcfg_pull_up_drv_level_11 = "/pinctrl/pcfg-pull-up-drv-level-11";
+		pcfg_pull_up_drv_level_12 = "/pinctrl/pcfg-pull-up-drv-level-12";
+		pcfg_pull_up_drv_level_13 = "/pinctrl/pcfg-pull-up-drv-level-13";
+		pcfg_pull_up_drv_level_14 = "/pinctrl/pcfg-pull-up-drv-level-14";
+		pcfg_pull_up_drv_level_15 = "/pinctrl/pcfg-pull-up-drv-level-15";
+		pcfg_pull_down_drv_level_0 = "/pinctrl/pcfg-pull-down-drv-level-0";
+		pcfg_pull_down_drv_level_1 = "/pinctrl/pcfg-pull-down-drv-level-1";
+		pcfg_pull_down_drv_level_2 = "/pinctrl/pcfg-pull-down-drv-level-2";
+		pcfg_pull_down_drv_level_3 = "/pinctrl/pcfg-pull-down-drv-level-3";
+		pcfg_pull_down_drv_level_4 = "/pinctrl/pcfg-pull-down-drv-level-4";
+		pcfg_pull_down_drv_level_5 = "/pinctrl/pcfg-pull-down-drv-level-5";
+		pcfg_pull_down_drv_level_6 = "/pinctrl/pcfg-pull-down-drv-level-6";
+		pcfg_pull_down_drv_level_7 = "/pinctrl/pcfg-pull-down-drv-level-7";
+		pcfg_pull_down_drv_level_8 = "/pinctrl/pcfg-pull-down-drv-level-8";
+		pcfg_pull_down_drv_level_9 = "/pinctrl/pcfg-pull-down-drv-level-9";
+		pcfg_pull_down_drv_level_10 = "/pinctrl/pcfg-pull-down-drv-level-10";
+		pcfg_pull_down_drv_level_11 = "/pinctrl/pcfg-pull-down-drv-level-11";
+		pcfg_pull_down_drv_level_12 = "/pinctrl/pcfg-pull-down-drv-level-12";
+		pcfg_pull_down_drv_level_13 = "/pinctrl/pcfg-pull-down-drv-level-13";
+		pcfg_pull_down_drv_level_14 = "/pinctrl/pcfg-pull-down-drv-level-14";
+		pcfg_pull_down_drv_level_15 = "/pinctrl/pcfg-pull-down-drv-level-15";
+		pcfg_pull_up_smt = "/pinctrl/pcfg-pull-up-smt";
+		pcfg_pull_down_smt = "/pinctrl/pcfg-pull-down-smt";
+		pcfg_pull_none_smt = "/pinctrl/pcfg-pull-none-smt";
+		pcfg_pull_none_drv_level_0_smt = "/pinctrl/pcfg-pull-none-drv-level-0-smt";
+		pcfg_pull_none_drv_level_1_smt = "/pinctrl/pcfg-pull-none-drv-level-1-smt";
+		pcfg_pull_none_drv_level_2_smt = "/pinctrl/pcfg-pull-none-drv-level-2-smt";
+		pcfg_pull_none_drv_level_3_smt = "/pinctrl/pcfg-pull-none-drv-level-3-smt";
+		pcfg_pull_none_drv_level_4_smt = "/pinctrl/pcfg-pull-none-drv-level-4-smt";
+		pcfg_pull_none_drv_level_5_smt = "/pinctrl/pcfg-pull-none-drv-level-5-smt";
+		pcfg_output_high = "/pinctrl/pcfg-output-high";
+		pcfg_output_high_pull_up = "/pinctrl/pcfg-output-high-pull-up";
+		pcfg_output_high_pull_down = "/pinctrl/pcfg-output-high-pull-down";
+		pcfg_output_high_pull_none = "/pinctrl/pcfg-output-high-pull-none";
+		pcfg_output_low = "/pinctrl/pcfg-output-low";
+		pcfg_output_low_pull_up = "/pinctrl/pcfg-output-low-pull-up";
+		pcfg_output_low_pull_down = "/pinctrl/pcfg-output-low-pull-down";
+		pcfg_output_low_pull_none = "/pinctrl/pcfg-output-low-pull-none";
+		auddsm_pins = "/pinctrl/auddsm/auddsm-pins";
+		bt1120_pins = "/pinctrl/bt1120/bt1120-pins";
+		can0m0_pins = "/pinctrl/can0/can0m0-pins";
+		can0m1_pins = "/pinctrl/can0/can0m1-pins";
+		can1m0_pins = "/pinctrl/can1/can1m0-pins";
+		can1m1_pins = "/pinctrl/can1/can1m1-pins";
+		can2m0_pins = "/pinctrl/can2/can2m0-pins";
+		can2m1_pins = "/pinctrl/can2/can2m1-pins";
+		cif_clk = "/pinctrl/cif/cif-clk";
+		cif_dvp_clk = "/pinctrl/cif/cif-dvp-clk";
+		cif_dvp_bus16 = "/pinctrl/cif/cif-dvp-bus16";
+		cif_dvp_bus8 = "/pinctrl/cif/cif-dvp-bus8";
+		clk32k_in = "/pinctrl/clk32k/clk32k-in";
+		clk32k_out0 = "/pinctrl/clk32k/clk32k-out0";
+		cpu_pins = "/pinctrl/cpu/cpu-pins";
+		ddrphych0_pins = "/pinctrl/ddrphych0/ddrphych0-pins";
+		ddrphych1_pins = "/pinctrl/ddrphych1/ddrphych1-pins";
+		ddrphych2_pins = "/pinctrl/ddrphych2/ddrphych2-pins";
+		ddrphych3_pins = "/pinctrl/ddrphych3/ddrphych3-pins";
+		dp0m0_pins = "/pinctrl/dp0/dp0m0-pins";
+		dp0m1_pins = "/pinctrl/dp0/dp0m1-pins";
+		dp0m2_pins = "/pinctrl/dp0/dp0m2-pins";
+		dp1m0_pins = "/pinctrl/dp1/dp1m0-pins";
+		dp1m1_pins = "/pinctrl/dp1/dp1m1-pins";
+		dp1m2_pins = "/pinctrl/dp1/dp1m2-pins";
+		emmc_rstnout = "/pinctrl/emmc/emmc-rstnout";
+		emmc_bus8 = "/pinctrl/emmc/emmc-bus8";
+		emmc_clk = "/pinctrl/emmc/emmc-clk";
+		emmc_cmd = "/pinctrl/emmc/emmc-cmd";
+		emmc_data_strobe = "/pinctrl/emmc/emmc-data-strobe";
+		eth1_pins = "/pinctrl/eth1/eth1-pins";
+		fspim0_pins = "/pinctrl/fspi/fspim0-pins";
+		fspim0_cs1 = "/pinctrl/fspi/fspim0-cs1";
+		fspim2_pins = "/pinctrl/fspi/fspim2-pins";
+		fspim2_cs1 = "/pinctrl/fspi/fspim2-cs1";
+		gmac1_miim = "/pinctrl/gmac1/gmac1-miim";
+		gmac1_clkinout = "/pinctrl/gmac1/gmac1-clkinout";
+		gmac1_rx_bus2 = "/pinctrl/gmac1/gmac1-rx-bus2";
+		gmac1_tx_bus2 = "/pinctrl/gmac1/gmac1-tx-bus2";
+		gmac1_rgmii_clk = "/pinctrl/gmac1/gmac1-rgmii-clk";
+		gmac1_rgmii_bus = "/pinctrl/gmac1/gmac1-rgmii-bus";
+		gmac1_ppsclk = "/pinctrl/gmac1/gmac1-ppsclk";
+		gmac1_ppstrig = "/pinctrl/gmac1/gmac1-ppstrig";
+		gmac1_ptp_ref_clk = "/pinctrl/gmac1/gmac1-ptp-ref-clk";
+		gmac1_txer = "/pinctrl/gmac1/gmac1-txer";
+		gpu_pins = "/pinctrl/gpu/gpu-pins";
+		hdmim0_rx_cec = "/pinctrl/hdmi/hdmim0-rx-cec";
+		hdmim0_rx_hpdin = "/pinctrl/hdmi/hdmim0-rx-hpdin";
+		hdmim0_rx_scl = "/pinctrl/hdmi/hdmim0-rx-scl";
+		hdmim0_rx_sda = "/pinctrl/hdmi/hdmim0-rx-sda";
+		hdmim0_tx0_cec = "/pinctrl/hdmi/hdmim0-tx0-cec";
+		hdmim0_tx0_hpd = "/pinctrl/hdmi/hdmim0-tx0-hpd";
+		hdmim0_tx0_scl = "/pinctrl/hdmi/hdmim0-tx0-scl";
+		hdmim0_tx0_sda = "/pinctrl/hdmi/hdmim0-tx0-sda";
+		hdmim0_tx1_hpd = "/pinctrl/hdmi/hdmim0-tx1-hpd";
+		hdmim1_rx = "/pinctrl/hdmi/hdmim1-rx";
+		hdmim1_rx_cec = "/pinctrl/hdmi/hdmim1-rx-cec";
+		hdmim1_rx_hpdin = "/pinctrl/hdmi/hdmim1-rx-hpdin";
+		hdmim1_rx_scl = "/pinctrl/hdmi/hdmim1-rx-scl";
+		hdmim1_rx_sda = "/pinctrl/hdmi/hdmim1-rx-sda";
+		hdmim1_tx0_cec = "/pinctrl/hdmi/hdmim1-tx0-cec";
+		hdmim1_tx0_hpd = "/pinctrl/hdmi/hdmim1-tx0-hpd";
+		hdmim1_tx0_scl = "/pinctrl/hdmi/hdmim1-tx0-scl";
+		hdmim1_tx0_sda = "/pinctrl/hdmi/hdmim1-tx0-sda";
+		hdmim1_tx1_cec = "/pinctrl/hdmi/hdmim1-tx1-cec";
+		hdmim1_tx1_hpd = "/pinctrl/hdmi/hdmim1-tx1-hpd";
+		hdmim1_tx1_scl = "/pinctrl/hdmi/hdmim1-tx1-scl";
+		hdmim1_tx1_sda = "/pinctrl/hdmi/hdmim1-tx1-sda";
+		hdmim2_rx_cec = "/pinctrl/hdmi/hdmim2-rx-cec";
+		hdmim2_rx_hpdin = "/pinctrl/hdmi/hdmim2-rx-hpdin";
+		hdmim2_rx_scl = "/pinctrl/hdmi/hdmim2-rx-scl";
+		hdmim2_rx_sda = "/pinctrl/hdmi/hdmim2-rx-sda";
+		hdmim2_tx0_scl = "/pinctrl/hdmi/hdmim2-tx0-scl";
+		hdmim2_tx0_sda = "/pinctrl/hdmi/hdmim2-tx0-sda";
+		hdmim2_tx1_cec = "/pinctrl/hdmi/hdmim2-tx1-cec";
+		hdmim2_tx1_scl = "/pinctrl/hdmi/hdmim2-tx1-scl";
+		hdmim2_tx1_sda = "/pinctrl/hdmi/hdmim2-tx1-sda";
+		hdmi_debug0 = "/pinctrl/hdmi/hdmi-debug0";
+		hdmi_debug1 = "/pinctrl/hdmi/hdmi-debug1";
+		hdmi_debug2 = "/pinctrl/hdmi/hdmi-debug2";
+		hdmi_debug3 = "/pinctrl/hdmi/hdmi-debug3";
+		hdmi_debug4 = "/pinctrl/hdmi/hdmi-debug4";
+		hdmi_debug5 = "/pinctrl/hdmi/hdmi-debug5";
+		hdmi_debug6 = "/pinctrl/hdmi/hdmi-debug6";
+		i2c0m0_xfer = "/pinctrl/i2c0/i2c0m0-xfer";
+		i2c0m2_xfer = "/pinctrl/i2c0/i2c0m2-xfer";
+		i2c1m0_xfer = "/pinctrl/i2c1/i2c1m0-xfer";
+		i2c1m1_xfer = "/pinctrl/i2c1/i2c1m1-xfer";
+		i2c1m2_xfer = "/pinctrl/i2c1/i2c1m2-xfer";
+		i2c1m3_xfer = "/pinctrl/i2c1/i2c1m3-xfer";
+		i2c1m4_xfer = "/pinctrl/i2c1/i2c1m4-xfer";
+		i2c2m0_xfer = "/pinctrl/i2c2/i2c2m0-xfer";
+		i2c2m2_xfer = "/pinctrl/i2c2/i2c2m2-xfer";
+		i2c2m3_xfer = "/pinctrl/i2c2/i2c2m3-xfer";
+		i2c2m4_xfer = "/pinctrl/i2c2/i2c2m4-xfer";
+		i2c3m0_xfer = "/pinctrl/i2c3/i2c3m0-xfer";
+		i2c3m1_xfer = "/pinctrl/i2c3/i2c3m1-xfer";
+		i2c3m2_xfer = "/pinctrl/i2c3/i2c3m2-xfer";
+		i2c3m4_xfer = "/pinctrl/i2c3/i2c3m4-xfer";
+		i2c4m0_xfer = "/pinctrl/i2c4/i2c4m0-xfer";
+		i2c4m2_xfer = "/pinctrl/i2c4/i2c4m2-xfer";
+		i2c4m3_xfer = "/pinctrl/i2c4/i2c4m3-xfer";
+		i2c4m4_xfer = "/pinctrl/i2c4/i2c4m4-xfer";
+		i2c5m0_xfer = "/pinctrl/i2c5/i2c5m0-xfer";
+		i2c5m1_xfer = "/pinctrl/i2c5/i2c5m1-xfer";
+		i2c5m2_xfer = "/pinctrl/i2c5/i2c5m2-xfer";
+		i2c5m3_xfer = "/pinctrl/i2c5/i2c5m3-xfer";
+		i2c6m0_xfer = "/pinctrl/i2c6/i2c6m0-xfer";
+		i2c6m1_xfer = "/pinctrl/i2c6/i2c6m1-xfer";
+		i2c6m3_xfer = "/pinctrl/i2c6/i2c6m3-xfer";
+		i2c6m4_xfer = "/pinctrl/i2c6/i2c6m4-xfer";
+		i2c7m0_xfer = "/pinctrl/i2c7/i2c7m0-xfer";
+		i2c7m2_xfer = "/pinctrl/i2c7/i2c7m2-xfer";
+		i2c7m3_xfer = "/pinctrl/i2c7/i2c7m3-xfer";
+		i2c8m0_xfer = "/pinctrl/i2c8/i2c8m0-xfer";
+		i2c8m2_xfer = "/pinctrl/i2c8/i2c8m2-xfer";
+		i2c8m3_xfer = "/pinctrl/i2c8/i2c8m3-xfer";
+		i2c8m4_xfer = "/pinctrl/i2c8/i2c8m4-xfer";
+		i2s0_lrck = "/pinctrl/i2s0/i2s0-lrck";
+		i2s0_mclk = "/pinctrl/i2s0/i2s0-mclk";
+		i2s0_sclk = "/pinctrl/i2s0/i2s0-sclk";
+		i2s0_sdi0 = "/pinctrl/i2s0/i2s0-sdi0";
+		i2s0_sdi1 = "/pinctrl/i2s0/i2s0-sdi1";
+		i2s0_sdi2 = "/pinctrl/i2s0/i2s0-sdi2";
+		i2s0_sdi3 = "/pinctrl/i2s0/i2s0-sdi3";
+		i2s0_sdo0 = "/pinctrl/i2s0/i2s0-sdo0";
+		i2s0_sdo1 = "/pinctrl/i2s0/i2s0-sdo1";
+		i2s0_sdo2 = "/pinctrl/i2s0/i2s0-sdo2";
+		i2s0_sdo3 = "/pinctrl/i2s0/i2s0-sdo3";
+		i2s1m0_lrck = "/pinctrl/i2s1/i2s1m0-lrck";
+		i2s1m0_mclk = "/pinctrl/i2s1/i2s1m0-mclk";
+		i2s1m0_sclk = "/pinctrl/i2s1/i2s1m0-sclk";
+		i2s1m0_sdi0 = "/pinctrl/i2s1/i2s1m0-sdi0";
+		i2s1m0_sdi1 = "/pinctrl/i2s1/i2s1m0-sdi1";
+		i2s1m0_sdi2 = "/pinctrl/i2s1/i2s1m0-sdi2";
+		i2s1m0_sdi3 = "/pinctrl/i2s1/i2s1m0-sdi3";
+		i2s1m0_sdo0 = "/pinctrl/i2s1/i2s1m0-sdo0";
+		i2s1m0_sdo1 = "/pinctrl/i2s1/i2s1m0-sdo1";
+		i2s1m0_sdo2 = "/pinctrl/i2s1/i2s1m0-sdo2";
+		i2s1m0_sdo3 = "/pinctrl/i2s1/i2s1m0-sdo3";
+		i2s1m1_lrck = "/pinctrl/i2s1/i2s1m1-lrck";
+		i2s1m1_mclk = "/pinctrl/i2s1/i2s1m1-mclk";
+		i2s1m1_sclk = "/pinctrl/i2s1/i2s1m1-sclk";
+		i2s1m1_sdi0 = "/pinctrl/i2s1/i2s1m1-sdi0";
+		i2s1m1_sdi1 = "/pinctrl/i2s1/i2s1m1-sdi1";
+		i2s1m1_sdi2 = "/pinctrl/i2s1/i2s1m1-sdi2";
+		i2s1m1_sdi3 = "/pinctrl/i2s1/i2s1m1-sdi3";
+		i2s1m1_sdo0 = "/pinctrl/i2s1/i2s1m1-sdo0";
+		i2s1m1_sdo1 = "/pinctrl/i2s1/i2s1m1-sdo1";
+		i2s1m1_sdo2 = "/pinctrl/i2s1/i2s1m1-sdo2";
+		i2s1m1_sdo3 = "/pinctrl/i2s1/i2s1m1-sdo3";
+		i2s2m1_lrck = "/pinctrl/i2s2/i2s2m1-lrck";
+		i2s2m1_mclk = "/pinctrl/i2s2/i2s2m1-mclk";
+		i2s2m1_sclk = "/pinctrl/i2s2/i2s2m1-sclk";
+		i2s2m1_sdi = "/pinctrl/i2s2/i2s2m1-sdi";
+		i2s2m1_sdo = "/pinctrl/i2s2/i2s2m1-sdo";
+		i2s3_lrck = "/pinctrl/i2s3/i2s3-lrck";
+		i2s3_mclk = "/pinctrl/i2s3/i2s3-mclk";
+		i2s3_sclk = "/pinctrl/i2s3/i2s3-sclk";
+		i2s3_sdi = "/pinctrl/i2s3/i2s3-sdi";
+		i2s3_sdo = "/pinctrl/i2s3/i2s3-sdo";
+		jtagm0_pins = "/pinctrl/jtag/jtagm0-pins";
+		jtagm1_pins = "/pinctrl/jtag/jtagm1-pins";
+		jtagm2_pins = "/pinctrl/jtag/jtagm2-pins";
+		litcpu_pins = "/pinctrl/litcpu/litcpu-pins";
+		mcum0_pins = "/pinctrl/mcu/mcum0-pins";
+		mcum1_pins = "/pinctrl/mcu/mcum1-pins";
+		mipim0_camera0_clk = "/pinctrl/mipi/mipim0-camera0-clk";
+		mipim0_camera1_clk = "/pinctrl/mipi/mipim0-camera1-clk";
+		mipim0_camera2_clk = "/pinctrl/mipi/mipim0-camera2-clk";
+		mipim0_camera3_clk = "/pinctrl/mipi/mipim0-camera3-clk";
+		mipim0_camera4_clk = "/pinctrl/mipi/mipim0-camera4-clk";
+		mipim1_camera0_clk = "/pinctrl/mipi/mipim1-camera0-clk";
+		mipim1_camera1_clk = "/pinctrl/mipi/mipim1-camera1-clk";
+		mipim1_camera2_clk = "/pinctrl/mipi/mipim1-camera2-clk";
+		mipim1_camera3_clk = "/pinctrl/mipi/mipim1-camera3-clk";
+		mipim1_camera4_clk = "/pinctrl/mipi/mipim1-camera4-clk";
+		mipi_te0 = "/pinctrl/mipi/mipi-te0";
+		mipi_te1 = "/pinctrl/mipi/mipi-te1";
+		npu_pins = "/pinctrl/npu/npu-pins";
+		pcie20x1m0_pins = "/pinctrl/pcie20x1/pcie20x1m0-pins";
+		pcie20x1m1_pins = "/pinctrl/pcie20x1/pcie20x1m1-pins";
+		pcie20x1_2_button_rstn = "/pinctrl/pcie20x1/pcie20x1-2-button-rstn";
+		pcie30phy_pins = "/pinctrl/pcie30phy/pcie30phy-pins";
+		pcie30x1m0_pins = "/pinctrl/pcie30x1/pcie30x1m0-pins";
+		pcie30x1m1_pins = "/pinctrl/pcie30x1/pcie30x1m1-pins";
+		pcie30x1m2_pins = "/pinctrl/pcie30x1/pcie30x1m2-pins";
+		pcie30x1_0_button_rstn = "/pinctrl/pcie30x1/pcie30x1-0-button-rstn";
+		pcie30x1_1_button_rstn = "/pinctrl/pcie30x1/pcie30x1-1-button-rstn";
+		pcie30x2m0_pins = "/pinctrl/pcie30x2/pcie30x2m0-pins";
+		pcie30x2m1_pins = "/pinctrl/pcie30x2/pcie30x2m1-pins";
+		pcie30x2m2_pins = "/pinctrl/pcie30x2/pcie30x2m2-pins";
+		pcie30x2m3_pins = "/pinctrl/pcie30x2/pcie30x2m3-pins";
+		pcie30x2_button_rstn = "/pinctrl/pcie30x2/pcie30x2-button-rstn";
+		pcie30x4m0_pins = "/pinctrl/pcie30x4/pcie30x4m0-pins";
+		pcie30x4m1_pins = "/pinctrl/pcie30x4/pcie30x4m1-pins";
+		pcie30x4m2_pins = "/pinctrl/pcie30x4/pcie30x4m2-pins";
+		pcie30x4m3_pins = "/pinctrl/pcie30x4/pcie30x4m3-pins";
+		pcie30x4_button_rstn = "/pinctrl/pcie30x4/pcie30x4-button-rstn";
+		pdm0m0_clk = "/pinctrl/pdm0/pdm0m0-clk";
+		pdm0m0_clk1 = "/pinctrl/pdm0/pdm0m0-clk1";
+		pdm0m0_sdi0 = "/pinctrl/pdm0/pdm0m0-sdi0";
+		pdm0m0_sdi1 = "/pinctrl/pdm0/pdm0m0-sdi1";
+		pdm0m0_sdi2 = "/pinctrl/pdm0/pdm0m0-sdi2";
+		pdm0m0_sdi3 = "/pinctrl/pdm0/pdm0m0-sdi3";
+		pdm0m1_clk = "/pinctrl/pdm0/pdm0m1-clk";
+		pdm0m1_clk1 = "/pinctrl/pdm0/pdm0m1-clk1";
+		pdm0m1_sdi0 = "/pinctrl/pdm0/pdm0m1-sdi0";
+		pdm0m1_sdi1 = "/pinctrl/pdm0/pdm0m1-sdi1";
+		pdm0m1_sdi2 = "/pinctrl/pdm0/pdm0m1-sdi2";
+		pdm0m1_sdi3 = "/pinctrl/pdm0/pdm0m1-sdi3";
+		pdm1m0_clk = "/pinctrl/pdm1/pdm1m0-clk";
+		pdm1m0_clk1 = "/pinctrl/pdm1/pdm1m0-clk1";
+		pdm1m0_sdi0 = "/pinctrl/pdm1/pdm1m0-sdi0";
+		pdm1m0_sdi1 = "/pinctrl/pdm1/pdm1m0-sdi1";
+		pdm1m0_sdi2 = "/pinctrl/pdm1/pdm1m0-sdi2";
+		pdm1m0_sdi3 = "/pinctrl/pdm1/pdm1m0-sdi3";
+		pdm1m1_clk = "/pinctrl/pdm1/pdm1m1-clk";
+		pdm1m1_clk1 = "/pinctrl/pdm1/pdm1m1-clk1";
+		pdm1m1_sdi0 = "/pinctrl/pdm1/pdm1m1-sdi0";
+		pdm1m1_sdi1 = "/pinctrl/pdm1/pdm1m1-sdi1";
+		pdm1m1_sdi2 = "/pinctrl/pdm1/pdm1m1-sdi2";
+		pdm1m1_sdi3 = "/pinctrl/pdm1/pdm1m1-sdi3";
+		pmic_pins = "/pinctrl/pmic/pmic-pins";
+		pmu_pins = "/pinctrl/pmu/pmu-pins";
+		pwm0m0_pins = "/pinctrl/pwm0/pwm0m0-pins";
+		pwm0m1_pins = "/pinctrl/pwm0/pwm0m1-pins";
+		pwm0m2_pins = "/pinctrl/pwm0/pwm0m2-pins";
+		pwm1m0_pins = "/pinctrl/pwm1/pwm1m0-pins";
+		pwm1m1_pins = "/pinctrl/pwm1/pwm1m1-pins";
+		pwm1m2_pins = "/pinctrl/pwm1/pwm1m2-pins";
+		pwm2m0_pins = "/pinctrl/pwm2/pwm2m0-pins";
+		pwm2m1_pins = "/pinctrl/pwm2/pwm2m1-pins";
+		pwm3m0_pins = "/pinctrl/pwm3/pwm3m0-pins";
+		pwm3m1_pins = "/pinctrl/pwm3/pwm3m1-pins";
+		pwm3m2_pins = "/pinctrl/pwm3/pwm3m2-pins";
+		pwm3m3_pins = "/pinctrl/pwm3/pwm3m3-pins";
+		pwm4m0_pins = "/pinctrl/pwm4/pwm4m0-pins";
+		pwm5m0_pins = "/pinctrl/pwm5/pwm5m0-pins";
+		pwm5m1_pins = "/pinctrl/pwm5/pwm5m1-pins";
+		pwm6m0_pins = "/pinctrl/pwm6/pwm6m0-pins";
+		pwm6m1_pins = "/pinctrl/pwm6/pwm6m1-pins";
+		pwm7m0_pins = "/pinctrl/pwm7/pwm7m0-pins";
+		pwm7m1_pins = "/pinctrl/pwm7/pwm7m1-pins";
+		pwm7m2_pins = "/pinctrl/pwm7/pwm7m2-pins";
+		pwm8m0_pins = "/pinctrl/pwm8/pwm8m0-pins";
+		pwm8m1_pins = "/pinctrl/pwm8/pwm8m1-pins";
+		pwm8m2_pins = "/pinctrl/pwm8/pwm8m2-pins";
+		pwm9m0_pins = "/pinctrl/pwm9/pwm9m0-pins";
+		pwm9m1_pins = "/pinctrl/pwm9/pwm9m1-pins";
+		pwm9m2_pins = "/pinctrl/pwm9/pwm9m2-pins";
+		pwm10m0_pins = "/pinctrl/pwm10/pwm10m0-pins";
+		pwm10m1_pins = "/pinctrl/pwm10/pwm10m1-pins";
+		pwm10m2_pins = "/pinctrl/pwm10/pwm10m2-pins";
+		pwm11m0_pins = "/pinctrl/pwm11/pwm11m0-pins";
+		pwm11m1_pins = "/pinctrl/pwm11/pwm11m1-pins";
+		pwm11m2_pins = "/pinctrl/pwm11/pwm11m2-pins";
+		pwm11m3_pins = "/pinctrl/pwm11/pwm11m3-pins";
+		pwm12m0_pins = "/pinctrl/pwm12/pwm12m0-pins";
+		pwm12m1_pins = "/pinctrl/pwm12/pwm12m1-pins";
+		pwm13m0_pins = "/pinctrl/pwm13/pwm13m0-pins";
+		pwm13m1_pins = "/pinctrl/pwm13/pwm13m1-pins";
+		pwm13m2_pins = "/pinctrl/pwm13/pwm13m2-pins";
+		pwm14m0_pins = "/pinctrl/pwm14/pwm14m0-pins";
+		pwm14m1_pins = "/pinctrl/pwm14/pwm14m1-pins";
+		pwm14m2_pins = "/pinctrl/pwm14/pwm14m2-pins";
+		pwm15m0_pins = "/pinctrl/pwm15/pwm15m0-pins";
+		pwm15m1_pins = "/pinctrl/pwm15/pwm15m1-pins";
+		pwm15m2_pins = "/pinctrl/pwm15/pwm15m2-pins";
+		pwm15m3_pins = "/pinctrl/pwm15/pwm15m3-pins";
+		refclk_pins = "/pinctrl/refclk/refclk-pins";
+		sata_pins = "/pinctrl/sata/sata-pins";
+		sata_reset = "/pinctrl/sata/sata-reset";
+		sata0m0_pins = "/pinctrl/sata0/sata0m0-pins";
+		sata0m1_pins = "/pinctrl/sata0/sata0m1-pins";
+		sata1m0_pins = "/pinctrl/sata1/sata1m0-pins";
+		sata1m1_pins = "/pinctrl/sata1/sata1m1-pins";
+		sata2m0_pins = "/pinctrl/sata2/sata2m0-pins";
+		sata2m1_pins = "/pinctrl/sata2/sata2m1-pins";
+		sdiom1_pins = "/pinctrl/sdio/sdiom1-pins";
+		sdmmc_bus4 = "/pinctrl/sdmmc/sdmmc-bus4";
+		sdmmc_clk = "/pinctrl/sdmmc/sdmmc-clk";
+		sdmmc_cmd = "/pinctrl/sdmmc/sdmmc-cmd";
+		sdmmc_det = "/pinctrl/sdmmc/sdmmc-det";
+		sdmmc_pwren = "/pinctrl/sdmmc/sdmmc-pwren";
+		spdif0m0_tx = "/pinctrl/spdif0/spdif0m0-tx";
+		spdif0m1_tx = "/pinctrl/spdif0/spdif0m1-tx";
+		spdif1m0_tx = "/pinctrl/spdif1/spdif1m0-tx";
+		spdif1m1_tx = "/pinctrl/spdif1/spdif1m1-tx";
+		spdif1m2_tx = "/pinctrl/spdif1/spdif1m2-tx";
+		spi0m0_pins = "/pinctrl/spi0/spi0m0-pins";
+		spi0m0_cs0 = "/pinctrl/spi0/spi0m0-cs0";
+		spi0m0_cs1 = "/pinctrl/spi0/spi0m0-cs1";
+		spi0m1_pins = "/pinctrl/spi0/spi0m1-pins";
+		spi0m1_cs0 = "/pinctrl/spi0/spi0m1-cs0";
+		spi0m1_cs1 = "/pinctrl/spi0/spi0m1-cs1";
+		spi0m2_pins = "/pinctrl/spi0/spi0m2-pins";
+		spi0m2_cs0 = "/pinctrl/spi0/spi0m2-cs0";
+		spi0m2_cs1 = "/pinctrl/spi0/spi0m2-cs1";
+		spi0m3_pins = "/pinctrl/spi0/spi0m3-pins";
+		spi0m3_cs0 = "/pinctrl/spi0/spi0m3-cs0";
+		spi0m3_cs1 = "/pinctrl/spi0/spi0m3-cs1";
+		spi1m1_pins = "/pinctrl/spi1/spi1m1-pins";
+		spi1m1_cs0 = "/pinctrl/spi1/spi1m1-cs0";
+		spi1m1_cs1 = "/pinctrl/spi1/spi1m1-cs1";
+		spi1m2_pins = "/pinctrl/spi1/spi1m2-pins";
+		spi1m2_cs0 = "/pinctrl/spi1/spi1m2-cs0";
+		spi1m2_cs1 = "/pinctrl/spi1/spi1m2-cs1";
+		spi2m0_pins = "/pinctrl/spi2/spi2m0-pins";
+		spi2m0_cs0 = "/pinctrl/spi2/spi2m0-cs0";
+		spi2m0_cs1 = "/pinctrl/spi2/spi2m0-cs1";
+		spi2m1_pins = "/pinctrl/spi2/spi2m1-pins";
+		spi2m1_cs0 = "/pinctrl/spi2/spi2m1-cs0";
+		spi2m1_cs1 = "/pinctrl/spi2/spi2m1-cs1";
+		spi2m2_pins = "/pinctrl/spi2/spi2m2-pins";
+		spi2m2_cs0 = "/pinctrl/spi2/spi2m2-cs0";
+		spi2m2_cs1 = "/pinctrl/spi2/spi2m2-cs1";
+		spi3m1_pins = "/pinctrl/spi3/spi3m1-pins";
+		spi3m1_cs0 = "/pinctrl/spi3/spi3m1-cs0";
+		spi3m1_cs1 = "/pinctrl/spi3/spi3m1-cs1";
+		spi3m2_pins = "/pinctrl/spi3/spi3m2-pins";
+		spi3m2_cs0 = "/pinctrl/spi3/spi3m2-cs0";
+		spi3m2_cs1 = "/pinctrl/spi3/spi3m2-cs1";
+		spi3m3_pins = "/pinctrl/spi3/spi3m3-pins";
+		spi3m3_cs0 = "/pinctrl/spi3/spi3m3-cs0";
+		spi3m3_cs1 = "/pinctrl/spi3/spi3m3-cs1";
+		spi4m0_pins = "/pinctrl/spi4/spi4m0-pins";
+		spi4m0_cs0 = "/pinctrl/spi4/spi4m0-cs0";
+		spi4m0_cs1 = "/pinctrl/spi4/spi4m0-cs1";
+		spi4m1_pins = "/pinctrl/spi4/spi4m1-pins";
+		spi4m1_cs0 = "/pinctrl/spi4/spi4m1-cs0";
+		spi4m1_cs1 = "/pinctrl/spi4/spi4m1-cs1";
+		spi4m2_pins = "/pinctrl/spi4/spi4m2-pins";
+		spi4m2_cs0 = "/pinctrl/spi4/spi4m2-cs0";
+		tsadcm1_shut = "/pinctrl/tsadc/tsadcm1-shut";
+		tsadc_shut = "/pinctrl/tsadc/tsadc-shut";
+		tsadc_shut_org = "/pinctrl/tsadc/tsadc-shut-org";
+		uart0m0_xfer = "/pinctrl/uart0/uart0m0-xfer";
+		uart0m1_xfer = "/pinctrl/uart0/uart0m1-xfer";
+		uart0m2_xfer = "/pinctrl/uart0/uart0m2-xfer";
+		uart0_ctsn = "/pinctrl/uart0/uart0-ctsn";
+		uart0_rtsn = "/pinctrl/uart0/uart0-rtsn";
+		uart1m1_xfer = "/pinctrl/uart1/uart1m1-xfer";
+		uart1m1_ctsn = "/pinctrl/uart1/uart1m1-ctsn";
+		uart1m1_rtsn = "/pinctrl/uart1/uart1m1-rtsn";
+		uart1m2_xfer = "/pinctrl/uart1/uart1m2-xfer";
+		uart1m2_ctsn = "/pinctrl/uart1/uart1m2-ctsn";
+		uart1m2_rtsn = "/pinctrl/uart1/uart1m2-rtsn";
+		uart2m0_xfer = "/pinctrl/uart2/uart2m0-xfer";
+		uart2m1_xfer = "/pinctrl/uart2/uart2m1-xfer";
+		uart2m2_xfer = "/pinctrl/uart2/uart2m2-xfer";
+		uart2_ctsn = "/pinctrl/uart2/uart2-ctsn";
+		uart2_rtsn = "/pinctrl/uart2/uart2-rtsn";
+		uart3m0_xfer = "/pinctrl/uart3/uart3m0-xfer";
+		uart3m1_xfer = "/pinctrl/uart3/uart3m1-xfer";
+		uart3m2_xfer = "/pinctrl/uart3/uart3m2-xfer";
+		uart3_ctsn = "/pinctrl/uart3/uart3-ctsn";
+		uart3_rtsn = "/pinctrl/uart3/uart3-rtsn";
+		uart4m0_xfer = "/pinctrl/uart4/uart4m0-xfer";
+		uart4m1_xfer = "/pinctrl/uart4/uart4m1-xfer";
+		uart4m2_xfer = "/pinctrl/uart4/uart4m2-xfer";
+		uart4_ctsn = "/pinctrl/uart4/uart4-ctsn";
+		uart4_rtsn = "/pinctrl/uart4/uart4-rtsn";
+		uart5m0_xfer = "/pinctrl/uart5/uart5m0-xfer";
+		uart5m0_ctsn = "/pinctrl/uart5/uart5m0-ctsn";
+		uart5m0_rtsn = "/pinctrl/uart5/uart5m0-rtsn";
+		uart5m1_xfer = "/pinctrl/uart5/uart5m1-xfer";
+		uart5m1_ctsn = "/pinctrl/uart5/uart5m1-ctsn";
+		uart5m1_rtsn = "/pinctrl/uart5/uart5m1-rtsn";
+		uart5m2_xfer = "/pinctrl/uart5/uart5m2-xfer";
+		uart6m1_xfer = "/pinctrl/uart6/uart6m1-xfer";
+		uart6m1_ctsn = "/pinctrl/uart6/uart6m1-ctsn";
+		uart6m1_rtsn = "/pinctrl/uart6/uart6m1-rtsn";
+		uart6m2_xfer = "/pinctrl/uart6/uart6m2-xfer";
+		uart7m1_xfer = "/pinctrl/uart7/uart7m1-xfer";
+		uart7m1_ctsn = "/pinctrl/uart7/uart7m1-ctsn";
+		uart7m1_rtsn = "/pinctrl/uart7/uart7m1-rtsn";
+		uart7m2_xfer = "/pinctrl/uart7/uart7m2-xfer";
+		uart8m0_xfer = "/pinctrl/uart8/uart8m0-xfer";
+		uart8m0_ctsn = "/pinctrl/uart8/uart8m0-ctsn";
+		uart8m0_rtsn = "/pinctrl/uart8/uart8m0-rtsn";
+		uart8m1_xfer = "/pinctrl/uart8/uart8m1-xfer";
+		uart8m1_ctsn = "/pinctrl/uart8/uart8m1-ctsn";
+		uart8m1_rtsn = "/pinctrl/uart8/uart8m1-rtsn";
+		uart8_xfer = "/pinctrl/uart8/uart8-xfer";
+		uart9m1_xfer = "/pinctrl/uart9/uart9m1-xfer";
+		uart9m1_ctsn = "/pinctrl/uart9/uart9m1-ctsn";
+		uart9m1_rtsn = "/pinctrl/uart9/uart9m1-rtsn";
+		uart9m2_xfer = "/pinctrl/uart9/uart9m2-xfer";
+		uart9m2_ctsn = "/pinctrl/uart9/uart9m2-ctsn";
+		uart9m2_rtsn = "/pinctrl/uart9/uart9m2-rtsn";
+		vop_pins = "/pinctrl/vop/vop-pins";
+		bt656_pins = "/pinctrl/bt656/bt656-pins";
+		tsadc_gpio_func = "/pinctrl/gpio-func/tsadc-gpio-func";
+		leds_gpio = "/pinctrl/gpio-func/leds-gpio";
+		hp_det = "/pinctrl/headphone/hp-det";
+		hym8563_int = "/pinctrl/hym8563/hym8563-int";
+		lcd0_rst_gpio = "/pinctrl/lcd/lcd0-rst-gpio";
+		lcd1_rst_gpio = "/pinctrl/lcd/lcd1-rst-gpio";
+		usbc0_int = "/pinctrl/usb-typec/usbc0-int";
+		typec5v_pwren = "/pinctrl/usb-typec/typec5v-pwren";
+		uart9_gpios = "/pinctrl/wireless-bluetooth/uart9-gpios";
+		bt_gpio = "/pinctrl/wireless-bluetooth/bt-gpio";
+		wifi_host_wake_irq = "/pinctrl/wireless-wlan/wifi-host-wake-irq";
+		wifi_poweren_gpio = "/pinctrl/wireless-wlan/wifi-poweren-gpio";
+		adc_keys = "/adc-keys";
+		backlight = "/backlight";
+		backlight_1 = "/backlight_1";
+		dp0_sound = "/dp0-sound";
+		hdmi0_sound = "/hdmi0-sound";
+		spdif_tx1_dc = "/spdif-tx1-dc";
+		spdif_tx1_sound = "/spdif-tx1-sound";
+		vcc12v_dcin = "/vcc12v-dcin";
+		vcc5v0_sys = "/vcc5v0-sys";
+		vcc5v0_usbdcin = "/vcc5v0-usbdcin";
+		vcc5v0_usb = "/vcc5v0-usb";
+		combophy_avdd0v85 = "/combophy-avdd0v85";
+		combophy_avdd1v8 = "/combophy-avdd1v8";
+		es8388_sound = "/es8388-sound";
+		wireless_bluetooth = "/wireless-bluetooth";
+		wireless_wlan = "/wireless-wlan";
+		vbus5v0_typec = "/vbus5v0-typec";
+		cspmu = "/cspmu@fd10c000";
+		debug = "/debug@fd104000";
+		fiq_debugger = "/fiq-debugger";
+		drm_logo = "/reserved-memory/drm-logo@00000000";
+		drm_cubic_lut = "/reserved-memory/drm-cubic-lut@00000000";
+		ramoops = "/reserved-memory/ramoops@110000";
+		vcc_3v3_sd_s0 = "/vcc-3v3-sd-s0";
+		vcc_1v1_nldo_s3 = "/vcc-1v1-nldo-s3";
+		vcc3v3_pcie2x1l2 = "/vcc3v3-pcie2x1l2";
+		leds = "/gpio-leds";
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/roc-rk3588s-pc.dts b/arch/arm64/boot/dts/rockchip/roc-rk3588s-pc.dts
new file mode 100644
index 0000000000000000000000000000000000000000..24e72dc6eb025a243ebecc7caada23a4c57d2044
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/roc-rk3588s-pc.dts
@@ -0,0 +1,7370 @@
+/dts-v1/;
+
+/ {
+	compatible = "rockchip,roc-rk3588s-pc\0rockchip,rk3588";
+	interrupt-parent = <0x01>;
+	#address-cells = <0x02>;
+	#size-cells = <0x02>;
+	model = "Firefly ROC-RK3588S-PC HDMI(Linux)";
+
+	aliases {
+		csi2dcphy0 = "/csi2-dcphy0";
+		csi2dcphy1 = "/csi2-dcphy1";
+		csi2dphy0 = "/csi2-dphy0";
+		csi2dphy1 = "/csi2-dphy1";
+		csi2dphy2 = "/csi2-dphy2";
+		dsi0 = "/dsi@fde20000";
+		dsi1 = "/dsi@fde30000";
+		ethernet0 = "/ethernet@fe1b0000";
+		ethernet1 = "/ethernet@fe1c0000";
+		gpio0 = "/pinctrl/gpio@fd8a0000";
+		gpio1 = "/pinctrl/gpio@fec20000";
+		gpio2 = "/pinctrl/gpio@fec30000";
+		gpio3 = "/pinctrl/gpio@fec40000";
+		gpio4 = "/pinctrl/gpio@fec50000";
+		i2c0 = "/i2c@fd880000";
+		i2c1 = "/i2c@fea90000";
+		i2c2 = "/i2c@feaa0000";
+		i2c3 = "/i2c@feab0000";
+		i2c4 = "/i2c@feac0000";
+		i2c5 = "/i2c@fead0000";
+		i2c6 = "/i2c@fec80000";
+		i2c7 = "/i2c@fec90000";
+		i2c8 = "/i2c@feca0000";
+		rkcif_mipi_lvds0 = "/rkcif-mipi-lvds";
+		rkcif_mipi_lvds1 = "/rkcif-mipi-lvds1";
+		rkcif_mipi_lvds2 = "/rkcif-mipi-lvds2";
+		rkcif_mipi_lvds3 = "/rkcif-mipi-lvds3";
+		rkvenc0 = "/rkvenc-core@fdbd0000";
+		rkvenc1 = "/rkvenc-core@fdbe0000";
+		jpege0 = "/jpege-core@fdba0000";
+		jpege1 = "/jpege-core@fdba4000";
+		jpege2 = "/jpege-core@fdba8000";
+		jpege3 = "/jpege-core@fdbac000";
+		serial0 = "/serial@fd890000";
+		serial1 = "/serial@feb40000";
+		serial2 = "/serial@feb50000";
+		serial3 = "/serial@feb60000";
+		serial4 = "/serial@feb70000";
+		serial5 = "/serial@feb80000";
+		serial6 = "/serial@feb90000";
+		serial7 = "/serial@feba0000";
+		serial8 = "/serial@febb0000";
+		serial9 = "/serial@febc0000";
+		spi0 = "/spi@feb00000";
+		spi1 = "/spi@feb10000";
+		spi2 = "/spi@feb20000";
+		spi3 = "/spi@feb30000";
+		spi4 = "/spi@fecb0000";
+		spi5 = "/spi@fe2b0000";
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+
+		spll {
+			compatible = "fixed-clock";
+			#clock-cells = <0x00>;
+			clock-frequency = <0x29d7ab80>;
+			clock-output-names = "spll";
+		};
+
+		xin32k {
+			compatible = "fixed-clock";
+			#clock-cells = <0x00>;
+			clock-frequency = <0x8000>;
+			clock-output-names = "xin32k";
+		};
+
+		xin24m {
+			compatible = "fixed-clock";
+			#clock-cells = <0x00>;
+			clock-frequency = <0x16e3600>;
+			clock-output-names = "xin24m";
+		};
+
+		hclk_vo1@fd7c08ec {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08ec 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x264>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x05>;
+		};
+
+		aclk_vdpu_low_pre@fd7c08b0 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08b0 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1bc>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		hclk_vo0@fd7c08dc {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08dc 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x26d>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x04>;
+		};
+
+		hclk_usb@fd7c08a8 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08a8 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x264>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		hclk_nvm@fd7c087c {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c087c 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x141>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+			phandle = <0x03>;
+		};
+
+		aclk_usb@fd7c08a8 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08a8 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x263>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		hclk_isp1_pre@fd7c0868 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c0868 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1e1>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		aclk_isp1_pre@fd7c0868 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c0868 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1e0>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		aclk_rkvdec0_pre@fd7c08a0 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08a0 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1bc>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		hclk_rkvdec0_pre@fd7c08a0 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08a0 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1be>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		aclk_rkvdec1_pre@fd7c08a4 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08a4 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1bc>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		hclk_rkvdec1_pre@fd7c08a4 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08a4 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1be>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		aclk_jpeg_decoder_pre@fd7c08b0 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08b0 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1bc>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		aclk_rkvenc1_pre@fd7c08c0 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08c0 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1c5>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		hclk_rkvenc1_pre@fd7c08c0 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08c0 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1c4>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		aclk_hdcp0_pre@fd7c08dc {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08dc 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x26c>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		aclk_hdcp1_pre@fd7c08ec {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08ec 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x263>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		pclk_av1_pre@fd7c0910 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c0910 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1be>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		aclk_av1_pre@fd7c0910 {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c0910 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x02 0x1bc>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		hclk_sdio_pre@fd7c092c {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c092c 0x00 0x10>;
+			clock-names = "link";
+			clocks = <0x03>;
+			#power-domain-cells = <0x01>;
+			#clock-cells = <0x00>;
+		};
+
+		pclk_vo0_grf@fd7c08dc {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08dc 0x00 0x04>;
+			clocks = <0x04>;
+			clock-names = "link";
+			#clock-cells = <0x00>;
+			phandle = <0x59>;
+		};
+
+		pclk_vo1_grf@fd7c08ec {
+			compatible = "rockchip,rk3588-clock-gate-link";
+			reg = <0x00 0xfd7c08ec 0x00 0x04>;
+			clocks = <0x05>;
+			clock-names = "link";
+			#clock-cells = <0x00>;
+			phandle = <0x5a>;
+		};
+	};
+
+	cpus {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		cpu-map {
+
+			cluster0 {
+
+				core0 {
+					cpu = <0x06>;
+				};
+
+				core1 {
+					cpu = <0x07>;
+				};
+
+				core2 {
+					cpu = <0x08>;
+				};
+
+				core3 {
+					cpu = <0x09>;
+				};
+			};
+
+			cluster1 {
+
+				core0 {
+					cpu = <0x0a>;
+				};
+
+				core1 {
+					cpu = <0x0b>;
+				};
+			};
+
+			cluster2 {
+
+				core0 {
+					cpu = <0x0c>;
+				};
+
+				core1 {
+					cpu = <0x0d>;
+				};
+			};
+		};
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x00>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x212>;
+			clocks = <0x0e 0x00>;
+			operating-points-v2 = <0x0f>;
+			cpu-idle-states = <0x10>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x80>;
+			next-level-cache = <0x11>;
+			#cooling-cells = <0x02>;
+			dynamic-power-coefficient = <0x64>;
+			cpu-supply = <0x12>;
+			mem-supply = <0x12>;
+			phandle = <0x06>;
+		};
+
+		cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x212>;
+			clocks = <0x0e 0x00>;
+			operating-points-v2 = <0x0f>;
+			cpu-idle-states = <0x10>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x80>;
+			next-level-cache = <0x13>;
+			phandle = <0x07>;
+		};
+
+		cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x212>;
+			clocks = <0x0e 0x00>;
+			operating-points-v2 = <0x0f>;
+			cpu-idle-states = <0x10>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x80>;
+			next-level-cache = <0x14>;
+			phandle = <0x08>;
+		};
+
+		cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x212>;
+			clocks = <0x0e 0x00>;
+			operating-points-v2 = <0x0f>;
+			cpu-idle-states = <0x10>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x80>;
+			next-level-cache = <0x15>;
+			phandle = <0x09>;
+		};
+
+		cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x400>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x400>;
+			clocks = <0x0e 0x02>;
+			operating-points-v2 = <0x16>;
+			cpu-idle-states = <0x10>;
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x100>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x100>;
+			next-level-cache = <0x17>;
+			#cooling-cells = <0x02>;
+			dynamic-power-coefficient = <0x12c>;
+			cpu-supply = <0x18>;
+			mem-supply = <0x18>;
+			phandle = <0x0a>;
+		};
+
+		cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x500>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x400>;
+			clocks = <0x0e 0x02>;
+			operating-points-v2 = <0x16>;
+			cpu-idle-states = <0x10>;
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x100>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x100>;
+			next-level-cache = <0x19>;
+			phandle = <0x0b>;
+		};
+
+		cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x600>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x400>;
+			clocks = <0x0e 0x03>;
+			operating-points-v2 = <0x1a>;
+			cpu-idle-states = <0x10>;
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x100>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x100>;
+			next-level-cache = <0x1b>;
+			#cooling-cells = <0x02>;
+			dynamic-power-coefficient = <0x12c>;
+			cpu-supply = <0x1c>;
+			mem-supply = <0x1c>;
+			phandle = <0x0c>;
+		};
+
+		cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x700>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <0x400>;
+			clocks = <0x0e 0x03>;
+			operating-points-v2 = <0x1a>;
+			cpu-idle-states = <0x10>;
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x100>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x100>;
+			next-level-cache = <0x1d>;
+			phandle = <0x0d>;
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			cpu-sleep {
+				compatible = "arm,idle-state";
+				local-timer-stop;
+				arm,psci-suspend-param = <0x10000>;
+				entry-latency-us = <0x64>;
+				exit-latency-us = <0x78>;
+				min-residency-us = <0x3e8>;
+				phandle = <0x10>;
+			};
+		};
+
+		l2-cache-l0 {
+			compatible = "cache";
+			cache-size = <0x20000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x200>;
+			next-level-cache = <0x1e>;
+			phandle = <0x11>;
+		};
+
+		l2-cache-l1 {
+			compatible = "cache";
+			cache-size = <0x20000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x200>;
+			next-level-cache = <0x1e>;
+			phandle = <0x13>;
+		};
+
+		l2-cache-l2 {
+			compatible = "cache";
+			cache-size = <0x20000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x200>;
+			next-level-cache = <0x1e>;
+			phandle = <0x14>;
+		};
+
+		l2-cache-l3 {
+			compatible = "cache";
+			cache-size = <0x20000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x200>;
+			next-level-cache = <0x1e>;
+			phandle = <0x15>;
+		};
+
+		l2-cache-b0 {
+			compatible = "cache";
+			cache-size = <0x80000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x400>;
+			next-level-cache = <0x1e>;
+			phandle = <0x17>;
+		};
+
+		l2-cache-b1 {
+			compatible = "cache";
+			cache-size = <0x80000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x400>;
+			next-level-cache = <0x1e>;
+			phandle = <0x19>;
+		};
+
+		l2-cache-b2 {
+			compatible = "cache";
+			cache-size = <0x80000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x400>;
+			next-level-cache = <0x1e>;
+			phandle = <0x1b>;
+		};
+
+		l2-cache-b3 {
+			compatible = "cache";
+			cache-size = <0x80000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x400>;
+			next-level-cache = <0x1e>;
+			phandle = <0x1d>;
+		};
+
+		l3-cache {
+			compatible = "cache";
+			cache-size = <0x300000>;
+			cache-line-size = <0x40>;
+			cache-sets = <0x1000>;
+			phandle = <0x1e>;
+		};
+	};
+
+	cluster0-opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+		nvmem-cells = <0x1f>;
+		nvmem-cell-names = "leakage";
+		rockchip,supported-hw;
+		rockchip,opp-shared-dsu;
+		rockchip,pvtm-voltage-sel = <0x00 0x582 0x00 0x583 0x59a 0x01 0x59b 0x5b2 0x02 0x5b3 0x5ca 0x03 0x5cb 0x5e2 0x04 0x5e3 0x5fa 0x05 0x5fb 0x270f 0x06>;
+		rockchip,pvtm-pvtpll;
+		rockchip,pvtm-offset = <0x64>;
+		rockchip,pvtm-sample-time = <0x44c>;
+		rockchip,pvtm-freq = <0x159b40>;
+		rockchip,pvtm-volt = <0xb71b0>;
+		rockchip,pvtm-ref-temp = <0x19>;
+		rockchip,pvtm-temp-prop = <0xf4 0xf4>;
+		rockchip,pvtm-thermal-zone = "soc-thermal";
+		rockchip,grf = <0x20>;
+		rockchip,reboot-freq = <0x159b40>;
+		rockchip,temp-hysteresis = <0x1388>;
+		rockchip,low-temp = <0x2710>;
+		rockchip,low-temp-min-volt = <0xb71b0>;
+		rockchip,high-temp = <0x14c08>;
+		rockchip,high-temp-max-freq = <0x188940>;
+		phandle = <0x0f>;
+
+		opp-408000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x18519600>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-600000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x23c34600>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-816000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x30a32c00>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1008000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x3c14dc00>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1200000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x47868c00>;
+			opp-microvolt = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>;
+			opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>;
+			opp-microvolt-L2 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>;
+			opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>;
+			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
+			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
+			opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1416000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x54667200>;
+			opp-microvolt = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>;
+			opp-microvolt-L1 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
+			opp-microvolt-L2 = <0xb40dc 0xb40dc 0xe7ef0 0xb40dc 0xb40dc 0xe7ef0>;
+			opp-microvolt-L3 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>;
+			opp-microvolt-L4 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>;
+			opp-microvolt-L5 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>;
+			opp-microvolt-L6 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>;
+			clock-latency-ns = <0x9c40>;
+			opp-suspend;
+		};
+
+		opp-1608000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x5fd82200>;
+			opp-microvolt = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>;
+			opp-microvolt-L1 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>;
+			opp-microvolt-L2 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>;
+			opp-microvolt-L3 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>;
+			opp-microvolt-L4 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>;
+			opp-microvolt-L5 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>;
+			opp-microvolt-L6 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1800000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x6b49d200>;
+			opp-microvolt = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>;
+			opp-microvolt-L1 = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>;
+			opp-microvolt-L2 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>;
+			opp-microvolt-L3 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>;
+			opp-microvolt-L4 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>;
+			opp-microvolt-L5 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>;
+			opp-microvolt-L6 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>;
+			clock-latency-ns = <0x9c40>;
+		};
+	};
+
+	cluster1-opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+		nvmem-cells = <0x21>;
+		nvmem-cell-names = "leakage";
+		rockchip,supported-hw;
+		rockchip,pvtm-voltage-sel = <0x00 0x63b 0x00 0x63c 0x64f 0x01 0x650 0x668 0x02 0x669 0x68b 0x03 0x68c 0x6ae 0x04 0x6af 0x6cf 0x05 0x6d0 0x6f0 0x06 0x6f1 0x270f 0x07>;
+		rockchip,pvtm-pvtpll;
+		rockchip,pvtm-offset = <0x18>;
+		rockchip,pvtm-sample-time = <0x44c>;
+		rockchip,pvtm-freq = <0x188940>;
+		rockchip,pvtm-volt = <0xb71b0>;
+		rockchip,pvtm-ref-temp = <0x19>;
+		rockchip,pvtm-temp-prop = <0x10e 0x10e>;
+		rockchip,pvtm-thermal-zone = "soc-thermal";
+		rockchip,pvtm-low-len-sel = <0x03>;
+		rockchip,grf = <0x22>;
+		volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>;
+		low-volt-mem-read-margin = <0x04>;
+		intermediate-threshold-freq = <0xf6180>;
+		rockchip,idle-threshold-freq = <0x21b100>;
+		rockchip,reboot-freq = <0x1b7740>;
+		rockchip,temp-hysteresis = <0x1388>;
+		rockchip,low-temp = <0x2710>;
+		rockchip,low-temp-min-volt = <0xb71b0>;
+		rockchip,high-temp = <0x14c08>;
+		rockchip,high-temp-max-freq = <0x21b100>;
+		phandle = <0x16>;
+
+		opp-408000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x18519600>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+			opp-suspend;
+		};
+
+		opp-600000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x23c34600>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-816000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x30a32c00>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1008000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x3c14dc00>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1200000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x47868c00>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1416000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x54667200>;
+			opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>;
+			opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>;
+			opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
+			opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
+			opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>;
+			opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1608000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x5fd82200>;
+			opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>;
+			opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>;
+			opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>;
+			opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>;
+			opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>;
+			opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
+			opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1800000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x6b49d200>;
+			opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>;
+			opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>;
+			opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>;
+			opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>;
+			opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>;
+			opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>;
+			opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>;
+			opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2016000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x7829b800>;
+			opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>;
+			opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>;
+			opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>;
+			opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>;
+			opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>;
+			opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>;
+			opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>;
+			opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2208000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x839b6800>;
+			opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>;
+			opp-microvolt-L1 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>;
+			opp-microvolt-L2 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>;
+			opp-microvolt-L3 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>;
+			opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>;
+			opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>;
+			opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>;
+			opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2256000000 {
+			opp-supported-hw = <0xff 0x13>;
+			opp-hz = <0x00 0x8677d400>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2304000000 {
+			opp-supported-hw = <0xff 0x24>;
+			opp-hz = <0x00 0x89544000>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2352000000 {
+			opp-supported-hw = <0xff 0x48>;
+			opp-hz = <0x00 0x8c30ac00>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2400000000 {
+			opp-supported-hw = <0xff 0x80>;
+			opp-hz = <0x00 0x8f0d1800>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+	};
+
+	cluster2-opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+		nvmem-cells = <0x23>;
+		nvmem-cell-names = "leakage";
+		rockchip,supported-hw;
+		rockchip,pvtm-voltage-sel = <0x00 0x63b 0x00 0x63c 0x64f 0x01 0x650 0x668 0x02 0x669 0x68b 0x03 0x68c 0x6ae 0x04 0x6af 0x6cf 0x05 0x6d0 0x6f0 0x06 0x6f1 0x270f 0x07>;
+		rockchip,pvtm-pvtpll;
+		rockchip,pvtm-offset = <0x18>;
+		rockchip,pvtm-sample-time = <0x44c>;
+		rockchip,pvtm-freq = <0x188940>;
+		rockchip,pvtm-volt = <0xb71b0>;
+		rockchip,pvtm-ref-temp = <0x19>;
+		rockchip,pvtm-temp-prop = <0x10e 0x10e>;
+		rockchip,pvtm-thermal-zone = "soc-thermal";
+		rockchip,pvtm-low-len-sel = <0x03>;
+		rockchip,grf = <0x24>;
+		volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>;
+		low-volt-mem-read-margin = <0x04>;
+		intermediate-threshold-freq = <0xf6180>;
+		rockchip,idle-threshold-freq = <0x21b100>;
+		rockchip,reboot-freq = <0x1b7740>;
+		rockchip,temp-hysteresis = <0x1388>;
+		rockchip,low-temp = <0x2710>;
+		rockchip,low-temp-min-volt = <0xb71b0>;
+		rockchip,high-temp = <0x14c08>;
+		rockchip,high-temp-max-freq = <0x21b100>;
+		phandle = <0x1a>;
+
+		opp-408000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x18519600>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+			opp-suspend;
+		};
+
+		opp-600000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x23c34600>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-816000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x30a32c00>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1008000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x3c14dc00>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1200000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x47868c00>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1416000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x54667200>;
+			opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>;
+			opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>;
+			opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
+			opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
+			opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>;
+			opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1608000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x5fd82200>;
+			opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>;
+			opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>;
+			opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>;
+			opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>;
+			opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>;
+			opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
+			opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1800000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x6b49d200>;
+			opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>;
+			opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>;
+			opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>;
+			opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>;
+			opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>;
+			opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>;
+			opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>;
+			opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2016000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x7829b800>;
+			opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>;
+			opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>;
+			opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>;
+			opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>;
+			opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>;
+			opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>;
+			opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>;
+			opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2208000000 {
+			opp-supported-hw = <0xff 0xffff>;
+			opp-hz = <0x00 0x839b6800>;
+			opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>;
+			opp-microvolt-L3 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>;
+			opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>;
+			opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>;
+			opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>;
+			opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2256000000 {
+			opp-supported-hw = <0xff 0x13>;
+			opp-hz = <0x00 0x8677d400>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2304000000 {
+			opp-supported-hw = <0xff 0x24>;
+			opp-hz = <0x00 0x89544000>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2352000000 {
+			opp-supported-hw = <0xff 0x48>;
+			opp-hz = <0x00 0x8c30ac00>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-2400000000 {
+			opp-supported-hw = <0xff 0x80>;
+			opp-hz = <0x00 0x8f0d1800>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
+			clock-latency-ns = <0x9c40>;
+		};
+	};
+
+	arm-pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <0x01 0x07 0x08>;
+		interrupt-affinity = <0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d>;
+	};
+
+	cpuinfo {
+		compatible = "rockchip,cpuinfo";
+		nvmem-cells = <0x25 0x26 0x27>;
+		nvmem-cell-names = "id\0cpu-version\0cpu-code";
+	};
+
+	csi2-dcphy0 {
+		compatible = "rockchip,rk3588-csi2-dcphy";
+		phys = <0x28>;
+		phy-names = "dcphy";
+		status = "disabled";
+	};
+
+	csi2-dcphy1 {
+		compatible = "rockchip,rk3588-csi2-dcphy";
+		phys = <0x29>;
+		phy-names = "dcphy";
+		status = "disabled";
+	};
+
+	csi2-dphy0 {
+		compatible = "rockchip,rk3568-csi2-dphy";
+		rockchip,hw = <0x2a>;
+		status = "okay";
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0x2b>;
+					data-lanes = <0x01 0x02 0x03 0x04>;
+					phandle = <0x155>;
+				};
+			};
+
+			port@1 {
+				reg = <0x01>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0x2c>;
+					phandle = <0xb4>;
+				};
+			};
+		};
+	};
+
+	csi2-dphy1 {
+		compatible = "rockchip,rk3568-csi2-dphy";
+		rockchip,hw = <0x2a>;
+		status = "disabled";
+	};
+
+	csi2-dphy2 {
+		compatible = "rockchip,rk3568-csi2-dphy";
+		rockchip,hw = <0x2a>;
+		status = "disabled";
+	};
+
+	display-subsystem {
+		compatible = "rockchip,display-subsystem";
+		ports = <0x2d>;
+		memory-region = <0x2e>;
+		memory-region-names = "drm-logo";
+
+		route {
+
+			route-dp0 {
+				status = "disabled";
+				logo,uboot = "logo.bmp";
+				logo,kernel = "logo_kernel.bmp";
+				logo,mode = "center";
+				charge_logo,mode = "center";
+				connect = <0x2f>;
+			};
+
+			route-dsi0 {
+				status = "disabled";
+				logo,uboot = "logo.bmp";
+				logo,kernel = "logo_kernel.bmp";
+				logo,mode = "center";
+				charge_logo,mode = "center";
+				connect = <0x30>;
+			};
+
+			route-dsi1 {
+				status = "disabled";
+				logo,uboot = "logo.bmp";
+				logo,kernel = "logo_kernel.bmp";
+				logo,mode = "center";
+				charge_logo,mode = "center";
+				connect = <0x31>;
+			};
+
+			route-edp0 {
+				status = "disabled";
+				logo,uboot = "logo.bmp";
+				logo,kernel = "logo_kernel.bmp";
+				logo,mode = "center";
+				charge_logo,mode = "center";
+				connect = <0x32>;
+			};
+
+			route-edp1 {
+				status = "disabled";
+				logo,uboot = "logo.bmp";
+				logo,kernel = "logo_kernel.bmp";
+				logo,mode = "center";
+				charge_logo,mode = "center";
+			};
+
+			route-hdmi0 {
+				status = "okay";
+				logo,uboot = "logo.bmp";
+				logo,kernel = "logo_kernel.bmp";
+				logo,mode = "center";
+				charge_logo,mode = "center";
+				connect = <0x33>;
+			};
+
+			route-rgb {
+				status = "disabled";
+				logo,uboot = "logo.bmp";
+				logo,kernel = "logo_kernel.bmp";
+				logo,mode = "center";
+				charge_logo,mode = "center";
+				connect = <0x34>;
+			};
+		};
+	};
+
+	dmc {
+		compatible = "rockchip,rk3588-dmc";
+		interrupts = <0x00 0x49 0x04>;
+		interrupt-names = "complete";
+		devfreq-events = <0x35>;
+		clocks = <0x0e 0x04>;
+		clock-names = "dmc_clk";
+		operating-points-v2 = <0x36>;
+		upthreshold = <0x28>;
+		downdifferential = <0x14>;
+		system-status-level = <0x01 0x04 0x08 0x08 0x02 0x01 0x10 0x04 0x10000 0x04 0x1000 0x08 0x4000 0x08 0x2000 0x08 0xc00 0x08>;
+		auto-freq-en = <0x01>;
+		status = "okay";
+		center-supply = <0x37>;
+	};
+
+	dmc-opp-table {
+		compatible = "operating-points-v2";
+		nvmem-cells = <0x38>;
+		nvmem-cell-names = "leakage";
+		phandle = <0x36>;
+
+		opp-528000000 {
+			opp-hz = <0x00 0x1f78a400>;
+			opp-microvolt = <0xa4cb8>;
+		};
+
+		opp-1068000000 {
+			opp-hz = <0x00 0x3fa86300>;
+			opp-microvolt = <0xb1008>;
+		};
+
+		opp-1560000000 {
+			opp-hz = <0x00 0x5cfbb600>;
+			opp-microvolt = <0xc3500>;
+		};
+
+		opp-2750000000 {
+			opp-hz = <0x00 0xa3e9ab80>;
+			opp-microvolt = <0xcf850>;
+		};
+	};
+
+	firmware {
+
+		scmi {
+			compatible = "arm,scmi-smc";
+			shmem = <0x39>;
+			arm,smc-id = <0x82000010>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <0x01>;
+				assigned-clocks = <0x0e 0x00 0x0e 0x02 0x0e 0x03>;
+				assigned-clock-rates = <0x30a32c00 0x30a32c00 0x30a32c00>;
+				phandle = <0x0e>;
+			};
+
+			protocol@16 {
+				reg = <0x16>;
+				#reset-cells = <0x01>;
+				phandle = <0xf4>;
+			};
+		};
+
+		sdei {
+			compatible = "arm,sdei-1.0";
+			method = "smc";
+		};
+
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+
+	jpege-ccu {
+		compatible = "rockchip,vpu-encoder-v2-ccu";
+		status = "okay";
+		phandle = <0xa0>;
+	};
+
+	mpp-srv {
+		compatible = "rockchip,mpp-service";
+		rockchip,taskqueue-count = <0x0c>;
+		status = "okay";
+		phandle = <0x9b>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	rkcif-dvp {
+		compatible = "rockchip,rkcif-dvp";
+		rockchip,hw = <0x3a>;
+		iommus = <0x3b>;
+		status = "disabled";
+		phandle = <0x3c>;
+	};
+
+	rkcif-dvp-sditf {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x3c>;
+		status = "disabled";
+	};
+
+	rkcif-mipi-lvds {
+		compatible = "rockchip,rkcif-mipi-lvds";
+		rockchip,hw = <0x3a>;
+		iommus = <0x3b>;
+		status = "disabled";
+		phandle = <0x3d>;
+	};
+
+	rkcif-mipi-lvds-sditf {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x3d>;
+		status = "disabled";
+	};
+
+	rkcif-mipi-lvds-sditf-vir1 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x3d>;
+		status = "disabled";
+	};
+
+	rkcif-mipi-lvds-sditf-vir2 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x3d>;
+		status = "disabled";
+	};
+
+	rkcif-mipi-lvds-sditf-vir3 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x3d>;
+		status = "disabled";
+	};
+
+	rkcif-mipi-lvds1 {
+		compatible = "rockchip,rkcif-mipi-lvds";
+		rockchip,hw = <0x3a>;
+		iommus = <0x3b>;
+		status = "disabled";
+		phandle = <0x3e>;
+	};
+
+	rkcif-mipi-lvds1-sditf {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x3e>;
+		status = "disabled";
+	};
+
+	rkcif-mipi-lvds1-sditf-vir1 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x3e>;
+		status = "disabled";
+	};
+
+	rkcif-mipi-lvds1-sditf-vir2 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x3e>;
+		status = "disabled";
+	};
+
+	rkcif-mipi-lvds1-sditf-vir3 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x3e>;
+		status = "disabled";
+	};
+
+	rkcif-mipi-lvds2 {
+		compatible = "rockchip,rkcif-mipi-lvds";
+		rockchip,hw = <0x3a>;
+		iommus = <0x3b>;
+		status = "okay";
+		phandle = <0x40>;
+
+		port {
+
+			endpoint {
+				remote-endpoint = <0x3f>;
+				phandle = <0xb5>;
+			};
+		};
+	};
+
+	rkcif-mipi-lvds2-sditf {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x40>;
+		status = "disabled";
+
+		port {
+
+			endpoint {
+				remote-endpoint = <0x41>;
+				phandle = <0x44>;
+			};
+		};
+	};
+
+	rkcif-mipi-lvds2-sditf-vir1 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x40>;
+		status = "disabled";
+	};
+
+	rkcif-mipi-lvds2-sditf-vir2 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x40>;
+		status = "disabled";
+	};
+
+	rkcif-mipi-lvds2-sditf-vir3 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x40>;
+		status = "disabled";
+	};
+
+	rkcif-mipi-lvds3 {
+		compatible = "rockchip,rkcif-mipi-lvds";
+		rockchip,hw = <0x3a>;
+		iommus = <0x3b>;
+		status = "disabled";
+		phandle = <0x42>;
+	};
+
+	rkcif-mipi-lvds3-sditf {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x42>;
+		status = "disabled";
+	};
+
+	rkcif-mipi-lvds3-sditf-vir1 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x42>;
+		status = "disabled";
+	};
+
+	rkcif-mipi-lvds3-sditf-vir2 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x42>;
+		status = "disabled";
+	};
+
+	rkcif-mipi-lvds3-sditf-vir3 {
+		compatible = "rockchip,rkcif-sditf";
+		rockchip,cif = <0x42>;
+		status = "disabled";
+	};
+
+	rkisp0-vir0 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <0x43>;
+		status = "disabled";
+
+		port {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			endpoint@0 {
+				reg = <0x00>;
+				remote-endpoint = <0x44>;
+				phandle = <0x41>;
+			};
+		};
+	};
+
+	rkisp0-vir1 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <0x43>;
+		status = "disabled";
+	};
+
+	rkisp0-vir2 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <0x43>;
+		status = "disabled";
+	};
+
+	rkisp0-vir3 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <0x43>;
+		status = "disabled";
+	};
+
+	rkisp1-vir0 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <0x45>;
+		status = "disabled";
+	};
+
+	rkisp1-vir1 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <0x45>;
+		status = "disabled";
+	};
+
+	rkisp1-vir2 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <0x45>;
+		status = "disabled";
+	};
+
+	rkisp1-vir3 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <0x45>;
+		status = "disabled";
+	};
+
+	rkispp0-vir0 {
+		compatible = "rockchip,rk3588-rkispp-vir";
+		rockchip,hw = <0x46>;
+		status = "disabled";
+	};
+
+	rkispp1-vir0 {
+		compatible = "rockchip,rk3588-rkispp-vir";
+		rockchip,hw = <0x47>;
+		status = "disabled";
+	};
+
+	rkvenc-ccu {
+		compatible = "rockchip,rkv-encoder-v2-ccu";
+		status = "okay";
+		phandle = <0xa6>;
+	};
+
+	rockchip-suspend {
+		compatible = "rockchip,pm-rk3588";
+		status = "okay";
+		rockchip,sleep-debug-en = <0x01>;
+		rockchip,sleep-mode-config = <0x5000604>;
+		rockchip,wakeup-config = <0x100>;
+	};
+
+	rockchip-system-monitor {
+		compatible = "rockchip,system-monitor";
+		rockchip,thermal-zone = "soc-thermal";
+	};
+
+	thermal-zones {
+
+		soc-thermal {
+			polling-delay-passive = <0x14>;
+			polling-delay = <0x3e8>;
+			sustainable-power = <0x834>;
+			thermal-sensors = <0x48 0x00>;
+
+			trips {
+
+				trip-point-0 {
+					temperature = <0x124f8>;
+					hysteresis = <0x7d0>;
+					type = "passive";
+				};
+
+				trip-point-1 {
+					temperature = <0x14c08>;
+					hysteresis = <0x7d0>;
+					type = "passive";
+					phandle = <0x49>;
+				};
+
+				soc-crit {
+					temperature = <0x1c138>;
+					hysteresis = <0x7d0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+
+				map0 {
+					trip = <0x49>;
+					cooling-device = <0x06 0xffffffff 0xffffffff>;
+					contribution = <0x400>;
+				};
+
+				map1 {
+					trip = <0x49>;
+					cooling-device = <0x0a 0xffffffff 0xffffffff>;
+					contribution = <0x400>;
+				};
+
+				map2 {
+					trip = <0x49>;
+					cooling-device = <0x0c 0xffffffff 0xffffffff>;
+					contribution = <0x400>;
+				};
+
+				map3 {
+					trip = <0x49>;
+					cooling-device = <0x4a 0xffffffff 0xffffffff>;
+					contribution = <0x400>;
+				};
+			};
+		};
+
+		bigcore0-thermal {
+			polling-delay-passive = <0x14>;
+			polling-delay = <0x3e8>;
+			thermal-sensors = <0x48 0x01>;
+		};
+
+		bigcore1-thermal {
+			polling-delay-passive = <0x14>;
+			polling-delay = <0x3e8>;
+			thermal-sensors = <0x48 0x02>;
+		};
+
+		littlecore-thermal {
+			polling-delay-passive = <0x14>;
+			polling-delay = <0x3e8>;
+			thermal-sensors = <0x48 0x03>;
+		};
+
+		center-thermal {
+			polling-delay-passive = <0x14>;
+			polling-delay = <0x3e8>;
+			thermal-sensors = <0x48 0x04>;
+		};
+
+		gpu-thermal {
+			polling-delay-passive = <0x14>;
+			polling-delay = <0x3e8>;
+			thermal-sensors = <0x48 0x05>;
+		};
+
+		npu-thermal {
+			polling-delay-passive = <0x14>;
+			polling-delay = <0x3e8>;
+			thermal-sensors = <0x48 0x06>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>;
+	};
+
+	sram@10f000 {
+		compatible = "mmio-sram";
+		reg = <0x00 0x10f000 0x00 0x100>;
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+		ranges = <0x00 0x00 0x10f000 0x100>;
+
+		sram@0 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x00 0x100>;
+			phandle = <0x39>;
+		};
+	};
+
+	gpu@fb000000 {
+		compatible = "arm,mali-bifrost";
+		reg = <0x00 0xfb000000 0x00 0x200000>;
+		interrupts = <0x00 0x5e 0x04 0x00 0x5d 0x04 0x00 0x5c 0x04>;
+		interrupt-names = "GPU\0MMU\0JOB";
+		clocks = <0x0e 0x05 0x02 0x115 0x02 0x116 0x02 0x114>;
+		clock-names = "clk_mali\0clk_gpu_coregroup\0clk_gpu_stacks\0clk_gpu";
+		assigned-clocks = <0x0e 0x05>;
+		assigned-clock-rates = <0xbebc200>;
+		power-domains = <0x4b 0x0c>;
+		operating-points-v2 = <0x4c>;
+		#cooling-cells = <0x02>;
+		dynamic-power-coefficient = <0xba6>;
+		upthreshold = <0x1e>;
+		downdifferential = <0x0a>;
+		status = "okay";
+		mali-supply = <0x4d>;
+		mem-supply = <0x4d>;
+		phandle = <0x4a>;
+	};
+
+	gpu-opp-table {
+		compatible = "operating-points-v2";
+		nvmem-cells = <0x4e>;
+		nvmem-cell-names = "leakage";
+		rockchip,pvtm-voltage-sel = <0x00 0x32f 0x00 0x330 0x343 0x01 0x344 0x35c 0x02 0x35d 0x375 0x03 0x376 0x38e 0x04 0x38f 0x270f 0x05>;
+		rockchip,pvtm-pvtpll;
+		rockchip,pvtm-offset = <0x1c>;
+		rockchip,pvtm-sample-time = <0x44c>;
+		rockchip,pvtm-freq = <0xc3500>;
+		rockchip,pvtm-volt = <0xb71b0>;
+		rockchip,pvtm-ref-temp = <0x19>;
+		rockchip,pvtm-temp-prop = <0xffffff79 0xffffff79>;
+		rockchip,pvtm-thermal-zone = "gpu-thermal";
+		clocks = <0x02 0x114>;
+		clock-names = "clk";
+		rockchip,grf = <0x4f>;
+		volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>;
+		low-volt-mem-read-margin = <0x04>;
+		intermediate-threshold-freq = <0x61a80>;
+		rockchip,temp-hysteresis = <0x1388>;
+		rockchip,low-temp = <0x2710>;
+		rockchip,low-temp-min-volt = <0xb71b0>;
+		rockchip,high-temp = <0x14c08>;
+		rockchip,high-temp-max-freq = <0xc3500>;
+		phandle = <0x4c>;
+
+		opp-300000000 {
+			opp-hz = <0x00 0x11e1a300>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-400000000 {
+			opp-hz = <0x00 0x17d78400>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-500000000 {
+			opp-hz = <0x00 0x1dcd6500>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-600000000 {
+			opp-hz = <0x00 0x23c34600>;
+			opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-700000000 {
+			opp-hz = <0x00 0x29b92700>;
+			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+			opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
+			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-800000000 {
+			opp-hz = <0x00 0x2faf0800>;
+			opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
+			opp-microvolt-L1 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>;
+			opp-microvolt-L2 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>;
+			opp-microvolt-L3 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>;
+			opp-microvolt-L4 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+		};
+
+		opp-900000000 {
+			opp-hz = <0x00 0x35a4e900>;
+			opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
+			opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
+			opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>;
+			opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>;
+			opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
+		};
+
+		opp-1000000000 {
+			opp-hz = <0x00 0x3b9aca00>;
+			opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>;
+			opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>;
+			opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>;
+			opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>;
+			opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
+		};
+	};
+
+	usbdrd3_0 {
+		compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3";
+		clocks = <0x02 0x1a3 0x02 0x1a2 0x02 0x1a1>;
+		clock-names = "ref\0suspend\0bus";
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+		status = "okay";
+
+		usb@fc000000 {
+			compatible = "snps,dwc3";
+			reg = <0x00 0xfc000000 0x00 0x400000>;
+			interrupts = <0x00 0xdc 0x04>;
+			power-domains = <0x4b 0x1f>;
+			resets = <0x02 0x2a4>;
+			reset-names = "usb3-otg";
+			dr_mode = "otg";
+			phys = <0x50 0x51>;
+			phy-names = "usb2-phy\0usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			quirk-skip-phy-init;
+			status = "okay";
+			usb-role-switch;
+
+			port {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0x52>;
+					phandle = <0x121>;
+				};
+			};
+		};
+	};
+
+	usb@fc800000 {
+		compatible = "generic-ehci";
+		reg = <0x00 0xfc800000 0x00 0x40000>;
+		interrupts = <0x00 0xd7 0x04>;
+		clocks = <0x02 0x19d 0x02 0x19e 0x53>;
+		clock-names = "usbhost\0arbiter\0utmi";
+		phys = <0x54>;
+		phy-names = "usb2-phy";
+		power-domains = <0x4b 0x1f>;
+		status = "okay";
+	};
+
+	usb@fc840000 {
+		compatible = "generic-ohci";
+		reg = <0x00 0xfc840000 0x00 0x40000>;
+		interrupts = <0x00 0xd8 0x04>;
+		clocks = <0x02 0x19d 0x02 0x19e 0x53>;
+		clock-names = "usbhost\0arbiter\0utmi";
+		phys = <0x54>;
+		phy-names = "usb2-phy";
+		power-domains = <0x4b 0x1f>;
+		status = "okay";
+	};
+
+	usb@fc880000 {
+		compatible = "generic-ehci";
+		reg = <0x00 0xfc880000 0x00 0x40000>;
+		interrupts = <0x00 0xda 0x04>;
+		clocks = <0x02 0x19f 0x02 0x1a0 0x55>;
+		clock-names = "usbhost\0arbiter\0utmi";
+		phys = <0x56>;
+		phy-names = "usb2-phy";
+		power-domains = <0x4b 0x1f>;
+		status = "okay";
+	};
+
+	usb@fc8c0000 {
+		compatible = "generic-ohci";
+		reg = <0x00 0xfc8c0000 0x00 0x40000>;
+		interrupts = <0x00 0xdb 0x04>;
+		clocks = <0x02 0x19f 0x02 0x1a0 0x55>;
+		clock-names = "usbhost\0arbiter\0utmi";
+		phys = <0x56>;
+		phy-names = "usb2-phy";
+		power-domains = <0x4b 0x1f>;
+		status = "okay";
+	};
+
+	iommu@fc900000 {
+		compatible = "arm,smmu-v3";
+		reg = <0x00 0xfc900000 0x00 0x200000>;
+		interrupts = <0x00 0x171 0x04 0x00 0x173 0x04 0x00 0x176 0x04 0x00 0x16f 0x04>;
+		interrupt-names = "eventq\0gerror\0priq\0cmdq-sync";
+		#iommu-cells = <0x01>;
+		status = "disabled";
+	};
+
+	iommu@fcb00000 {
+		compatible = "arm,smmu-v3";
+		reg = <0x00 0xfcb00000 0x00 0x200000>;
+		interrupts = <0x00 0x17d 0x04 0x00 0x17f 0x04 0x00 0x182 0x04 0x00 0x17b 0x04>;
+		interrupt-names = "eventq\0gerror\0priq\0cmdq-sync";
+		#iommu-cells = <0x01>;
+		status = "disabled";
+	};
+
+	usbhost3_0 {
+		compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3";
+		clocks = <0x02 0x179 0x02 0x178 0x02 0x177 0x02 0x17a 0x02 0x166 0x02 0x181>;
+		clock-names = "ref\0suspend\0bus\0utmi\0php\0pipe";
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+		status = "okay";
+
+		usb@fcd00000 {
+			compatible = "snps,dwc3";
+			reg = <0x00 0xfcd00000 0x00 0x400000>;
+			interrupts = <0x00 0xde 0x04>;
+			resets = <0x02 0x237>;
+			reset-names = "usb3-host";
+			dr_mode = "host";
+			phys = <0x57 0x04>;
+			phy-names = "usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			snps,dis_rxdet_inp3_quirk;
+			status = "okay";
+		};
+	};
+
+	syscon@fd588000 {
+		compatible = "rockchip,rk3588-pmu0-grf\0syscon\0simple-mfd";
+		reg = <0x00 0xfd588000 0x00 0x2000>;
+
+		reboot-mode {
+			compatible = "syscon-reboot-mode";
+			offset = <0x80>;
+			mode-bootloader = <0x5242c301>;
+			mode-charge = <0x5242c30b>;
+			mode-fastboot = <0x5242c309>;
+			mode-loader = <0x5242c301>;
+			mode-normal = <0x5242c300>;
+			mode-recovery = <0x5242c303>;
+			mode-ums = <0x5242c30c>;
+			mode-panic = <0x5242c307>;
+			mode-watchdog = <0x5242c308>;
+		};
+	};
+
+	syscon@fd58a000 {
+		compatible = "rockchip,rk3588-pmu1-grf\0syscon";
+		reg = <0x00 0xfd58a000 0x00 0x2000>;
+		phandle = <0xda>;
+	};
+
+	syscon@fd58c000 {
+		compatible = "rockchip,rk3588-sys-grf\0syscon\0simple-mfd";
+		reg = <0x00 0xfd58c000 0x00 0x1000>;
+		phandle = <0xb3>;
+
+		rgb {
+			compatible = "rockchip,rk3588-rgb";
+			pinctrl-names = "default";
+			pinctrl-0 = <0x58>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				port@0 {
+					reg = <0x00>;
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+
+					endpoint@2 {
+						reg = <0x02>;
+						remote-endpoint = <0x34>;
+						status = "disabled";
+						phandle = <0xc8>;
+					};
+				};
+			};
+		};
+	};
+
+	syscon@fd590000 {
+		compatible = "rockchip,rk3588-bigcore0-grf\0syscon";
+		reg = <0x00 0xfd590000 0x00 0x100>;
+		phandle = <0x22>;
+	};
+
+	syscon@fd592000 {
+		compatible = "rockchip,rk3588-bigcore1-grf\0syscon";
+		reg = <0x00 0xfd592000 0x00 0x100>;
+		phandle = <0x24>;
+	};
+
+	syscon@fd594000 {
+		compatible = "rockchip,rk3588-litcore-grf\0syscon";
+		reg = <0x00 0xfd594000 0x00 0x100>;
+		phandle = <0x20>;
+	};
+
+	syscon@fd598000 {
+		compatible = "rockchip,rk3588-dsu-grf\0syscon";
+		reg = <0x00 0xfd598000 0x00 0x100>;
+	};
+
+	syscon@fd5a0000 {
+		compatible = "rockchip,rk3588-gpu-grf\0syscon";
+		reg = <0x00 0xfd5a0000 0x00 0x100>;
+		phandle = <0x4f>;
+	};
+
+	syscon@fd5a2000 {
+		compatible = "rockchip,rk3588-npu-grf\0syscon";
+		reg = <0x00 0xfd5a2000 0x00 0x100>;
+		phandle = <0x99>;
+	};
+
+	syscon@fd5a4000 {
+		compatible = "rockchip,rk3588-vop-grf\0syscon";
+		reg = <0x00 0xfd5a4000 0x00 0x2000>;
+		phandle = <0xb8>;
+	};
+
+	syscon@fd5a6000 {
+		compatible = "rockchip,rk3588-vo-grf\0syscon";
+		reg = <0x00 0xfd5a6000 0x00 0x2000>;
+		clocks = <0x59>;
+		phandle = <0x15d>;
+	};
+
+	syscon@fd5a8000 {
+		compatible = "rockchip,rk3588-vo-grf\0syscon";
+		reg = <0x00 0xfd5a8000 0x00 0x100>;
+		clocks = <0x5a>;
+		phandle = <0xb9>;
+	};
+
+	syscon@fd5ac000 {
+		compatible = "rockchip,rk3588-usb-grf\0syscon";
+		reg = <0x00 0xfd5ac000 0x00 0x4000>;
+		phandle = <0x5b>;
+	};
+
+	syscon@fd5b0000 {
+		compatible = "rockchip,rk3588-php-grf\0syscon";
+		reg = <0x00 0xfd5b0000 0x00 0x1000>;
+		phandle = <0x5d>;
+	};
+
+	syscon@fd5b4000 {
+		compatible = "rockchip,mipi-dphy-grf\0syscon";
+		reg = <0x00 0xfd5b4000 0x00 0x1000>;
+		phandle = <0x163>;
+	};
+
+	syscon@fd5b5000 {
+		compatible = "rockchip,mipi-dphy-grf\0syscon";
+		reg = <0x00 0xfd5b5000 0x00 0x1000>;
+	};
+
+	syscon@fd5bc000 {
+		compatible = "rockchip,pipe-phy-grf\0syscon";
+		reg = <0x00 0xfd5bc000 0x00 0x100>;
+		phandle = <0x164>;
+	};
+
+	syscon@fd5c4000 {
+		compatible = "rockchip,pipe-phy-grf\0syscon";
+		reg = <0x00 0xfd5c4000 0x00 0x100>;
+		phandle = <0x165>;
+	};
+
+	syscon@fd5c8000 {
+		compatible = "rockchip,rk3588-usbdpphy-grf\0syscon";
+		reg = <0x00 0xfd5c8000 0x00 0x4000>;
+		phandle = <0x15c>;
+	};
+
+	syscon@fd5d0000 {
+		compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd";
+		reg = <0x00 0xfd5d0000 0x00 0x4000>;
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+		phandle = <0x15b>;
+
+		usb2-phy@0 {
+			compatible = "rockchip,rk3588-usb2phy";
+			reg = <0x00 0x10>;
+			interrupts = <0x00 0x189 0x04>;
+			resets = <0x02 0xc0047 0x02 0x488>;
+			reset-names = "phy\0apb";
+			clocks = <0x02 0x2b5>;
+			clock-names = "phyclk";
+			clock-output-names = "usb480m_phy0";
+			#clock-cells = <0x00>;
+			rockchip,usbctrl-grf = <0x5b>;
+			status = "okay";
+			phandle = <0x15e>;
+
+			otg-port {
+				#phy-cells = <0x00>;
+				status = "okay";
+				rockchip,typec-vbus-det;
+				phandle = <0x50>;
+			};
+		};
+	};
+
+	syscon@fd5d8000 {
+		compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd";
+		reg = <0x00 0xfd5d8000 0x00 0x4000>;
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+
+		usb2-phy@8000 {
+			compatible = "rockchip,rk3588-usb2phy";
+			reg = <0x8000 0x10>;
+			interrupts = <0x00 0x187 0x04>;
+			resets = <0x02 0xc0049 0x02 0x48a>;
+			reset-names = "phy\0apb";
+			clocks = <0x02 0x2b5>;
+			clock-names = "phyclk";
+			clock-output-names = "usb480m_phy2";
+			#clock-cells = <0x00>;
+			status = "okay";
+			phandle = <0x53>;
+
+			host-port {
+				#phy-cells = <0x00>;
+				status = "okay";
+				phy-supply = <0x5c>;
+				phandle = <0x54>;
+			};
+		};
+	};
+
+	syscon@fd5dc000 {
+		compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd";
+		reg = <0x00 0xfd5dc000 0x00 0x4000>;
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+
+		usb2-phy@c000 {
+			compatible = "rockchip,rk3588-usb2phy";
+			reg = <0xc000 0x10>;
+			interrupts = <0x00 0x188 0x04>;
+			resets = <0x02 0xc004a 0x02 0x48b>;
+			reset-names = "phy\0apb";
+			clocks = <0x02 0x2b5>;
+			clock-names = "phyclk";
+			clock-output-names = "usb480m_phy3";
+			#clock-cells = <0x00>;
+			status = "okay";
+			phandle = <0x55>;
+
+			host-port {
+				#phy-cells = <0x00>;
+				status = "okay";
+				phy-supply = <0x5c>;
+				phandle = <0x56>;
+			};
+		};
+	};
+
+	syscon@fd5e0000 {
+		compatible = "rockchip,rk3588-hdptxphy-grf\0syscon";
+		reg = <0x00 0xfd5e0000 0x00 0x100>;
+		phandle = <0x15a>;
+	};
+
+	syscon@fd5e8000 {
+		compatible = "rockchip,mipi-dcphy-grf\0syscon";
+		reg = <0x00 0xfd5e8000 0x00 0x4000>;
+		phandle = <0x161>;
+	};
+
+	syscon@fd5ec000 {
+		compatible = "rockchip,mipi-dcphy-grf\0syscon";
+		reg = <0x00 0xfd5ec000 0x00 0x4000>;
+		phandle = <0x162>;
+	};
+
+	syscon@fd5f0000 {
+		compatible = "rockchip,rk3588-ioc\0syscon";
+		reg = <0x00 0xfd5f0000 0x00 0x10000>;
+		phandle = <0x166>;
+	};
+
+	sram@fd601000 {
+		compatible = "mmio-sram";
+		reg = <0x00 0xfd601000 0x00 0xef000>;
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+		ranges = <0x00 0x00 0xfd601000 0xef000>;
+
+		rkvdec-sram@0 {
+			reg = <0x00 0x78000>;
+			phandle = <0xaa>;
+		};
+
+		rkvdec-sram@78000 {
+			reg = <0x78000 0x77000>;
+			phandle = <0xac>;
+		};
+	};
+
+	clock-controller@fd7c0000 {
+		compatible = "rockchip,rk3588-cru";
+		rockchip,grf = <0x5d>;
+		reg = <0x00 0xfd7c0000 0x00 0x5c000>;
+		#clock-cells = <0x01>;
+		#reset-cells = <0x01>;
+		assigned-clocks = <0x02 0x09 0x02 0x05 0x02 0x08 0x02 0x07 0x02 0xd8 0x02 0xda 0x02 0xd9 0x02 0x10e 0x02 0x10f 0x02 0x110 0x02 0x299 0x02 0x29a 0x02 0x270 0x02 0x7b 0x02 0xec 0x02 0x114>;
+		assigned-clock-rates = <0x4190ab00 0x2ee00000 0x32a9f880 0x46cf7100 0x29d7ab80 0x17d78400 0x1dcd6500 0x2faf0800 0x5f5e100 0x17d78400 0x5f5e100 0xbebc200 0x2faf0800 0x165a0bc0 0x8f0d180 0xbebc200>;
+		phandle = <0x02>;
+	};
+
+	i2c@fd880000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfd880000 0x00 0x1000>;
+		clocks = <0x02 0x287 0x02 0x286>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x13d 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x5e>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+
+		rk8602@42 {
+			compatible = "rockchip,rk8602";
+			reg = <0x42>;
+			vin-supply = <0x5f>;
+			regulator-compatible = "rk860x-reg";
+			regulator-name = "vdd_cpu_big0_s0";
+			regulator-min-microvolt = <0x86470>;
+			regulator-max-microvolt = <0x100590>;
+			regulator-ramp-delay = <0x8fc>;
+			rockchip,suspend-voltage-selector = <0x01>;
+			regulator-boot-on;
+			regulator-always-on;
+			phandle = <0x18>;
+
+			regulator-state-mem {
+				regulator-off-in-suspend;
+			};
+		};
+
+		rk8603@43 {
+			compatible = "rockchip,rk8603";
+			reg = <0x43>;
+			vin-supply = <0x5f>;
+			regulator-compatible = "rk860x-reg";
+			regulator-name = "vdd_cpu_big1_s0";
+			regulator-min-microvolt = <0x86470>;
+			regulator-max-microvolt = <0x100590>;
+			regulator-ramp-delay = <0x8fc>;
+			rockchip,suspend-voltage-selector = <0x01>;
+			regulator-boot-on;
+			regulator-always-on;
+			phandle = <0x1c>;
+
+			regulator-state-mem {
+				regulator-off-in-suspend;
+			};
+		};
+	};
+
+	serial@fd890000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfd890000 0x00 0x100>;
+		interrupts = <0x00 0x14b 0x04>;
+		clocks = <0x02 0x2ae 0x02 0x2af>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0x60 0x06 0x60 0x07>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x61>;
+		status = "disabled";
+	};
+
+	pwm@fd8b0000 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfd8b0000 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x62>;
+		clocks = <0x02 0x2a5 0x02 0x2a4>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+	};
+
+	pwm@fd8b0010 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfd8b0010 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x63>;
+		clocks = <0x02 0x2a5 0x02 0x2a4>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+	};
+
+	pwm@fd8b0020 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfd8b0020 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x64>;
+		clocks = <0x02 0x2a5 0x02 0x2a4>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+	};
+
+	pwm@fd8b0030 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfd8b0030 0x00 0x10>;
+		interrupts = <0x00 0x158 0x04 0x00 0x159 0x04>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x65>;
+		clocks = <0x02 0x2a5 0x02 0x2a4>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+	};
+
+	power-management@fd8d8000 {
+		compatible = "rockchip,rk3588-pmu\0syscon\0simple-mfd";
+		reg = <0x00 0xfd8d8000 0x00 0x400>;
+		phandle = <0xba>;
+
+		power-controller {
+			compatible = "rockchip,rk3588-power-controller";
+			#power-domain-cells = <0x01>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			status = "okay";
+			phandle = <0x4b>;
+
+			power-domain@8 {
+				reg = <0x08>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				power-domain@9 {
+					reg = <0x09>;
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+					clocks = <0x02 0x12f 0x02 0x131 0x02 0x130 0x02 0x126>;
+					pm_qos = <0x66 0x67 0x68>;
+
+					power-domain@10 {
+						reg = <0x0a>;
+						clocks = <0x02 0x12f 0x02 0x131 0x02 0x130>;
+						pm_qos = <0x69>;
+					};
+
+					power-domain@11 {
+						reg = <0x0b>;
+						clocks = <0x02 0x12f 0x02 0x131 0x02 0x130>;
+						pm_qos = <0x6a>;
+					};
+				};
+			};
+
+			power-domain@12 {
+				reg = <0x0c>;
+				clocks = <0x02 0x114 0x02 0x115 0x02 0x116>;
+				pm_qos = <0x6b 0x6c 0x6d 0x6e>;
+			};
+
+			power-domain@13 {
+				reg = <0x0d>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				power-domain@14 {
+					reg = <0x0e>;
+					clocks = <0x02 0x18f 0x02 0x1be 0x02 0x1bc 0x02 0x190 0x02 0x18e>;
+					pm_qos = <0x6f>;
+				};
+
+				power-domain@15 {
+					reg = <0x0f>;
+					clocks = <0x02 0x194 0x02 0x1be 0x02 0x1bc 0x02 0x195>;
+					pm_qos = <0x70>;
+				};
+
+				power-domain@16 {
+					reg = <0x10>;
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+					clocks = <0x02 0x1c4 0x02 0x1c5>;
+					pm_qos = <0x71 0x72 0x73>;
+
+					power-domain@17 {
+						reg = <0x11>;
+						clocks = <0x02 0x1c9 0x02 0x1c4 0x02 0x1c5 0x02 0x1ca>;
+						pm_qos = <0x74 0x75 0x76>;
+					};
+				};
+			};
+
+			power-domain@21 {
+				reg = <0x15>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				clocks = <0x02 0x1be 0x02 0x1bd 0x02 0x1bc 0x02 0x1bf 0x02 0x1aa 0x02 0x1a9 0x02 0x1ac 0x02 0x1ad 0x02 0x1ae 0x02 0x1af 0x02 0x1b0 0x02 0x1b1 0x02 0x1b2 0x02 0x1b3 0x02 0x1b4 0x02 0x1b5 0x02 0x1b7 0x02 0x1b6>;
+				pm_qos = <0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e>;
+
+				power-domain@23 {
+					reg = <0x17>;
+					clocks = <0x02 0x4b 0x02 0x49 0x02 0x1be>;
+					pm_qos = <0x7f>;
+				};
+
+				power-domain@14 {
+					reg = <0x0e>;
+					clocks = <0x02 0x18f 0x02 0x1be 0x02 0x1bc 0x02 0x190>;
+					pm_qos = <0x6f>;
+				};
+
+				power-domain@15 {
+					reg = <0x0f>;
+					clocks = <0x02 0x194 0x02 0x1be 0x02 0x1bc>;
+					pm_qos = <0x70>;
+				};
+
+				power-domain@22 {
+					reg = <0x16>;
+					clocks = <0x02 0x1ba 0x02 0x1b9>;
+					pm_qos = <0x80>;
+				};
+			};
+
+			power-domain@24 {
+				reg = <0x18>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				clocks = <0x02 0x26e 0x02 0x26d 0x02 0x270>;
+				pm_qos = <0x81 0x82>;
+
+				power-domain@25 {
+					reg = <0x19>;
+					clocks = <0x02 0x1f6 0x02 0x1f7 0x02 0x1f5 0x02 0x1f3 0x02 0x1ee 0x02 0x1ed 0x02 0x26d>;
+					pm_qos = <0x83>;
+				};
+			};
+
+			power-domain@26 {
+				reg = <0x1a>;
+				clocks = <0x02 0x22e 0x02 0x22f 0x02 0x22d 0x02 0x218 0x02 0x217 0x02 0x22b 0x02 0x264>;
+				pm_qos = <0x84 0x85>;
+			};
+
+			power-domain@27 {
+				reg = <0x1b>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				clocks = <0x02 0x1e1 0x02 0x1e2 0x02 0x1df 0x02 0x1de 0x02 0x1e5 0x02 0x1e4>;
+				pm_qos = <0x86 0x87 0x88 0x89>;
+
+				power-domain@28 {
+					reg = <0x1c>;
+					clocks = <0x02 0x121 0x02 0x120 0x02 0x1e1 0x02 0x1e2>;
+					pm_qos = <0x8a 0x8b>;
+				};
+
+				power-domain@29 {
+					reg = <0x1d>;
+					clocks = <0x02 0x1d6 0x02 0x1d5 0x02 0x1d9 0x02 0x1d8 0x02 0x1e2>;
+					pm_qos = <0x8c 0x8d>;
+				};
+			};
+
+			power-domain@30 {
+				reg = <0x1e>;
+				clocks = <0x02 0x189 0x02 0x18a>;
+				pm_qos = <0x8e>;
+			};
+
+			power-domain@31 {
+				reg = <0x1f>;
+				clocks = <0x02 0x166 0x02 0x19b 0x02 0x19c 0x02 0x19d 0x02 0x19e 0x02 0x19f 0x02 0x1a0>;
+				pm_qos = <0x8f 0x90 0x91 0x92>;
+			};
+
+			power-domain@33 {
+				reg = <0x21>;
+				clocks = <0x02 0x166 0x02 0x169 0x02 0x16a>;
+			};
+
+			power-domain@34 {
+				reg = <0x22>;
+				clocks = <0x02 0x166 0x02 0x169 0x02 0x16a>;
+			};
+
+			power-domain@37 {
+				reg = <0x25>;
+				clocks = <0x02 0x199 0x02 0x140>;
+				pm_qos = <0x93>;
+			};
+
+			power-domain@38 {
+				reg = <0x26>;
+				clocks = <0x02 0x3c 0x02 0x3d>;
+			};
+
+			power-domain@40 {
+				reg = <0x28>;
+				pm_qos = <0x94>;
+			};
+		};
+	};
+
+	pvtm@fda40000 {
+		compatible = "rockchip,rk3588-bigcore0-pvtm";
+		reg = <0x00 0xfda40000 0x00 0x100>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		pvtm@0 {
+			reg = <0x00>;
+			clocks = <0x02 0x2c6 0x02 0x15>;
+			clock-names = "clk\0pclk";
+		};
+	};
+
+	pvtm@fda50000 {
+		compatible = "rockchip,rk3588-bigcore1-pvtm";
+		reg = <0x00 0xfda50000 0x00 0x100>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		pvtm@1 {
+			reg = <0x01>;
+			clocks = <0x02 0x2c8 0x02 0x17>;
+			clock-names = "clk\0pclk";
+		};
+	};
+
+	pvtm@fda60000 {
+		compatible = "rockchip,rk3588-litcore-pvtm";
+		reg = <0x00 0xfda60000 0x00 0x100>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		pvtm@2 {
+			reg = <0x02>;
+			clocks = <0x02 0x2ca 0x02 0x1b>;
+			clock-names = "clk\0pclk";
+		};
+	};
+
+	pvtm@fdaf0000 {
+		compatible = "rockchip,rk3588-npu-pvtm";
+		reg = <0x00 0xfdaf0000 0x00 0x100>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		pvtm@3 {
+			reg = <0x03>;
+			clocks = <0x02 0x12b 0x02 0x129>;
+			clock-names = "clk\0pclk";
+			resets = <0x02 0x1de 0x02 0x1dc>;
+			reset-names = "rts\0rst-p";
+		};
+	};
+
+	pvtm@fdb30000 {
+		compatible = "rockchip,rk3588-gpu-pvtm";
+		reg = <0x00 0xfdb30000 0x00 0x100>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		pvtm@4 {
+			reg = <0x04>;
+			clocks = <0x02 0x118>;
+			clock-names = "clk";
+			resets = <0x02 0x430 0x02 0x42f>;
+			reset-names = "rts\0rst-p";
+		};
+	};
+
+	npu@fdab0000 {
+		compatible = "rockchip,rk3588-rknpu";
+		reg = <0x00 0xfdab0000 0x00 0x10000 0x00 0xfdac0000 0x00 0x10000 0x00 0xfdad0000 0x00 0x10000>;
+		interrupts = <0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04>;
+		interrupt-names = "npu0_irq\0npu1_irq\0npu2_irq";
+		clocks = <0x0e 0x06 0x02 0x12d 0x02 0x122 0x02 0x124 0x02 0x12e 0x02 0x123 0x02 0x125 0x02 0x131>;
+		clock-names = "clk_npu\0aclk0\0aclk1\0aclk2\0hclk0\0hclk1\0hclk2\0pclk";
+		assigned-clocks = <0x0e 0x06>;
+		assigned-clock-rates = <0xbebc200>;
+		resets = <0x02 0x1e6 0x02 0x1b0 0x02 0x1c0 0x02 0x1e8 0x02 0x1b2 0x02 0x1c2>;
+		reset-names = "srst_a0\0srst_a1\0srst_a2\0srst_h0\0srst_h1\0srst_h2";
+		power-domains = <0x4b 0x09 0x4b 0x0a 0x4b 0x0b>;
+		power-domain-names = "npu0\0npu1\0npu2";
+		operating-points-v2 = <0x95>;
+		iommus = <0x96>;
+		status = "okay";
+		rknpu-supply = <0x97>;
+		mem-supply = <0x97>;
+	};
+
+	npu-opp-table {
+		compatible = "operating-points-v2";
+		nvmem-cells = <0x98>;
+		nvmem-cell-names = "leakage";
+		rockchip,pvtm-voltage-sel = <0x00 0x32f 0x00 0x330 0x343 0x01 0x344 0x35c 0x02 0x35d 0x375 0x03 0x376 0x38e 0x04 0x38f 0x270f 0x05>;
+		rockchip,pvtm-pvtpll;
+		rockchip,pvtm-offset = <0x50>;
+		rockchip,pvtm-sample-time = <0x44c>;
+		rockchip,pvtm-freq = <0xc3500>;
+		rockchip,pvtm-volt = <0xb71b0>;
+		rockchip,pvtm-ref-temp = <0x19>;
+		rockchip,pvtm-temp-prop = <0xffffff8f 0xffffff8f>;
+		rockchip,pvtm-thermal-zone = "npu-thermal";
+		clocks = <0x02 0x12a>;
+		clock-names = "pclk";
+		rockchip,grf = <0x99>;
+		volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>;
+		low-volt-read-margin = <0x04>;
+		intermediate-threshold-freq = <0x7a120>;
+		rockchip,init-freq = <0xf4240>;
+		rockchip,temp-hysteresis = <0x1388>;
+		rockchip,low-temp = <0x2710>;
+		rockchip,low-temp-min-volt = <0xb71b0>;
+		rockchip,high-temp = <0x14c08>;
+		rockchip,high-temp-max-freq = <0xc3500>;
+		phandle = <0x95>;
+
+		opp-300000000 {
+			opp-hz = <0x00 0x11e1a300>;
+			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+			opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
+			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-400000000 {
+			opp-hz = <0x00 0x17d78400>;
+			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+			opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
+			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-500000000 {
+			opp-hz = <0x00 0x1dcd6500>;
+			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+			opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
+			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-600000000 {
+			opp-hz = <0x00 0x23c34600>;
+			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+			opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
+			opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-700000000 {
+			opp-hz = <0x00 0x29b92700>;
+			opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+			opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
+			opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+			opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
+		};
+
+		opp-800000000 {
+			opp-hz = <0x00 0x2faf0800>;
+			opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
+			opp-microvolt-L2 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>;
+			opp-microvolt-L3 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>;
+			opp-microvolt-L4 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>;
+			opp-microvolt-L5 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
+		};
+
+		opp-900000000 {
+			opp-hz = <0x00 0x35a4e900>;
+			opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
+			opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
+			opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>;
+			opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>;
+			opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
+			opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>;
+		};
+
+		opp-1000000000 {
+			opp-hz = <0x00 0x3b9aca00>;
+			opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>;
+			opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>;
+			opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>;
+			opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>;
+			opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
+			opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
+		};
+	};
+
+	iommu@fdab9000 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdab9000 0x00 0x100 0x00 0xfdaba000 0x00 0x100 0x00 0xfdaca000 0x00 0x100 0x00 0xfdada000 0x00 0x100>;
+		interrupts = <0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04>;
+		interrupt-names = "npu0_mmu\0npu1_mmu\0npu2_mmu";
+		clocks = <0x02 0x12d 0x02 0x122 0x02 0x124 0x02 0x12e 0x02 0x123 0x02 0x125>;
+		clock-names = "aclk0\0aclk1\0aclk2\0iface0\0iface1\0iface2";
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0x96>;
+	};
+
+	vdpu@fdb50400 {
+		compatible = "rockchip,vpu-decoder-v2";
+		reg = <0x00 0xfdb50400 0x00 0x400>;
+		interrupts = <0x00 0x77 0x04>;
+		interrupt-names = "irq_vdpu";
+		clocks = <0x02 0x1c0 0x02 0x1c1>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		rockchip,normal-rates = <0x2367b880 0x00>;
+		assigned-clocks = <0x02 0x1c0>;
+		assigned-clock-rates = <0x2367b880>;
+		resets = <0x02 0x2c8 0x02 0x2c9>;
+		reset-names = "shared_video_a\0shared_video_h";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0x9a>;
+		rockchip,srv = <0x9b>;
+		rockchip,taskqueue-node = <0x00>;
+		power-domains = <0x4b 0x15>;
+		status = "okay";
+	};
+
+	iommu@fdb50800 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdb50800 0x00 0x40>;
+		interrupts = <0x00 0x76 0x04>;
+		interrupt-names = "irq_vdpu_mmu";
+		clocks = <0x02 0x1c0 0x02 0x1c1>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x4b 0x15>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0x9a>;
+	};
+
+	avsd-plus@fdb51000 {
+		compatible = "rockchip,avs-plus-decoder";
+		reg = <0x00 0xfdb51000 0x00 0x200>;
+		interrupts = <0x00 0x77 0x04>;
+		interrupt-names = "irq_avsd";
+		clocks = <0x02 0x1c0 0x02 0x1c1>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		resets = <0x02 0x2c8 0x02 0x2c9>;
+		reset-names = "shared_video_a\0shared_video_h";
+		iommus = <0x9a>;
+		power-domains = <0x4b 0x15>;
+		rockchip,srv = <0x9b>;
+		rockchip,taskqueue-node = <0x00>;
+		status = "disabled";
+	};
+
+	rga@fdb60000 {
+		compatible = "rockchip,rga3_core0";
+		reg = <0x00 0xfdb60000 0x00 0x1000>;
+		interrupts = <0x00 0x72 0x04>;
+		interrupt-names = "rga3_core0_irq";
+		clocks = <0x02 0x1ba 0x02 0x1b9 0x02 0x1bb>;
+		clock-names = "aclk_rga3_0\0hclk_rga3_0\0clk_rga3_0";
+		power-domains = <0x4b 0x16>;
+		iommus = <0x9c>;
+		status = "okay";
+	};
+
+	iommu@fdb60f00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdb60f00 0x00 0x100>;
+		interrupts = <0x00 0x72 0x04>;
+		interrupt-names = "rga3_0_mmu";
+		clocks = <0x02 0x1ba 0x02 0x1b9>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x4b 0x16>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0x9c>;
+	};
+
+	rga@fdb70000 {
+		compatible = "rockchip,rga3_core1";
+		reg = <0x00 0xfdb70000 0x00 0x1000>;
+		interrupts = <0x00 0x73 0x04>;
+		interrupt-names = "rga3_core1_irq";
+		clocks = <0x02 0x18a 0x02 0x189 0x02 0x18b>;
+		clock-names = "aclk_rga3_1\0hclk_rga3_1\0clk_rga3_1";
+		power-domains = <0x4b 0x1e>;
+		iommus = <0x9d>;
+		status = "okay";
+	};
+
+	iommu@fdb70f00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdb70f00 0x00 0x100>;
+		interrupts = <0x00 0x73 0x04>;
+		interrupt-names = "rga3_1_mmu";
+		clocks = <0x02 0x18a 0x02 0x189>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x4b 0x1e>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0x9d>;
+	};
+
+	rga@fdb80000 {
+		compatible = "rockchip,rga2_core0";
+		reg = <0x00 0xfdb80000 0x00 0x1000>;
+		interrupts = <0x00 0x74 0x04>;
+		interrupt-names = "rga2_irq";
+		clocks = <0x02 0x1b7 0x02 0x1b6 0x02 0x1b8>;
+		clock-names = "aclk_rga2\0hclk_rga2\0clk_rga2";
+		power-domains = <0x4b 0x15>;
+		status = "okay";
+	};
+
+	jpegd@fdb90000 {
+		compatible = "rockchip,rkv-jpeg-decoder-v1";
+		reg = <0x00 0xfdb90000 0x00 0x400>;
+		interrupts = <0x00 0x81 0x04>;
+		interrupt-names = "irq_jpegd";
+		clocks = <0x02 0x1b4 0x02 0x1b5>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		rockchip,normal-rates = <0x23c34600 0x00>;
+		assigned-clocks = <0x02 0x1b4>;
+		assigned-clock-rates = <0x23c34600>;
+		resets = <0x02 0x2d2 0x02 0x2d3>;
+		reset-names = "video_a\0video_h";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0x9e>;
+		rockchip,srv = <0x9b>;
+		rockchip,taskqueue-node = <0x01>;
+		power-domains = <0x4b 0x15>;
+		status = "okay";
+	};
+
+	iommu@fdb90480 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdb90480 0x00 0x40>;
+		interrupts = <0x00 0x82 0x04>;
+		interrupt-names = "irq_jpegd_mmu";
+		clocks = <0x02 0x1b4 0x02 0x1b5>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x4b 0x15>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0x9e>;
+	};
+
+	jpege-core@fdba0000 {
+		compatible = "rockchip,vpu-encoder-v2-core";
+		reg = <0x00 0xfdba0000 0x00 0x400>;
+		interrupts = <0x00 0x7a 0x04>;
+		interrupt-names = "irq_jpege0";
+		clocks = <0x02 0x1ac 0x02 0x1ad>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		rockchip,normal-rates = <0x2367b880 0x00>;
+		assigned-clocks = <0x02 0x1ac>;
+		assigned-clock-rates = <0x2367b880>;
+		resets = <0x02 0x2ca 0x02 0x2cb>;
+		reset-names = "video_a\0video_h";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0x9f>;
+		rockchip,srv = <0x9b>;
+		rockchip,taskqueue-node = <0x02>;
+		rockchip,ccu = <0xa0>;
+		power-domains = <0x4b 0x15>;
+		status = "okay";
+	};
+
+	iommu@fdba0800 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdba0800 0x00 0x40>;
+		interrupts = <0x00 0x79 0x04>;
+		interrupt-names = "irq_jpege0_mmu";
+		clocks = <0x02 0x1ac 0x02 0x1ad>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x4b 0x15>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0x9f>;
+	};
+
+	jpege-core@fdba4000 {
+		compatible = "rockchip,vpu-encoder-v2-core";
+		reg = <0x00 0xfdba4000 0x00 0x400>;
+		interrupts = <0x00 0x7c 0x04>;
+		interrupt-names = "irq_jpege1";
+		clocks = <0x02 0x1ae 0x02 0x1af>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		rockchip,normal-rates = <0x2367b880 0x00>;
+		assigned-clocks = <0x02 0x1ae>;
+		assigned-clock-rates = <0x2367b880>;
+		resets = <0x02 0x2cc 0x02 0x2cd>;
+		reset-names = "video_a\0video_h";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xa1>;
+		rockchip,srv = <0x9b>;
+		rockchip,taskqueue-node = <0x03>;
+		rockchip,ccu = <0xa0>;
+		power-domains = <0x4b 0x15>;
+		status = "okay";
+	};
+
+	iommu@fdba4800 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdba4800 0x00 0x40>;
+		interrupts = <0x00 0x7b 0x04>;
+		interrupt-names = "irq_jpege1_mmu";
+		clocks = <0x02 0x1ae 0x02 0x1af>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x4b 0x15>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0xa1>;
+	};
+
+	jpege-core@fdba8000 {
+		compatible = "rockchip,vpu-encoder-v2-core";
+		reg = <0x00 0xfdba8000 0x00 0x400>;
+		interrupts = <0x00 0x7e 0x04>;
+		interrupt-names = "irq_jpege2";
+		clocks = <0x02 0x1b0 0x02 0x1b1>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		rockchip,normal-rates = <0x2367b880 0x00>;
+		assigned-clocks = <0x02 0x1b0>;
+		assigned-clock-rates = <0x2367b880>;
+		resets = <0x02 0x2ce 0x02 0x2cf>;
+		reset-names = "video_a\0video_h";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xa2>;
+		rockchip,srv = <0x9b>;
+		rockchip,taskqueue-node = <0x04>;
+		rockchip,ccu = <0xa0>;
+		power-domains = <0x4b 0x15>;
+		status = "okay";
+	};
+
+	iommu@fdba8800 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdba8800 0x00 0x40>;
+		interrupts = <0x00 0x7d 0x04>;
+		interrupt-names = "irq_jpege2_mmu";
+		clocks = <0x02 0x1b0 0x02 0x1b1>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x4b 0x15>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0xa2>;
+	};
+
+	jpege-core@fdbac000 {
+		compatible = "rockchip,vpu-encoder-v2-core";
+		reg = <0x00 0xfdbac000 0x00 0x400>;
+		interrupts = <0x00 0x80 0x04>;
+		interrupt-names = "irq_jpege3";
+		clocks = <0x02 0x1b2 0x02 0x1b3>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		rockchip,normal-rates = <0x2367b880 0x00>;
+		assigned-clocks = <0x02 0x1b2>;
+		assigned-clock-rates = <0x2367b880>;
+		resets = <0x02 0x2d0 0x02 0x2d1>;
+		reset-names = "video_a\0video_h";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xa3>;
+		rockchip,srv = <0x9b>;
+		rockchip,taskqueue-node = <0x05>;
+		rockchip,ccu = <0xa0>;
+		power-domains = <0x4b 0x15>;
+		status = "okay";
+	};
+
+	iommu@fdbac800 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdbac800 0x00 0x40>;
+		interrupts = <0x00 0x7f 0x04>;
+		interrupt-names = "irq_jpege3_mmu";
+		clocks = <0x02 0x1b2 0x02 0x1b3>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x4b 0x15>;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0xa3>;
+	};
+
+	iep@fdbb0000 {
+		compatible = "rockchip,iep-v2";
+		reg = <0x00 0xfdbb0000 0x00 0x500>;
+		interrupts = <0x00 0x75 0x04>;
+		interrupt-names = "irq_iep";
+		clocks = <0x02 0x1aa 0x02 0x1a9 0x02 0x1ab>;
+		clock-names = "aclk\0hclk\0sclk";
+		resets = <0x02 0x2d5 0x02 0x2d4 0x02 0x2d6>;
+		reset-names = "rst_a\0rst_h\0rst_s";
+		rockchip,skip-pmu-idle-request;
+		power-domains = <0x4b 0x15>;
+		rockchip,srv = <0x9b>;
+		rockchip,taskqueue-node = <0x06>;
+		iommus = <0xa4>;
+		status = "okay";
+	};
+
+	iommu@fdbb0800 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdbb0800 0x00 0x100>;
+		interrupts = <0x00 0x75 0x04>;
+		interrupt-names = "irq_iep_mmu";
+		clocks = <0x02 0x1aa 0x02 0x1a9>;
+		clock-names = "aclk\0iface";
+		#iommu-cells = <0x00>;
+		power-domains = <0x4b 0x15>;
+		status = "okay";
+		phandle = <0xa4>;
+	};
+
+	rkvenc-core@fdbd0000 {
+		compatible = "rockchip,rkv-encoder-v2-core";
+		reg = <0x00 0xfdbd0000 0x00 0x6000>;
+		interrupts = <0x00 0x65 0x04>;
+		interrupt-names = "irq_rkvenc0";
+		clocks = <0x02 0x1c5 0x02 0x1c4 0x02 0x1c6>;
+		clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core";
+		rockchip,normal-rates = <0x23c34600 0x00 0x2faf0800>;
+		assigned-clocks = <0x02 0x1c5 0x02 0x1c6>;
+		assigned-clock-rates = <0x23c34600 0x2faf0800>;
+		resets = <0x02 0x2f5 0x02 0x2f4 0x02 0x2f6>;
+		reset-names = "video_a\0video_h\0video_core";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xa5>;
+		rockchip,srv = <0x9b>;
+		rockchip,ccu = <0xa6>;
+		rockchip,taskqueue-node = <0x07>;
+		rockchip,task-capacity = <0x08>;
+		power-domains = <0x4b 0x10>;
+		status = "okay";
+	};
+
+	iommu@fdbdf000 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdbdf000 0x00 0x40 0x00 0xfdbdf040 0x00 0x40>;
+		interrupts = <0x00 0x63 0x04 0x00 0x64 0x04>;
+		interrupt-names = "irq_rkvenc0_mmu0\0irq_rkvenc0_mmu1";
+		clocks = <0x02 0x1c5 0x02 0x1c4>;
+		clock-names = "aclk\0iface";
+		rockchip,disable-mmu-reset;
+		rockchip,enable-cmd-retry;
+		rockchip,shootdown-entire;
+		#iommu-cells = <0x00>;
+		power-domains = <0x4b 0x10>;
+		status = "okay";
+		phandle = <0xa5>;
+	};
+
+	rkvenc-core@fdbe0000 {
+		compatible = "rockchip,rkv-encoder-v2-core";
+		reg = <0x00 0xfdbe0000 0x00 0x6000>;
+		interrupts = <0x00 0x68 0x04>;
+		interrupt-names = "irq_rkvenc1";
+		clocks = <0x02 0x1ca 0x02 0x1c9 0x02 0x1cb>;
+		clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core";
+		rockchip,normal-rates = <0x23c34600 0x00 0x2faf0800>;
+		assigned-clocks = <0x02 0x1ca 0x02 0x1cb>;
+		assigned-clock-rates = <0x23c34600 0x2faf0800>;
+		resets = <0x02 0x305 0x02 0x304 0x02 0x306>;
+		reset-names = "video_a\0video_h\0video_core";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xa7>;
+		rockchip,srv = <0x9b>;
+		rockchip,ccu = <0xa6>;
+		rockchip,taskqueue-node = <0x07>;
+		rockchip,task-capacity = <0x08>;
+		power-domains = <0x4b 0x11>;
+		status = "okay";
+	};
+
+	iommu@fdbef000 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdbef000 0x00 0x40 0x00 0xfdbef040 0x00 0x40>;
+		interrupts = <0x00 0x66 0x04 0x00 0x67 0x04>;
+		interrupt-names = "irq_rkvenc1_mmu0\0irq_rkvenc1_mmu1";
+		clocks = <0x02 0x1ca 0x02 0x1c9>;
+		lock-names = "aclk\0iface";
+		rockchip,disable-mmu-reset;
+		rockchip,enable-cmd-retry;
+		rockchip,shootdown-entire;
+		#iommu-cells = <0x00>;
+		power-domains = <0x4b 0x11>;
+		status = "okay";
+		phandle = <0xa7>;
+	};
+
+	rkvdec-ccu@fdc30000 {
+		compatible = "rockchip,rkv-decoder-v2-ccu";
+		reg = <0x00 0xfdc30000 0x00 0x100>;
+		reg-names = "ccu";
+		clocks = <0x02 0x18e>;
+		clock-names = "aclk_ccu";
+		assigned-clocks = <0x02 0x18e>;
+		assigned-clock-rates = <0x23c34600>;
+		resets = <0x02 0x282>;
+		reset-names = "video_ccu";
+		rockchip,skip-pmu-idle-request;
+		power-domains = <0x4b 0x0e>;
+		status = "okay";
+		phandle = <0xa9>;
+	};
+
+	rkvdec-core@fdc38000 {
+		compatible = "rockchip,rkv-decoder-v2";
+		reg = <0x00 0xfdc38100 0x00 0x400 0x00 0xfdc38000 0x00 0x100>;
+		reg-names = "regs\0link";
+		interrupts = <0x00 0x5f 0x04>;
+		interrupt-names = "irq_rkvdec0";
+		clocks = <0x02 0x190 0x02 0x18f 0x02 0x193 0x02 0x191 0x02 0x192>;
+		clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core\0clk_cabac\0clk_hevc_cabac";
+		rockchip,normal-rates = <0x2faf0800 0x00 0x23c34600 0x23c34600 0x3b9aca00>;
+		assigned-clocks = <0x02 0x190 0x02 0x193 0x02 0x191 0x02 0x192>;
+		assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>;
+		resets = <0x02 0x284 0x02 0x283 0x02 0x289 0x02 0x287 0x02 0x288>;
+		reset-names = "video_a\0video_h\0video_core\0video_cabac\0video_hevc_cabac";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xa8>;
+		rockchip,srv = <0x9b>;
+		rockchip,ccu = <0xa9>;
+		rockchip,core-mask = <0x10001>;
+		rockchip,taskqueue-node = <0x09>;
+		rockchip,sram = <0xaa>;
+		rockchip,rcb-iova = <0x10000000 0x100000>;
+		rockchip,rcb-min-width = <0x200>;
+		power-domains = <0x4b 0x0e>;
+		status = "okay";
+	};
+
+	iommu@fdc38700 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdc38700 0x00 0x40 0x00 0xfdc38740 0x00 0x40>;
+		interrupts = <0x00 0x60 0x04>;
+		interrupt-names = "irq_rkvdec0_mmu";
+		clocks = <0x02 0x190 0x02 0x18f>;
+		clock-names = "aclk\0iface";
+		rockchip,disable-mmu-reset;
+		rockchip,enable-cmd-retry;
+		rockchip,shootdown-entire;
+		rockchip,master-handle-irq;
+		#iommu-cells = <0x00>;
+		power-domains = <0x4b 0x0e>;
+		status = "okay";
+		phandle = <0xa8>;
+	};
+
+	rkvdec-core@fdc48000 {
+		compatible = "rockchip,rkv-decoder-v2";
+		reg = <0x00 0xfdc48100 0x00 0x400 0x00 0xfdc48000 0x00 0x100>;
+		reg-names = "regs\0link";
+		interrupts = <0x00 0x61 0x04>;
+		interrupt-names = "irq_rkvdec1";
+		clocks = <0x02 0x195 0x02 0x194 0x02 0x198 0x02 0x196 0x02 0x197>;
+		clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core\0clk_cabac\0clk_hevc_cabac";
+		rockchip,normal-rates = <0x2faf0800 0x00 0x23c34600 0x23c34600 0x3b9aca00>;
+		assigned-clocks = <0x02 0x195 0x02 0x198 0x02 0x196 0x02 0x197>;
+		assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>;
+		resets = <0x02 0x293 0x02 0x292 0x02 0x298 0x02 0x296 0x02 0x297>;
+		reset-names = "video_a\0video_h\0video_core\0video_cabac\0video_hevc_cabac";
+		rockchip,skip-pmu-idle-request;
+		iommus = <0xab>;
+		rockchip,srv = <0x9b>;
+		rockchip,ccu = <0xa9>;
+		rockchip,core-mask = <0x20002>;
+		rockchip,taskqueue-node = <0x09>;
+		rockchip,sram = <0xac>;
+		rockchip,rcb-iova = <0x10100000 0x100000>;
+		rockchip,rcb-min-width = <0x200>;
+		power-domains = <0x4b 0x0f>;
+		status = "okay";
+	};
+
+	iommu@fdc48700 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdc48700 0x00 0x40 0x00 0xfdc48740 0x00 0x40>;
+		interrupts = <0x00 0x62 0x04>;
+		interrupt-names = "irq_rkvdec1_mmu";
+		clocks = <0x02 0x195 0x02 0x194>;
+		clock-names = "aclk\0iface";
+		rockchip,disable-mmu-reset;
+		rockchip,enable-cmd-retry;
+		rockchip,shootdown-entire;
+		rockchip,master-handle-irq;
+		#iommu-cells = <0x00>;
+		power-domains = <0x4b 0x0f>;
+		status = "okay";
+		phandle = <0xab>;
+	};
+
+	av1d@fdc70000 {
+		compatible = "rockchip,av1-decoder";
+		reg = <0x00 0xfdc70000 0x00 0x800 0x00 0xfdc80000 0x00 0x400 0x00 0xfdc90000 0x00 0x400>;
+		reg-names = "vcd\0cache\0afbc";
+		interrupts = <0x00 0x6c 0x04 0x00 0x6b 0x04 0x00 0x6a 0x04>;
+		interrupt-names = "irq_av1d\0irq_cache\0irq_afbc";
+		clocks = <0x02 0x49 0x02 0x4b>;
+		clock-names = "aclk_vcodec\0hclk_vcodec";
+		rockchip,normal-rates = <0x17d78400 0x17d78400>;
+		assigned-clocks = <0x02 0x49 0x02 0x4b>;
+		assigned-clock-rates = <0x17d78400 0x17d78400>;
+		resets = <0x02 0x442 0x02 0x445>;
+		reset-names = "video_a\0video_h";
+		iommus = <0xad>;
+		rockchip,srv = <0x9b>;
+		rockchip,taskqueue-node = <0x0b>;
+		power-domains = <0x4b 0x17>;
+		status = "okay";
+	};
+
+	iommu@fdca0000 {
+		compatible = "rockchip,iommu-av1";
+		reg = <0x00 0xfdca0000 0x00 0x600>;
+		interrupts = <0x00 0x6d 0x04>;
+		interrupt-names = "irq_av1d_mmu";
+		clocks = <0x02 0x49 0x02 0x4b>;
+		clock-names = "aclk\0iface";
+		#iommu-cells = <0x00>;
+		power-domains = <0x4b 0x17>;
+		status = "okay";
+		phandle = <0xad>;
+	};
+
+	rkisp-unite@fdcb0000 {
+		compatible = "rockchip,rk3588-rkisp-unite";
+		reg = <0x00 0xfdcb0000 0x00 0x10000 0x00 0xfdcc0000 0x00 0x10000>;
+		interrupts = <0x00 0x87 0x04 0x00 0x89 0x04 0x00 0x8a 0x04>;
+		interrupt-names = "isp_irq\0mi_irq\0mipi_irq";
+		clocks = <0x02 0x1de 0x02 0x1df 0x02 0x1db 0x02 0x1dc 0x02 0x1dd 0x02 0x120 0x02 0x121 0x02 0x11d 0x02 0x11e 0x02 0x11f>;
+		clock-names = "aclk_isp0\0hclk_isp0\0clk_isp_core0\0clk_isp_core_marvin0\0clk_isp_core_vicap0\0aclk_isp1\0hclk_isp1\0clk_isp_core1\0clk_isp_core_marvin1\0clk_isp_core_vicap1";
+		power-domains = <0x4b 0x1c>;
+		iommus = <0xae>;
+		status = "disabled";
+	};
+
+	rkisp@fdcb0000 {
+		compatible = "rockchip,rk3588-rkisp";
+		reg = <0x00 0xfdcb0000 0x00 0x7f00>;
+		interrupts = <0x00 0x83 0x04 0x00 0x85 0x04 0x00 0x86 0x04>;
+		interrupt-names = "isp_irq\0mi_irq\0mipi_irq";
+		clocks = <0x02 0x1de 0x02 0x1df 0x02 0x1db 0x02 0x1dc 0x02 0x1dd>;
+		clock-names = "aclk_isp\0hclk_isp\0clk_isp_core\0clk_isp_core_marvin\0clk_isp_core_vicap";
+		power-domains = <0x4b 0x1b>;
+		iommus = <0xaf>;
+		status = "disabled";
+		phandle = <0x43>;
+	};
+
+	rkisp-unite-mmu@fdcb7f00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdcb7f00 0x00 0x100 0x00 0xfdcc7f00 0x00 0x100>;
+		interrupts = <0x00 0x84 0x04 0x00 0x88 0x04>;
+		interrupt-names = "isp0_mmu\0isp1_mmu";
+		clocks = <0x02 0x1de 0x02 0x1df 0x02 0x120 0x02 0x121>;
+		clock-names = "aclk0\0iface0\0aclk1\0iface1";
+		power-domains = <0x4b 0x1c>;
+		#iommu-cells = <0x00>;
+		rockchip,disable-mmu-reset;
+		status = "disabled";
+		phandle = <0xae>;
+	};
+
+	iommu@fdcb7f00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdcb7f00 0x00 0x100>;
+		interrupts = <0x00 0x84 0x04>;
+		interrupt-names = "isp0_mmu";
+		clocks = <0x02 0x1de 0x02 0x1df>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x4b 0x1b>;
+		#iommu-cells = <0x00>;
+		rockchip,disable-mmu-reset;
+		status = "disabled";
+		phandle = <0xaf>;
+	};
+
+	rkisp@fdcc0000 {
+		compatible = "rockchip,rk3588-rkisp";
+		reg = <0x00 0xfdcc0000 0x00 0x7f00>;
+		interrupts = <0x00 0x87 0x04 0x00 0x89 0x04 0x00 0x8a 0x04>;
+		interrupt-names = "isp_irq\0mi_irq\0mipi_irq";
+		clocks = <0x02 0x120 0x02 0x121 0x02 0x11d 0x02 0x11e 0x02 0x11f>;
+		clock-names = "aclk_isp\0hclk_isp\0clk_isp_core\0clk_isp_core_marvin\0clk_isp_core_vicap";
+		power-domains = <0x4b 0x1c>;
+		iommus = <0xb0>;
+		status = "disabled";
+		phandle = <0x45>;
+	};
+
+	iommu@fdcc7f00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdcc7f00 0x00 0x100>;
+		interrupts = <0x00 0x88 0x04>;
+		interrupt-names = "isp1_mmu";
+		clocks = <0x02 0x120 0x02 0x121>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x4b 0x1c>;
+		#iommu-cells = <0x00>;
+		rockchip,disable-mmu-reset;
+		status = "disabled";
+		phandle = <0xb0>;
+	};
+
+	rkispp@fdcd0000 {
+		compatible = "rockchip,rk3588-rkispp";
+		reg = <0x00 0xfdcd0000 0x00 0xf00>;
+		interrupts = <0x00 0x8b 0x04>;
+		interrupt-names = "fec_irq";
+		clocks = <0x02 0x1d5 0x02 0x1d6 0x02 0x1d7>;
+		clock-names = "aclk_ispp\0hclk_ispp\0clk_ispp";
+		power-domains = <0x4b 0x1d>;
+		iommus = <0xb1>;
+		status = "disabled";
+		phandle = <0x46>;
+	};
+
+	iommu@fdcd0f00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdcd0f00 0x00 0x100>;
+		interrupts = <0x00 0x8c 0x04>;
+		interrupt-names = "fec0_mmu";
+		clocks = <0x02 0x1d5 0x02 0x1d6 0x02 0x1d7>;
+		clock-names = "aclk\0iface\0pclk";
+		power-domains = <0x4b 0x1d>;
+		#iommu-cells = <0x00>;
+		rockchip,disable-mmu-reset;
+		status = "disabled";
+		phandle = <0xb1>;
+	};
+
+	rkispp@fdcd8000 {
+		compatible = "rockchip,rk3588-rkispp";
+		reg = <0x00 0xfdcd8000 0x00 0xf00>;
+		interrupts = <0x00 0x8d 0x04>;
+		interrupt-names = "fec_irq";
+		clocks = <0x02 0x1d8 0x02 0x1d9 0x02 0x1da>;
+		clock-names = "aclk_ispp\0hclk_ispp\0clk_ispp";
+		power-domains = <0x4b 0x1d>;
+		iommus = <0xb2>;
+		status = "disabled";
+		phandle = <0x47>;
+	};
+
+	iommu@fdcd8f00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdcd8f00 0x00 0x100>;
+		interrupts = <0x00 0x8e 0x04>;
+		interrupt-names = "fec1_mmu";
+		clocks = <0x02 0x1d8 0x02 0x1d9 0x02 0x1da>;
+		clock-names = "aclk\0iface\0pclk";
+		power-domains = <0x4b 0x1d>;
+		#iommu-cells = <0x00>;
+		rockchip,disable-mmu-reset;
+		status = "disabled";
+		phandle = <0xb2>;
+	};
+
+	rkcif@fdce0000 {
+		compatible = "rockchip,rk3588-cif";
+		reg = <0x00 0xfdce0000 0x00 0x800>;
+		reg-names = "cif_regs";
+		interrupts = <0x00 0x9b 0x04>;
+		interrupt-names = "cif-intr";
+		clocks = <0x02 0x1e4 0x02 0x1e5 0x02 0x1e3>;
+		clock-names = "aclk_cif\0hclk_cif\0dclk_cif";
+		resets = <0x02 0x317 0x02 0x318 0x02 0x316>;
+		reset-names = "rst_cif_a\0rst_cif_h\0rst_cif_d";
+		assigned-clocks = <0x02 0x1e3>;
+		assigned-clock-rates = <0x23c34600>;
+		power-domains = <0x4b 0x1b>;
+		rockchip,grf = <0xb3>;
+		iommus = <0x3b>;
+		status = "okay";
+		phandle = <0x3a>;
+	};
+
+	iommu@fdce0800 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdce0800 0x00 0x100 0x00 0xfdce0900 0x00 0x100>;
+		interrupts = <0x00 0x71 0x04>;
+		interrupt-names = "cif_mmu";
+		clocks = <0x02 0x1e4 0x02 0x1e5>;
+		clock-names = "aclk\0iface";
+		power-domains = <0x4b 0x1b>;
+		rockchip,disable-mmu-reset;
+		#iommu-cells = <0x00>;
+		status = "okay";
+		phandle = <0x3b>;
+	};
+
+	mipi0-csi2@fdd10000 {
+		compatible = "rockchip,rk3588-mipi-csi2";
+		reg = <0x00 0xfdd10000 0x00 0x10000>;
+		reg-names = "csihost_regs";
+		interrupts = <0x00 0x8f 0x04 0x00 0x90 0x04>;
+		interrupt-names = "csi-intr1\0csi-intr2";
+		clocks = <0x02 0x1cf 0x02 0x1cd>;
+		clock-names = "pclk_csi2host\0iclk_csi2host";
+		resets = <0x02 0x324 0x02 0x334>;
+		reset-names = "srst_csihost_p\0srst_csihost_vicap";
+		status = "disabled";
+	};
+
+	mipi1-csi2@fdd20000 {
+		compatible = "rockchip,rk3588-mipi-csi2";
+		reg = <0x00 0xfdd20000 0x00 0x10000>;
+		reg-names = "csihost_regs";
+		interrupts = <0x00 0x91 0x04 0x00 0x92 0x04>;
+		interrupt-names = "csi-intr1\0csi-intr2";
+		clocks = <0x02 0x1d0 0x02 0x1ce>;
+		clock-names = "pclk_csi2host\0iclk_csi2host";
+		resets = <0x02 0x325 0x02 0x335>;
+		reset-names = "srst_csihost_p\0srst_csihost_vicap";
+		status = "disabled";
+	};
+
+	mipi2-csi2@fdd30000 {
+		compatible = "rockchip,rk3588-mipi-csi2";
+		reg = <0x00 0xfdd30000 0x00 0x10000>;
+		reg-names = "csihost_regs";
+		interrupts = <0x00 0x93 0x04 0x00 0x94 0x04>;
+		interrupt-names = "csi-intr1\0csi-intr2";
+		clocks = <0x02 0x1d1>;
+		clock-names = "pclk_csi2host";
+		resets = <0x02 0x326 0x02 0x336>;
+		reset-names = "srst_csihost_p\0srst_csihost_vicap";
+		status = "okay";
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xb4>;
+					phandle = <0x2c>;
+				};
+			};
+
+			port@1 {
+				reg = <0x01>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xb5>;
+					phandle = <0x3f>;
+				};
+			};
+		};
+	};
+
+	mipi3-csi2@fdd40000 {
+		compatible = "rockchip,rk3588-mipi-csi2";
+		reg = <0x00 0xfdd40000 0x00 0x10000>;
+		reg-names = "csihost_regs";
+		interrupts = <0x00 0x95 0x04 0x00 0x96 0x04>;
+		interrupt-names = "csi-intr1\0csi-intr2";
+		clocks = <0x02 0x1d2>;
+		clock-names = "pclk_csi2host";
+		resets = <0x02 0x327 0x02 0x337>;
+		reset-names = "srst_csihost_p\0srst_csihost_vicap";
+		status = "disabled";
+	};
+
+	vop@fdd90000 {
+		compatible = "rockchip,rk3588-vop";
+		reg = <0x00 0xfdd90000 0x00 0x4200 0x00 0xfdd95000 0x00 0x1000>;
+		reg-names = "regs\0gamma_lut";
+		interrupts = <0x00 0x9c 0x04>;
+		clocks = <0x02 0x270 0x02 0x26f 0x02 0x274 0x02 0x275 0x02 0x276 0x02 0x277 0x02 0x26e 0x02 0x271 0x02 0x272 0x02 0x273 0xb6>;
+		clock-names = "aclk_vop\0hclk_vop\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0pclk_vop\0dclk_src_vp0\0dclk_src_vp1\0dclk_src_vp2\0hdmi0_phy_pll";
+		resets = <0x02 0x349 0x02 0x348 0x02 0x34d 0x02 0x350 0x02 0x351 0x02 0x352>;
+		reset-names = "axi\0ahb\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3";
+		iommus = <0xb7>;
+		power-domains = <0x4b 0x18>;
+		rockchip,grf = <0xb3>;
+		rockchip,vop-grf = <0xb8>;
+		rockchip,vo1-grf = <0xb9>;
+		rockchip,pmu = <0xba>;
+		status = "okay";
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			phandle = <0x2d>;
+
+			port@0 {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				reg = <0x00>;
+				rockchip,plane-mask = <0x05>;
+				rockchip,primary-plane = <0x02>;
+				assigned-clocks = <0x02 0x270>;
+				assigned-clock-rates = <0x2faf0800>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xbb>;
+					phandle = <0xce>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xbc>;
+					phandle = <0xd8>;
+				};
+
+				endpoint@2 {
+					reg = <0x02>;
+					remote-endpoint = <0xbd>;
+					phandle = <0x33>;
+				};
+			};
+
+			port@1 {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				reg = <0x01>;
+				rockchip,plane-mask = <0x0a>;
+				rockchip,primary-plane = <0x03>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xbe>;
+					phandle = <0x2f>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xbf>;
+					phandle = <0xd9>;
+				};
+
+				endpoint@2 {
+					reg = <0x02>;
+					remote-endpoint = <0xc0>;
+					phandle = <0xd5>;
+				};
+			};
+
+			port@2 {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				reg = <0x02>;
+				assigned-clocks = <0x02 0x273>;
+				assigned-clock-parents = <0x02 0x04>;
+				rockchip,plane-mask = <0x140>;
+				rockchip,primary-plane = <0x08>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xc1>;
+					phandle = <0xcf>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xc2>;
+					phandle = <0x32>;
+				};
+
+				endpoint@2 {
+					reg = <0x02>;
+					remote-endpoint = <0xc3>;
+					phandle = <0xd6>;
+				};
+
+				endpoint@3 {
+					reg = <0x03>;
+					remote-endpoint = <0xc4>;
+					phandle = <0xcb>;
+				};
+
+				endpoint@4 {
+					reg = <0x04>;
+					remote-endpoint = <0xc5>;
+					phandle = <0xcc>;
+				};
+			};
+
+			port@3 {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				reg = <0x03>;
+				rockchip,plane-mask = <0x280>;
+				rockchip,primary-plane = <0x09>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xc6>;
+					phandle = <0x30>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xc7>;
+					phandle = <0x31>;
+				};
+
+				endpoint@2 {
+					reg = <0x02>;
+					remote-endpoint = <0xc8>;
+					phandle = <0x34>;
+				};
+			};
+		};
+	};
+
+	iommu@fdd97e00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x00 0xfdd97e00 0x00 0x100 0x00 0xfdd97f00 0x00 0x100>;
+		interrupts = <0x00 0x9c 0x04>;
+		interrupt-names = "vop_mmu";
+		clocks = <0x02 0x270 0x02 0x26f>;
+		clock-names = "aclk\0iface";
+		#iommu-cells = <0x00>;
+		rockchip,disable-device-link-resume;
+		rockchip,shootdown-entire;
+		status = "okay";
+		phandle = <0xb7>;
+	};
+
+	spdif-tx@fddb0000 {
+		compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif";
+		reg = <0x00 0xfddb0000 0x00 0x1000>;
+		interrupts = <0x00 0xc3 0x04>;
+		dmas = <0xc9 0x06>;
+		dma-names = "tx";
+		clock-names = "mclk\0hclk";
+		clocks = <0x02 0x209 0x02 0x204>;
+		assigned-clocks = <0x02 0x205>;
+		assigned-clock-parents = <0x02 0x05>;
+		power-domains = <0x4b 0x19>;
+		#sound-dai-cells = <0x00>;
+		status = "okay";
+		phandle = <0x177>;
+	};
+
+	i2s@fddc0000 {
+		compatible = "rockchip,rk3588-i2s-tdm";
+		reg = <0x00 0xfddc0000 0x00 0x1000>;
+		interrupts = <0x00 0xb8 0x04>;
+		clocks = <0x02 0x1fb 0x02 0x1fb 0x02 0x1f0>;
+		clock-names = "mclk_tx\0mclk_rx\0hclk";
+		assigned-clocks = <0x02 0x1f9>;
+		assigned-clock-parents = <0x02 0x05>;
+		dmas = <0xca 0x00>;
+		dma-names = "tx";
+		power-domains = <0x4b 0x19>;
+		resets = <0x02 0x38d>;
+		reset-names = "tx-m";
+		rockchip,playback-only;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+	};
+
+	spdif-tx@fdde0000 {
+		compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif";
+		reg = <0x00 0xfdde0000 0x00 0x1000>;
+		interrupts = <0x00 0xc4 0x04>;
+		dmas = <0xc9 0x07>;
+		dma-names = "tx";
+		clock-names = "mclk\0hclk";
+		clocks = <0x02 0x257 0x02 0x253>;
+		assigned-clocks = <0x02 0x254>;
+		assigned-clock-parents = <0x02 0x05>;
+		power-domains = <0x4b 0x1a>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+	};
+
+	i2s@fddf0000 {
+		compatible = "rockchip,rk3588-i2s-tdm";
+		reg = <0x00 0xfddf0000 0x00 0x1000>;
+		interrupts = <0x00 0xb9 0x04>;
+		clocks = <0x02 0x246 0x02 0x246 0x02 0x248>;
+		clock-names = "mclk_tx\0mclk_rx\0hclk";
+		assigned-clocks = <0x02 0x243>;
+		assigned-clock-parents = <0x02 0x05>;
+		dmas = <0xca 0x02>;
+		dma-names = "tx";
+		power-domains = <0x4b 0x1a>;
+		resets = <0x02 0x3e8>;
+		reset-names = "tx-m";
+		rockchip,playback-only;
+		#sound-dai-cells = <0x00>;
+		status = "okay";
+		phandle = <0x175>;
+	};
+
+	i2s@fddfc000 {
+		compatible = "rockchip,rk3588-i2s-tdm";
+		reg = <0x00 0xfddfc000 0x00 0x1000>;
+		interrupts = <0x00 0xbd 0x04>;
+		clocks = <0x02 0x242 0x02 0x242 0x02 0x23e>;
+		clock-names = "mclk_tx\0mclk_rx\0hclk";
+		assigned-clocks = <0x02 0x23f>;
+		assigned-clock-parents = <0x02 0x05>;
+		dmas = <0xca 0x17>;
+		dma-names = "rx";
+		power-domains = <0x4b 0x1a>;
+		resets = <0x02 0x413>;
+		reset-names = "rx-m";
+		rockchip,capture-only;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+	};
+
+	spdif-rx@fde08000 {
+		compatible = "rockchip,rk3588-spdifrx\0rockchip,rk3308-spdifrx";
+		reg = <0x00 0xfde08000 0x00 0x1000>;
+		interrupts = <0x00 0xc7 0x04>;
+		clocks = <0x02 0x25e 0x02 0x25d>;
+		clock-names = "mclk\0hclk";
+		assigned-clocks = <0x02 0x25e>;
+		assigned-clock-parents = <0x02 0x05>;
+		dmas = <0x60 0x15>;
+		dma-names = "rx";
+		power-domains = <0x4b 0x1a>;
+		resets = <0x02 0x3fd>;
+		reset-names = "spdifrx-m";
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+	};
+
+	dsi@fde20000 {
+		compatible = "rockchip,rk3588-mipi-dsi2";
+		reg = <0x00 0xfde20000 0x00 0x10000>;
+		interrupts = <0x00 0xa7 0x04>;
+		clocks = <0x02 0x278 0x02 0x27a>;
+		clock-names = "pclk\0sys_clk";
+		resets = <0x02 0x354>;
+		reset-names = "apb";
+		power-domains = <0x4b 0x18>;
+		phys = <0x28>;
+		phy-names = "dcphy";
+		rockchip,grf = <0xb8>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xcb>;
+					status = "disabled";
+					phandle = <0xc4>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0x30>;
+					status = "disabled";
+					phandle = <0xc6>;
+				};
+			};
+		};
+	};
+
+	dsi@fde30000 {
+		compatible = "rockchip,rk3588-mipi-dsi2";
+		reg = <0x00 0xfde30000 0x00 0x10000>;
+		interrupts = <0x00 0xa8 0x04>;
+		clocks = <0x02 0x279 0x02 0x27b>;
+		clock-names = "pclk\0sys_clk";
+		resets = <0x02 0x355>;
+		reset-names = "apb";
+		power-domains = <0x4b 0x18>;
+		phys = <0x29>;
+		phy-names = "dcphy";
+		rockchip,grf = <0xb8>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xcc>;
+					status = "disabled";
+					phandle = <0xc5>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0x31>;
+					status = "disabled";
+					phandle = <0xc7>;
+				};
+			};
+		};
+	};
+
+	dp@fde50000 {
+		compatible = "rockchip,rk3588-dp";
+		reg = <0x00 0xfde50000 0x00 0x4000>;
+		interrupts = <0x00 0xa1 0x04>;
+		clocks = <0x02 0x1e6 0x02 0x2cc 0x02 0x1fb 0x02 0x207 0x04>;
+		clock-names = "apb\0aux\0i2s\0spdif\0hclk";
+		assigned-clocks = <0x02 0x2cc>;
+		assigned-clock-rates = <0xf42400>;
+		resets = <0x02 0x388>;
+		phys = <0xcd>;
+		power-domains = <0x4b 0x19>;
+		#sound-dai-cells = <0x01>;
+		status = "okay";
+		phandle = <0x178>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xce>;
+					status = "disabled";
+					phandle = <0xbb>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0x2f>;
+					status = "disabled";
+					phandle = <0xbe>;
+				};
+
+				endpoint@2 {
+					reg = <0x02>;
+					remote-endpoint = <0xcf>;
+					status = "okay";
+					phandle = <0xc1>;
+				};
+			};
+		};
+	};
+
+	hdmi@fde80000 {
+		compatible = "rockchip,rk3588-dw-hdmi";
+		reg = <0x00 0xfde80000 0x00 0x20000>;
+		interrupts = <0x00 0xa9 0x04 0x00 0xaa 0x04 0x00 0xab 0x04 0x00 0xac 0x04 0x00 0x168 0x04>;
+		clocks = <0x02 0x221 0x02 0x265 0x02 0x222 0x02 0x223 0x02 0x246 0x02 0x274 0x02 0x275 0x02 0x276 0x02 0x277 0x05>;
+		clock-names = "pclk\0hpd\0earc\0hdmitx_ref\0aud\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0hclk_vo1";
+		resets = <0x02 0x3d0 0x02 0x49c>;
+		reset-names = "ref\0hdp";
+		power-domains = <0x4b 0x1a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0xd0 0xd1 0xd2 0xd3>;
+		reg-io-width = <0x04>;
+		rockchip,grf = <0xb3>;
+		rockchip,vo1_grf = <0xb9>;
+		phys = <0xb6>;
+		phy-names = "hdmi";
+		#sound-dai-cells = <0x00>;
+		status = "okay";
+		enable-gpios = <0xd4 0x0a 0x00>;
+		phandle = <0x176>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0x33>;
+					status = "okay";
+					phandle = <0xbd>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xd5>;
+					status = "disabled";
+					phandle = <0xc0>;
+				};
+
+				endpoint@2 {
+					reg = <0x02>;
+					remote-endpoint = <0xd6>;
+					status = "disabled";
+					phandle = <0xc3>;
+				};
+			};
+		};
+	};
+
+	edp@fdec0000 {
+		compatible = "rockchip,rk3588-edp";
+		reg = <0x00 0xfdec0000 0x00 0x1000>;
+		interrupts = <0x00 0xa3 0x04>;
+		clocks = <0x02 0x211 0x02 0x210 0x02 0x212 0x05>;
+		clock-names = "dp\0pclk\0spdif\0hclk";
+		resets = <0x02 0x3e1 0x02 0x3e0>;
+		reset-names = "dp\0apb";
+		phys = <0xd7>;
+		phy-names = "dp";
+		power-domains = <0x4b 0x1a>;
+		rockchip,grf = <0xb9>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@0 {
+					reg = <0x00>;
+					remote-endpoint = <0xd8>;
+					status = "disabled";
+					phandle = <0xbc>;
+				};
+
+				endpoint@1 {
+					reg = <0x01>;
+					remote-endpoint = <0xd9>;
+					status = "disabled";
+					phandle = <0xbf>;
+				};
+
+				endpoint@2 {
+					reg = <0x02>;
+					remote-endpoint = <0x32>;
+					status = "disabled";
+					phandle = <0xc2>;
+				};
+			};
+		};
+	};
+
+	qos@fdf35000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf35000 0x00 0x20>;
+		phandle = <0x6b>;
+	};
+
+	qos@fdf35200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf35200 0x00 0x20>;
+		phandle = <0x6c>;
+	};
+
+	qos@fdf35400 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf35400 0x00 0x20>;
+		phandle = <0x6d>;
+	};
+
+	qos@fdf35600 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf35600 0x00 0x20>;
+		phandle = <0x6e>;
+	};
+
+	qos@fdf36000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf36000 0x00 0x20>;
+		phandle = <0x8e>;
+	};
+
+	qos@fdf39000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf39000 0x00 0x20>;
+		phandle = <0x93>;
+	};
+
+	qos@fdf3d800 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf3d800 0x00 0x20>;
+		phandle = <0x94>;
+	};
+
+	qos@fdf3e000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf3e000 0x00 0x20>;
+		phandle = <0x90>;
+	};
+
+	qos@fdf3e200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf3e200 0x00 0x20>;
+		phandle = <0x8f>;
+	};
+
+	qos@fdf3e400 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf3e400 0x00 0x20>;
+		phandle = <0x91>;
+	};
+
+	qos@fdf3e600 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf3e600 0x00 0x20>;
+		phandle = <0x92>;
+	};
+
+	qos@fdf40000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf40000 0x00 0x20>;
+		phandle = <0x8c>;
+	};
+
+	qos@fdf40200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf40200 0x00 0x20>;
+		phandle = <0x8d>;
+	};
+
+	qos@fdf40400 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf40400 0x00 0x20>;
+		phandle = <0x86>;
+	};
+
+	qos@fdf40500 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf40500 0x00 0x20>;
+		phandle = <0x87>;
+	};
+
+	qos@fdf40600 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf40600 0x00 0x20>;
+		phandle = <0x88>;
+	};
+
+	qos@fdf40800 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf40800 0x00 0x20>;
+		phandle = <0x89>;
+	};
+
+	qos@fdf41000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf41000 0x00 0x20>;
+		phandle = <0x8a>;
+	};
+
+	qos@fdf41100 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf41100 0x00 0x20>;
+		phandle = <0x8b>;
+	};
+
+	qos@fdf60000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf60000 0x00 0x20>;
+		phandle = <0x71>;
+	};
+
+	qos@fdf60200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf60200 0x00 0x20>;
+		phandle = <0x72>;
+	};
+
+	qos@fdf60400 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf60400 0x00 0x20>;
+		phandle = <0x73>;
+	};
+
+	qos@fdf61000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf61000 0x00 0x20>;
+		phandle = <0x74>;
+	};
+
+	qos@fdf61200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf61200 0x00 0x20>;
+		phandle = <0x75>;
+	};
+
+	qos@fdf61400 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf61400 0x00 0x20>;
+		phandle = <0x76>;
+	};
+
+	qos@fdf62000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf62000 0x00 0x20>;
+		phandle = <0x6f>;
+	};
+
+	qos@fdf63000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf63000 0x00 0x20>;
+		phandle = <0x70>;
+	};
+
+	qos@fdf64000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf64000 0x00 0x20>;
+		phandle = <0x7f>;
+	};
+
+	qos@fdf66000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf66000 0x00 0x20>;
+		phandle = <0x77>;
+	};
+
+	qos@fdf66200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf66200 0x00 0x20>;
+		phandle = <0x78>;
+	};
+
+	qos@fdf66400 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf66400 0x00 0x20>;
+		phandle = <0x79>;
+	};
+
+	qos@fdf66600 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf66600 0x00 0x20>;
+		phandle = <0x7a>;
+	};
+
+	qos@fdf66800 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf66800 0x00 0x20>;
+		phandle = <0x7b>;
+	};
+
+	qos@fdf66a00 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf66a00 0x00 0x20>;
+		phandle = <0x7c>;
+	};
+
+	qos@fdf66c00 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf66c00 0x00 0x20>;
+		phandle = <0x7d>;
+	};
+
+	qos@fdf66e00 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf66e00 0x00 0x20>;
+		phandle = <0x7e>;
+	};
+
+	qos@fdf67000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf67000 0x00 0x20>;
+		phandle = <0x80>;
+	};
+
+	qos@fdf67200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf67200 0x00 0x20>;
+	};
+
+	qos@fdf70000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf70000 0x00 0x20>;
+		phandle = <0x69>;
+	};
+
+	qos@fdf71000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf71000 0x00 0x20>;
+		phandle = <0x6a>;
+	};
+
+	qos@fdf72000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf72000 0x00 0x20>;
+		phandle = <0x66>;
+	};
+
+	qos@fdf72200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf72200 0x00 0x20>;
+		phandle = <0x67>;
+	};
+
+	qos@fdf72400 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf72400 0x00 0x20>;
+		phandle = <0x68>;
+	};
+
+	qos@fdf80000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf80000 0x00 0x20>;
+		phandle = <0x83>;
+	};
+
+	qos@fdf81000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf81000 0x00 0x20>;
+		phandle = <0x84>;
+	};
+
+	qos@fdf81200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf81200 0x00 0x20>;
+		phandle = <0x85>;
+	};
+
+	qos@fdf82000 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf82000 0x00 0x20>;
+		phandle = <0x81>;
+	};
+
+	qos@fdf82200 {
+		compatible = "syscon";
+		reg = <0x00 0xfdf82200 0x00 0x20>;
+		phandle = <0x82>;
+	};
+
+	dfi@fe060000 {
+		reg = <0x00 0xfe060000 0x00 0x10000>;
+		compatible = "rockchip,rk3588-dfi";
+		rockchip,pmu_grf = <0xda>;
+		status = "okay";
+		phandle = <0x35>;
+	};
+
+	pcie@fe180000 {
+		compatible = "rockchip,rk3588-pcie\0snps,dw-pcie";
+		#address-cells = <0x03>;
+		#size-cells = <0x02>;
+		bus-range = <0x30 0x3f>;
+		clocks = <0x02 0x151 0x02 0x156 0x02 0x14c 0x02 0x15c 0x02 0x161 0x02 0x2c5>;
+		clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe";
+		device_type = "pci";
+		interrupts = <0x00 0xf8 0x04 0x00 0xf7 0x04 0x00 0xf6 0x04 0x00 0xf5 0x04 0x00 0xf4 0x04>;
+		interrupt-names = "sys\0pmc\0msg\0legacy\0err";
+		#interrupt-cells = <0x01>;
+		interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+		interrupt-map = <0x00 0x00 0x00 0x01 0xdb 0x00 0x00 0x00 0x00 0x02 0xdb 0x01 0x00 0x00 0x00 0x03 0xdb 0x02 0x00 0x00 0x00 0x04 0xdb 0x03>;
+		linux,pci-domain = <0x03>;
+		num-ib-windows = <0x08>;
+		num-ob-windows = <0x08>;
+		num-viewport = <0x04>;
+		max-link-speed = <0x02>;
+		msi-map = <0x3000 0xdc 0x3000 0x1000>;
+		num-lanes = <0x01>;
+		phys = <0x57 0x02>;
+		phy-names = "pcie-phy";
+		ranges = <0x800 0x00 0xf3000000 0x00 0xf3000000 0x00 0x100000 0x81000000 0x00 0xf3100000 0x00 0xf3100000 0x00 0x100000 0x82000000 0x00 0xf3200000 0x00 0xf3200000 0x00 0xe00000 0xc3000000 0x09 0xc0000000 0x09 0xc0000000 0x00 0x40000000>;
+		reg = <0x00 0xfe180000 0x00 0x10000 0x0a 0x40c00000 0x00 0x400000>;
+		reg-names = "pcie-apb\0pcie-dbi";
+		resets = <0x02 0x210 0x02 0x21f>;
+		reset-names = "pcie\0periph";
+		rockchip,pipe-grf = <0x5d>;
+		status = "disabled";
+
+		legacy-interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0x00>;
+			#interrupt-cells = <0x01>;
+			interrupt-parent = <0x01>;
+			interrupts = <0x00 0xf5 0x01>;
+			phandle = <0xdb>;
+		};
+	};
+
+	pcie@fe190000 {
+		compatible = "rockchip,rk3588-pcie\0snps,dw-pcie";
+		#address-cells = <0x03>;
+		#size-cells = <0x02>;
+		bus-range = <0x40 0x4f>;
+		clocks = <0x02 0x152 0x02 0x157 0x02 0x14d 0x02 0x15d 0x02 0x162 0x02 0x182>;
+		clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe";
+		device_type = "pci";
+		interrupts = <0x00 0xfd 0x04 0x00 0xfc 0x04 0x00 0xfb 0x04 0x00 0xfa 0x04 0x00 0xf9 0x04>;
+		interrupt-names = "sys\0pmc\0msg\0legacy\0err";
+		#interrupt-cells = <0x01>;
+		interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+		interrupt-map = <0x00 0x00 0x00 0x01 0xdd 0x00 0x00 0x00 0x00 0x02 0xdd 0x01 0x00 0x00 0x00 0x03 0xdd 0x02 0x00 0x00 0x00 0x04 0xdd 0x03>;
+		linux,pci-domain = <0x04>;
+		num-ib-windows = <0x08>;
+		num-ob-windows = <0x08>;
+		num-viewport = <0x04>;
+		max-link-speed = <0x02>;
+		msi-map = <0x4000 0xdc 0x4000 0x1000>;
+		num-lanes = <0x01>;
+		phys = <0xde 0x02>;
+		phy-names = "pcie-phy";
+		ranges = <0x800 0x00 0xf4000000 0x00 0xf4000000 0x00 0x100000 0x81000000 0x00 0xf4100000 0x00 0xf4100000 0x00 0x100000 0x82000000 0x00 0xf4200000 0x00 0xf4200000 0x00 0xe00000 0xc3000000 0x0a 0x00 0x0a 0x00 0x00 0x40000000>;
+		reg = <0x00 0xfe190000 0x00 0x10000 0x0a 0x41000000 0x00 0x400000>;
+		reg-names = "pcie-apb\0pcie-dbi";
+		resets = <0x02 0x211 0x02 0x220>;
+		reset-names = "pcie\0periph";
+		rockchip,pipe-grf = <0x5d>;
+		status = "disabled";
+
+		legacy-interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0x00>;
+			#interrupt-cells = <0x01>;
+			interrupt-parent = <0x01>;
+			interrupts = <0x00 0xfa 0x01>;
+			phandle = <0xdd>;
+		};
+	};
+
+	ethernet@fe1b0000 {
+		compatible = "rockchip,rk3588-gmac\0snps,dwmac-4.20a";
+		reg = <0x00 0xfe1b0000 0x00 0x10000>;
+		interrupts = <0x00 0xe3 0x04 0x00 0xe2 0x04>;
+		interrupt-names = "macirq\0eth_wake_irq";
+		rockchip,grf = <0xb3>;
+		rockchip,php_grf = <0x5d>;
+		clocks = <0x02 0x144 0x02 0x145 0x02 0x167 0x02 0x16c 0x02 0x142>;
+		clock-names = "stmmaceth\0clk_mac_ref\0pclk_mac\0aclk_mac\0ptp_ref";
+		resets = <0x02 0x20a>;
+		reset-names = "stmmaceth";
+		power-domains = <0x4b 0x21>;
+		snps,mixed-burst;
+		snps,tso;
+		snps,axi-config = <0xdf>;
+		snps,mtl-rx-config = <0xe0>;
+		snps,mtl-tx-config = <0xe1>;
+		status = "disabled";
+
+		mdio {
+			compatible = "snps,dwmac-mdio";
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+		};
+
+		stmmac-axi-config {
+			snps,wr_osr_lmt = <0x04>;
+			snps,rd_osr_lmt = <0x08>;
+			snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+			phandle = <0xdf>;
+		};
+
+		rx-queues-config {
+			snps,rx-queues-to-use = <0x02>;
+			phandle = <0xe0>;
+
+			queue0 {
+			};
+
+			queue1 {
+			};
+		};
+
+		tx-queues-config {
+			snps,tx-queues-to-use = <0x02>;
+			phandle = <0xe1>;
+
+			queue0 {
+			};
+
+			queue1 {
+			};
+		};
+	};
+
+	ethernet@fe1c0000 {
+		compatible = "rockchip,rk3588-gmac\0snps,dwmac-4.20a";
+		reg = <0x00 0xfe1c0000 0x00 0x10000>;
+		interrupts = <0x00 0xea 0x04 0x00 0xe9 0x04>;
+		interrupt-names = "macirq\0eth_wake_irq";
+		rockchip,grf = <0xb3>;
+		rockchip,php_grf = <0x5d>;
+		clocks = <0x02 0x144 0x02 0x145 0x02 0x168 0x02 0x16d 0x02 0x143>;
+		clock-names = "stmmaceth\0clk_mac_ref\0pclk_mac\0aclk_mac\0ptp_ref";
+		resets = <0x02 0x20b>;
+		reset-names = "stmmaceth";
+		power-domains = <0x4b 0x21>;
+		snps,mixed-burst;
+		snps,tso;
+		snps,axi-config = <0xe2>;
+		snps,mtl-rx-config = <0xe3>;
+		snps,mtl-tx-config = <0xe4>;
+		status = "okay";
+		phy-mode = "rgmii-rxid";
+		clock_in_out = "output";
+		snps,reset-gpio = <0xe5 0x1b 0x01>;
+		snps,reset-active-low;
+		snps,reset-delays-us = <0x00 0x4e20 0x186a0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0xe6 0xe7 0xe8 0xe9 0xea>;
+		tx_delay = <0x43>;
+		phy-handle = <0xeb>;
+
+		mdio {
+			compatible = "snps,dwmac-mdio";
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			phy@1 {
+				compatible = "ethernet-phy-ieee802.3-c22";
+				reg = <0x01>;
+				phandle = <0xeb>;
+			};
+		};
+
+		stmmac-axi-config {
+			snps,wr_osr_lmt = <0x04>;
+			snps,rd_osr_lmt = <0x08>;
+			snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+			phandle = <0xe2>;
+		};
+
+		rx-queues-config {
+			snps,rx-queues-to-use = <0x02>;
+			phandle = <0xe3>;
+
+			queue0 {
+			};
+
+			queue1 {
+			};
+		};
+
+		tx-queues-config {
+			snps,tx-queues-to-use = <0x02>;
+			phandle = <0xe4>;
+
+			queue0 {
+			};
+
+			queue1 {
+			};
+		};
+	};
+
+	sata@fe210000 {
+		compatible = "rockchip,rk-ahci\0snps,dwc-ahci";
+		reg = <0x00 0xfe210000 0x00 0x1000>;
+		clocks = <0x02 0x171 0x02 0x16e 0x02 0x174 0x02 0x163 0x02 0x17e>;
+		clock-names = "sata\0pmalive\0rxoob\0ref\0asic";
+		interrupts = <0x00 0x111 0x04>;
+		interrupt-names = "hostc";
+		phys = <0xde 0x01>;
+		phy-names = "sata-phy";
+		ports-implemented = <0x01>;
+		status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <0xec>;
+	};
+
+	sata@fe230000 {
+		compatible = "rockchip,rk-ahci\0snps,dwc-ahci";
+		reg = <0x00 0xfe230000 0x00 0x1000>;
+		clocks = <0x02 0x173 0x02 0x170 0x02 0x176 0x02 0x165 0x02 0x180>;
+		clock-names = "sata\0pmalive\0rxoob\0ref\0asic";
+		interrupts = <0x00 0x113 0x04>;
+		interrupt-names = "hostc";
+		phys = <0x57 0x01>;
+		phy-names = "sata-phy";
+		ports-implemented = <0x01>;
+		status = "disabled";
+	};
+
+	spi@fe2b0000 {
+		compatible = "rockchip,sfc";
+		reg = <0x00 0xfe2b0000 0x00 0x4000>;
+		interrupts = <0x00 0xce 0x04>;
+		clocks = <0x02 0x13d 0x02 0x13e>;
+		clock-names = "clk_sfc\0hclk_sfc";
+		assigned-clocks = <0x02 0x13d>;
+		assigned-clock-rates = <0x5f5e100>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+	};
+
+	mmc@fe2c0000 {
+		compatible = "rockchip,rk3588-dw-mshc\0rockchip,rk3288-dw-mshc";
+		reg = <0x00 0xfe2c0000 0x00 0x4000>;
+		interrupts = <0x00 0xcb 0x04>;
+		clocks = <0x0e 0x17 0x0e 0x09 0x02 0x2c2 0x02 0x2c3>;
+		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
+		fifo-depth = <0x100>;
+		max-frequency = <0x8f0d180>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0xed 0xee 0xef 0xf0>;
+		power-domains = <0x4b 0x28>;
+		status = "okay";
+		no-sdio;
+		no-mmc;
+		bus-width = <0x04>;
+		cap-mmc-highspeed;
+		cap-sd-highspeed;
+		disable-wp;
+		sd-uhs-sdr104;
+		vqmmc-supply = <0xf1>;
+		vmmc-supply = <0xf2>;
+	};
+
+	mmc@fe2d0000 {
+		compatible = "rockchip,rk3588-dw-mshc\0rockchip,rk3288-dw-mshc";
+		reg = <0x00 0xfe2d0000 0x00 0x4000>;
+		interrupts = <0x00 0xcc 0x04>;
+		clocks = <0x02 0x199 0x02 0x19a 0x02 0x2c0 0x02 0x2c1>;
+		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
+		fifo-depth = <0x100>;
+		max-frequency = <0xbebc200>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0xf3>;
+		power-domains = <0x4b 0x25>;
+		status = "disabled";
+	};
+
+	mmc@fe2e0000 {
+		compatible = "rockchip,rk3588-dwcmshc\0rockchip,dwcmshc-sdhci";
+		reg = <0x00 0xfe2e0000 0x00 0x10000>;
+		interrupts = <0x00 0xcd 0x04>;
+		assigned-clocks = <0x02 0x13b 0x02 0x13c 0x02 0x13a>;
+		assigned-clock-rates = <0xbebc200 0x16e3600 0xbebc200>;
+		clocks = <0x02 0x13a 0x02 0x138 0x02 0x139 0x02 0x13b 0x02 0x13c>;
+		clock-names = "core\0bus\0axi\0block\0timer";
+		resets = <0x02 0x1f6 0x02 0x1f4 0x02 0x1f5 0x02 0x1f7 0x02 0x1f8>;
+		reset-names = "core\0bus\0axi\0block\0timer";
+		max-frequency = <0xbebc200>;
+		status = "okay";
+		bus-width = <0x08>;
+		no-sdio;
+		no-sd;
+		non-removable;
+		mmc-hs400-1_8v;
+		mmc-hs400-enhanced-strobe;
+	};
+
+	crypto@fe370000 {
+		compatible = "rockchip,rk3588-crypto";
+		reg = <0x00 0xfe370000 0x00 0x2000>;
+		interrupts = <0x00 0xd1 0x04>;
+		clocks = <0x0e 0x0b 0x0e 0x0c 0x0e 0x14 0x0e 0x15>;
+		clock-names = "aclk\0hclk\0sclk\0pka";
+		resets = <0xf4 0x0f>;
+		reset-names = "crypto-rst";
+		status = "disabled";
+	};
+
+	rng@fe378000 {
+		compatible = "rockchip,trngv1";
+		reg = <0x00 0xfe378000 0x00 0x200>;
+		interrupts = <0x00 0x190 0x04>;
+		clocks = <0x0e 0x0c>;
+		clock-names = "hclk_trng";
+		resets = <0xf4 0x30>;
+		reset-names = "reset";
+		status = "okay";
+	};
+
+	i2s@fe470000 {
+		compatible = "rockchip,rk3588-i2s-tdm";
+		reg = <0x00 0xfe470000 0x00 0x1000>;
+		interrupts = <0x00 0xb4 0x04>;
+		clocks = <0x02 0x33 0x02 0x37 0x02 0x30>;
+		clock-names = "mclk_tx\0mclk_rx\0hclk";
+		assigned-clocks = <0x02 0x31 0x02 0x35>;
+		assigned-clock-parents = <0x02 0x05 0x02 0x05>;
+		dmas = <0x60 0x00 0x60 0x01>;
+		dma-names = "tx\0rx";
+		power-domains = <0x4b 0x26>;
+		resets = <0x02 0x77 0x02 0x7a>;
+		reset-names = "tx-m\0rx-m";
+		rockchip,clk-trcm = <0x01>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0xf5 0xf6 0xf7 0xf8>;
+		#sound-dai-cells = <0x00>;
+		status = "okay";
+		phandle = <0x17c>;
+	};
+
+	i2s@fe480000 {
+		compatible = "rockchip,rk3588-i2s-tdm";
+		reg = <0x00 0xfe480000 0x00 0x1000>;
+		interrupts = <0x00 0xb5 0x04>;
+		clocks = <0x02 0x28c 0x02 0x290 0x02 0x288>;
+		clock-names = "mclk_tx\0mclk_rx\0hclk";
+		dmas = <0x60 0x02 0x60 0x03>;
+		dma-names = "tx\0rx";
+		resets = <0x02 0xc002a 0x02 0xc002d>;
+		reset-names = "tx-m\0rx-m";
+		rockchip,clk-trcm = <0x01>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x100 0x101 0x102>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+	};
+
+	i2s@fe490000 {
+		compatible = "rockchip,rk3588-i2s\0rockchip,rk3066-i2s";
+		reg = <0x00 0xfe490000 0x00 0x1000>;
+		interrupts = <0x00 0xb6 0x04>;
+		clocks = <0x02 0x27 0x02 0x22>;
+		clock-names = "i2s_clk\0i2s_hclk";
+		assigned-clocks = <0x02 0x24>;
+		assigned-clock-parents = <0x02 0x05>;
+		dmas = <0xc9 0x00 0xc9 0x01>;
+		dma-names = "tx\0rx";
+		power-domains = <0x4b 0x26>;
+		rockchip,clk-trcm = <0x01>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x103 0x104 0x105 0x106>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+	};
+
+	i2s@fe4a0000 {
+		compatible = "rockchip,rk3588-i2s\0rockchip,rk3066-i2s";
+		reg = <0x00 0xfe4a0000 0x00 0x1000>;
+		interrupts = <0x00 0xb7 0x04>;
+		clocks = <0x02 0x2d 0x02 0x23>;
+		clock-names = "i2s_clk\0i2s_hclk";
+		assigned-clocks = <0x02 0x2a>;
+		assigned-clock-parents = <0x02 0x05>;
+		dmas = <0xc9 0x02 0xc9 0x03>;
+		dma-names = "tx\0rx";
+		power-domains = <0x4b 0x26>;
+		rockchip,clk-trcm = <0x01>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x107 0x108 0x109 0x10a>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+	};
+
+	pdm@fe4b0000 {
+		compatible = "rockchip,rk3588-pdm";
+		reg = <0x00 0xfe4b0000 0x00 0x1000>;
+		clocks = <0x02 0x29f 0x02 0x29e>;
+		clock-names = "pdm_clk\0pdm_hclk";
+		dmas = <0x60 0x04>;
+		dma-names = "rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x10b 0x10c 0x10d 0x10e 0x10f 0x110>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+	};
+
+	pdm@fe4c0000 {
+		compatible = "rockchip,rk3588-pdm";
+		reg = <0x00 0xfe4c0000 0x00 0x1000>;
+		clocks = <0x02 0x3b 0x02 0x3a>;
+		clock-names = "pdm_clk\0pdm_hclk";
+		assigned-clocks = <0x02 0x3b>;
+		assigned-clock-parents = <0x02 0x05>;
+		dmas = <0xc9 0x04>;
+		dma-names = "rx";
+		power-domains = <0x4b 0x26>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x111 0x112 0x113 0x114 0x115 0x116>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+	};
+
+	vad@fe4d0000 {
+		compatible = "rockchip,rk3588-vad";
+		reg = <0x00 0xfe4d0000 0x00 0x1000>;
+		reg-names = "vad";
+		clocks = <0x02 0x2a0>;
+		clock-names = "hclk";
+		interrupts = <0x00 0xca 0x04>;
+		rockchip,audio-src = <0x00>;
+		rockchip,det-channel = <0x00>;
+		rockchip,mode = <0x00>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+	};
+
+	spdif-tx@fe4e0000 {
+		compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif";
+		reg = <0x00 0xfe4e0000 0x00 0x1000>;
+		interrupts = <0x00 0xc1 0x04>;
+		dmas = <0x60 0x05>;
+		dma-names = "tx";
+		clock-names = "mclk\0hclk";
+		clocks = <0x02 0x41 0x02 0x3e>;
+		assigned-clocks = <0x02 0x3f>;
+		assigned-clock-parents = <0x02 0x05>;
+		power-domains = <0x4b 0x26>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x117>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+	};
+
+	spdif-tx@fe4f0000 {
+		compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif";
+		reg = <0x00 0xfe4f0000 0x00 0x1000>;
+		interrupts = <0x00 0xc2 0x04>;
+		dmas = <0xc9 0x05>;
+		dma-names = "tx";
+		clock-names = "mclk\0hclk";
+		clocks = <0x02 0x47 0x02 0x44>;
+		assigned-clocks = <0x02 0x45>;
+		assigned-clock-parents = <0x02 0x05>;
+		power-domains = <0x4b 0x26>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x118>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x179>;
+	};
+
+	codec-digital@fe500000 {
+		compatible = "rockchip,rk3588-codec-digital\0rockchip,codec-digital-v1";
+		reg = <0x00 0xfe500000 0x00 0x1000>;
+		clocks = <0x02 0x29 0x02 0x2f>;
+		clock-names = "dac\0pclk";
+		power-domains = <0x4b 0x26>;
+		resets = <0x02 0x84>;
+		reset-names = "reset";
+		rockchip,grf = <0xb3>;
+		rockchip,pwm-output-mode;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x119>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+	};
+
+	hwspinlock@fe5a0000 {
+		compatible = "rockchip,hwspinlock";
+		reg = <0x00 0xfe5a0000 0x00 0x100>;
+		#hwlock-cells = <0x01>;
+	};
+
+	interrupt-controller@fe600000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <0x03>;
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+		interrupt-controller;
+		reg = <0x00 0xfe600000 0x00 0x10000 0x00 0xfe680000 0x00 0x100000>;
+		interrupts = <0x01 0x09 0x04>;
+		phandle = <0x01>;
+
+		msi-controller@fe640000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <0x01>;
+			reg = <0x00 0xfe640000 0x00 0x20000>;
+			phandle = <0xdc>;
+		};
+
+		msi-controller@fe660000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <0x01>;
+			reg = <0x00 0xfe660000 0x00 0x20000>;
+		};
+	};
+
+	dma-controller@fea10000 {
+		compatible = "arm,pl330\0arm,primecell";
+		reg = <0x00 0xfea10000 0x00 0x4000>;
+		interrupts = <0x00 0x56 0x04 0x00 0x57 0x04>;
+		clocks = <0x02 0x78>;
+		clock-names = "apb_pclk";
+		#dma-cells = <0x01>;
+		arm,pl330-periph-burst;
+		phandle = <0x60>;
+	};
+
+	dma-controller@fea30000 {
+		compatible = "arm,pl330\0arm,primecell";
+		reg = <0x00 0xfea30000 0x00 0x4000>;
+		interrupts = <0x00 0x58 0x04 0x00 0x59 0x04>;
+		clocks = <0x02 0x79>;
+		clock-names = "apb_pclk";
+		#dma-cells = <0x01>;
+		arm,pl330-periph-burst;
+		phandle = <0xc9>;
+	};
+
+	can@fea50000 {
+		compatible = "rockchip,can-2.0";
+		reg = <0x00 0xfea50000 0x00 0x1000>;
+		interrupts = <0x00 0x155 0x04>;
+		clocks = <0x02 0x70 0x02 0x6f>;
+		clock-names = "baudclk\0apb_pclk";
+		resets = <0x02 0xb9 0x02 0xb8>;
+		reset-names = "can\0can-apb";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x11a>;
+		tx-fifo-depth = <0x01>;
+		rx-fifo-depth = <0x06>;
+		status = "disabled";
+	};
+
+	can@fea60000 {
+		compatible = "rockchip,can-2.0";
+		reg = <0x00 0xfea60000 0x00 0x1000>;
+		interrupts = <0x00 0x156 0x04>;
+		clocks = <0x02 0x72 0x02 0x71>;
+		clock-names = "baudclk\0apb_pclk";
+		resets = <0x02 0xbb 0x02 0xba>;
+		reset-names = "can\0can-apb";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x11b>;
+		tx-fifo-depth = <0x01>;
+		rx-fifo-depth = <0x06>;
+		status = "disabled";
+	};
+
+	can@fea70000 {
+		compatible = "rockchip,can-2.0";
+		reg = <0x00 0xfea70000 0x00 0x1000>;
+		interrupts = <0x00 0x157 0x04>;
+		clocks = <0x02 0x74 0x02 0x73>;
+		clock-names = "baudclk\0apb_pclk";
+		resets = <0x02 0xbd 0x02 0xbc>;
+		reset-names = "can\0can-apb";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x11c>;
+		tx-fifo-depth = <0x01>;
+		rx-fifo-depth = <0x06>;
+		status = "disabled";
+	};
+
+	decompress@fea80000 {
+		compatible = "rockchip,hw-decompress";
+		reg = <0x00 0xfea80000 0x00 0x1000>;
+		interrupts = <0x00 0x55 0x04>;
+		clocks = <0x02 0x75 0x02 0x77 0x02 0x76>;
+		clock-names = "aclk\0dclk\0pclk";
+		resets = <0x02 0x118>;
+		reset-names = "dresetn";
+		status = "disabled";
+	};
+
+	i2c@fea90000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfea90000 0x00 0x1000>;
+		clocks = <0x02 0x8d 0x02 0x85>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x13e 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x11d>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+	};
+
+	i2c@feaa0000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfeaa0000 0x00 0x1000>;
+		clocks = <0x02 0x8e 0x02 0x86>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x13f 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x11e>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+		clock-frequency = <0x61a80>;
+
+		rk8602@42 {
+			compatible = "rockchip,rk8602";
+			reg = <0x42>;
+			vin-supply = <0x5f>;
+			regulator-compatible = "rk860x-reg";
+			regulator-name = "vdd_npu_s0";
+			regulator-min-microvolt = <0x86470>;
+			regulator-max-microvolt = <0xe7ef0>;
+			regulator-ramp-delay = <0x8fc>;
+			rockchip,suspend-voltage-selector = <0x01>;
+			regulator-boot-on;
+			regulator-always-on;
+			phandle = <0x97>;
+
+			regulator-state-mem {
+				regulator-off-in-suspend;
+			};
+		};
+
+		fusb302@22 {
+			compatible = "fcs,fusb302";
+			reg = <0x22>;
+			interrupt-parent = <0xe5>;
+			interrupts = <0x14 0x08>;
+			pinctrl-names = "default";
+			pinctrl-0 = <0x11f>;
+			vbus-supply = <0x120>;
+			status = "okay";
+
+			ports {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				port@0 {
+					reg = <0x00>;
+
+					endpoint@0 {
+						remote-endpoint = <0x121>;
+						phandle = <0x52>;
+					};
+				};
+			};
+
+			connector {
+				compatible = "usb-c-connector";
+				label = "USB-C";
+				data-role = "dual";
+				power-role = "dual";
+				try-power-role = "sink";
+				op-sink-microwatt = <0xf4240>;
+				sink-pdos = <0x4019064>;
+				source-pdos = <0x401912c>;
+
+				altmodes {
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+
+					altmode@0 {
+						reg = <0x00>;
+						svid = <0xff01>;
+						vdo = <0xffffffff>;
+					};
+				};
+
+				ports {
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+
+					port@0 {
+						reg = <0x00>;
+
+						endpoint {
+							remote-endpoint = <0x122>;
+							phandle = <0x15f>;
+						};
+					};
+
+					port@1 {
+						reg = <0x01>;
+
+						endpoint {
+							remote-endpoint = <0x123>;
+							phandle = <0x160>;
+						};
+					};
+				};
+			};
+		};
+
+		hym8563@51 {
+			compatible = "haoyu,hym8563";
+			reg = <0x51>;
+			#clock-cells = <0x00>;
+			clock-frequency = <0x8000>;
+			clock-output-names = "hym8563";
+			pinctrl-names = "default";
+			pinctrl-0 = <0x124>;
+			interrupt-parent = <0xe5>;
+			interrupts = <0x08 0x08>;
+			wakeup-source;
+			status = "okay";
+		};
+	};
+
+	i2c@feab0000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfeab0000 0x00 0x1000>;
+		clocks = <0x02 0x8f 0x02 0x87>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x140 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x125>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+
+		es8388@11 {
+			status = "okay";
+			#sound-dai-cells = <0x00>;
+			compatible = "everest,es8388\0everest,es8323";
+			reg = <0x11>;
+			clocks = <0x02 0x39>;
+			clock-names = "mclk";
+			assigned-clocks = <0x02 0x39>;
+			assigned-clock-rates = <0xbb8000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <0x126>;
+			phandle = <0x17d>;
+		};
+	};
+
+	i2c@feac0000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfeac0000 0x00 0x1000>;
+		clocks = <0x02 0x90 0x02 0x88>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x141 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x127>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+	};
+
+	i2c@fead0000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfead0000 0x00 0x1000>;
+		clocks = <0x02 0x91 0x02 0x89>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x142 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x128>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+	};
+
+	timer@feae0000 {
+		compatible = "rockchip,rk3588-timer\0rockchip,rk3288-timer";
+		reg = <0x00 0xfeae0000 0x00 0x20>;
+		interrupts = <0x00 0x121 0x04>;
+		clocks = <0x02 0x5c 0x02 0x5f>;
+		clock-names = "pclk\0timer";
+	};
+
+	watchdog@feaf0000 {
+		compatible = "snps,dw-wdt";
+		reg = <0x00 0xfeaf0000 0x00 0x100>;
+		clocks = <0x02 0x6c 0x02 0x6b>;
+		clock-names = "tclk\0pclk";
+		interrupts = <0x00 0x13b 0x04>;
+		status = "disabled";
+	};
+
+	spi@feb00000 {
+		compatible = "rockchip,rk3066-spi";
+		reg = <0x00 0xfeb00000 0x00 0x1000>;
+		interrupts = <0x00 0x146 0x04>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		clocks = <0x02 0xa3 0x02 0x9e>;
+		clock-names = "spiclk\0apb_pclk";
+		dmas = <0x60 0x0e 0x60 0x0f>;
+		dma-names = "tx\0rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x129 0x12a 0x12b>;
+		num-cs = <0x02>;
+		status = "disabled";
+	};
+
+	spi@feb10000 {
+		compatible = "rockchip,rk3066-spi";
+		reg = <0x00 0xfeb10000 0x00 0x1000>;
+		interrupts = <0x00 0x147 0x04>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		clocks = <0x02 0xa4 0x02 0x9f>;
+		clock-names = "spiclk\0apb_pclk";
+		dmas = <0x60 0x10 0x60 0x11>;
+		dma-names = "tx\0rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x12c 0x12d>;
+		num-cs = <0x01>;
+		status = "okay";
+	};
+
+	spi@feb20000 {
+		compatible = "rockchip,rk3066-spi";
+		reg = <0x00 0xfeb20000 0x00 0x1000>;
+		interrupts = <0x00 0x148 0x04>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		clocks = <0x02 0xa5 0x02 0xa0>;
+		clock-names = "spiclk\0apb_pclk";
+		dmas = <0xc9 0x0f 0xc9 0x10>;
+		dma-names = "tx\0rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x12e 0x12f>;
+		num-cs = <0x01>;
+		status = "okay";
+		assigned-clocks = <0x02 0xa5>;
+		assigned-clock-rates = <0xbebc200>;
+
+		rk806single@0 {
+			compatible = "rockchip,rk806";
+			spi-max-frequency = <0xf4240>;
+			reg = <0x00>;
+			interrupt-parent = <0xe5>;
+			interrupts = <0x07 0x08>;
+			pinctrl-names = "default\0pmic-power-off";
+			pinctrl-0 = <0x130 0x131 0x132 0x133>;
+			pinctrl-1 = <0x134>;
+			low_voltage_threshold = <0xbb8>;
+			shutdown_voltage_threshold = <0xa8c>;
+			shutdown_temperture_threshold = <0xa0>;
+			hotdie_temperture_threshold = <0x73>;
+			pmic-reset-func = <0x01>;
+			vcc1-supply = <0x5f>;
+			vcc2-supply = <0x5f>;
+			vcc3-supply = <0x5f>;
+			vcc4-supply = <0x5f>;
+			vcc5-supply = <0x5f>;
+			vcc6-supply = <0x5f>;
+			vcc7-supply = <0x5f>;
+			vcc8-supply = <0x5f>;
+			vcc9-supply = <0x5f>;
+			vcc10-supply = <0x5f>;
+			vcc11-supply = <0x135>;
+			vcc12-supply = <0x5f>;
+			vcc13-supply = <0x136>;
+			vcc14-supply = <0x136>;
+			vcca-supply = <0x5f>;
+
+			pwrkey {
+				status = "okay";
+			};
+
+			pinctrl_rk806 {
+				gpio-controller;
+				#gpio-cells = <0x02>;
+
+				rk806_dvs1_null {
+					pins = "gpio_pwrctrl2";
+					function = "pin_fun0";
+					phandle = <0x131>;
+				};
+
+				rk806_dvs1_slp {
+					pins = "gpio_pwrctrl1";
+					function = "pin_fun1";
+				};
+
+				rk806_dvs1_pwrdn {
+					pins = "gpio_pwrctrl1";
+					function = "pin_fun2";
+					phandle = <0x134>;
+				};
+
+				rk806_dvs1_rst {
+					pins = "gpio_pwrctrl1";
+					function = "pin_fun3";
+				};
+
+				rk806_dvs2_null {
+					pins = "gpio_pwrctrl2";
+					function = "pin_fun0";
+					phandle = <0x132>;
+				};
+
+				rk806_dvs2_slp {
+					pins = "gpio_pwrctrl2";
+					function = "pin_fun1";
+				};
+
+				rk806_dvs2_pwrdn {
+					pins = "gpio_pwrctrl2";
+					function = "pin_fun2";
+				};
+
+				rk806_dvs2_rst {
+					pins = "gpio_pwrctrl2";
+					function = "pin_fun3";
+				};
+
+				rk806_dvs2_dvs {
+					pins = "gpio_pwrctrl2";
+					function = "pin_fun4";
+				};
+
+				rk806_dvs2_gpio {
+					pins = "gpio_pwrctrl2";
+					function = "pin_fun5";
+				};
+
+				rk806_dvs3_null {
+					pins = "gpio_pwrctrl3";
+					function = "pin_fun0";
+					phandle = <0x133>;
+				};
+
+				rk806_dvs3_slp {
+					pins = "gpio_pwrctrl3";
+					function = "pin_fun1";
+				};
+
+				rk806_dvs3_pwrdn {
+					pins = "gpio_pwrctrl3";
+					function = "pin_fun2";
+				};
+
+				rk806_dvs3_rst {
+					pins = "gpio_pwrctrl3";
+					function = "pin_fun3";
+				};
+
+				rk806_dvs3_dvs {
+					pins = "gpio_pwrctrl3";
+					function = "pin_fun4";
+				};
+
+				rk806_dvs3_gpio {
+					pins = "gpio_pwrctrl3";
+					function = "pin_fun5";
+				};
+			};
+
+			regulators {
+
+				DCDC_REG1 {
+					regulator-boot-on;
+					regulator-min-microvolt = <0x86470>;
+					regulator-max-microvolt = <0xe7ef0>;
+					regulator-ramp-delay = <0x30d4>;
+					regulator-name = "vdd_gpu_s0";
+					regulator-enable-ramp-delay = <0x190>;
+					phandle = <0x4d>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				DCDC_REG2 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x86470>;
+					regulator-max-microvolt = <0xe7ef0>;
+					regulator-ramp-delay = <0x30d4>;
+					regulator-name = "vdd_cpu_lit_s0";
+					phandle = <0x12>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				DCDC_REG3 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xa4cb8>;
+					regulator-max-microvolt = <0xb71b0>;
+					regulator-ramp-delay = <0x30d4>;
+					regulator-name = "vdd_log_s0";
+
+					regulator-state-mem {
+						regulator-suspend-microvolt = <0xb71b0>;
+						regulator-on-in-suspend;
+					};
+				};
+
+				DCDC_REG4 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x86470>;
+					regulator-max-microvolt = <0xe7ef0>;
+					regulator-init-microvolt = <0xb71b0>;
+					regulator-ramp-delay = <0x30d4>;
+					regulator-name = "vdd_vdenc_s0";
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				DCDC_REG5 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xa4cb8>;
+					regulator-max-microvolt = <0xdbba0>;
+					regulator-ramp-delay = <0x30d4>;
+					regulator-name = "vdd_ddr_s0";
+					phandle = <0x37>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+						regulator-suspend-microvolt = <0xcf850>;
+					};
+				};
+
+				DCDC_REG6 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-name = "vdd2_ddr_s3";
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+					};
+				};
+
+				DCDC_REG7 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1e8480>;
+					regulator-max-microvolt = <0x1e8480>;
+					regulator-name = "vdd_2v0_pldo_s3";
+					phandle = <0x135>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0x1e8480>;
+					};
+				};
+
+				DCDC_REG8 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x325aa0>;
+					regulator-max-microvolt = <0x325aa0>;
+					regulator-name = "vcc_3v3_s3";
+					phandle = <0x183>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0x325aa0>;
+					};
+				};
+
+				DCDC_REG9 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-name = "vddq_ddr_s0";
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				DCDC_REG10 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x1b7740>;
+					regulator-name = "vcc_1v8_s3";
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0x1b7740>;
+					};
+				};
+
+				PLDO_REG1 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x1b7740>;
+					regulator-name = "avcc_1v8_s0";
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				PLDO_REG2 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x1b7740>;
+					regulator-name = "vcc_1v8_s0";
+					phandle = <0x151>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+						regulator-suspend-microvolt = <0x1b7740>;
+					};
+				};
+
+				PLDO_REG3 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x124f80>;
+					regulator-max-microvolt = <0x124f80>;
+					regulator-name = "avdd_1v2_s0";
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				PLDO_REG4 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x325aa0>;
+					regulator-max-microvolt = <0x325aa0>;
+					regulator-name = "vcc_3v3_s0";
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				PLDO_REG5 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x325aa0>;
+					regulator-name = "vccio_sd_s0";
+					phandle = <0xf1>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				PLDO_REG6 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x1b7740>;
+					regulator-name = "pldo6_s3";
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0x1b7740>;
+					};
+				};
+
+				NLDO_REG1 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xb71b0>;
+					regulator-max-microvolt = <0xb71b0>;
+					regulator-name = "vdd_0v75_s3";
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0xb71b0>;
+					};
+				};
+
+				NLDO_REG2 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xcf850>;
+					regulator-max-microvolt = <0xcf850>;
+					regulator-name = "vdd_ddr_pll_s0";
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+						regulator-suspend-microvolt = <0xcf850>;
+					};
+				};
+
+				NLDO_REG3 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xb71b0>;
+					regulator-max-microvolt = <0xb71b0>;
+					regulator-name = "avdd_0v75_s0";
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				NLDO_REG4 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xcf850>;
+					regulator-max-microvolt = <0xcf850>;
+					regulator-name = "vdd_0v85_s0";
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				NLDO_REG5 {
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xb71b0>;
+					regulator-max-microvolt = <0xb71b0>;
+					regulator-name = "vdd_0v75_s0";
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+			};
+		};
+	};
+
+	spi@feb30000 {
+		compatible = "rockchip,rk3066-spi";
+		reg = <0x00 0xfeb30000 0x00 0x1000>;
+		interrupts = <0x00 0x149 0x04>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		clocks = <0x02 0xa6 0x02 0xa1>;
+		clock-names = "spiclk\0apb_pclk";
+		dmas = <0xc9 0x11 0xc9 0x12>;
+		dma-names = "tx\0rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x137 0x138 0x139>;
+		num-cs = <0x02>;
+		status = "disabled";
+	};
+
+	serial@feb40000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfeb40000 0x00 0x100>;
+		interrupts = <0x00 0x14c 0x04>;
+		clocks = <0x02 0xb7 0x02 0xab>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0x60 0x08 0x60 0x09>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x13a>;
+		status = "disabled";
+	};
+
+	serial@feb50000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfeb50000 0x00 0x100>;
+		interrupts = <0x00 0x14d 0x04>;
+		clocks = <0x02 0xbb 0x02 0xac>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0x60 0x0a 0x60 0x0b>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x13b>;
+		status = "disabled";
+	};
+
+	serial@feb60000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfeb60000 0x00 0x100>;
+		interrupts = <0x00 0x14e 0x04>;
+		clocks = <0x02 0xbf 0x02 0xad>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0x60 0x0c 0x60 0x0d>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x13c>;
+		status = "disabled";
+	};
+
+	serial@feb70000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfeb70000 0x00 0x100>;
+		interrupts = <0x00 0x14f 0x04>;
+		clocks = <0x02 0xc3 0x02 0xae>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0xc9 0x09 0xc9 0x0a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x13d>;
+		status = "disabled";
+	};
+
+	serial@feb80000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfeb80000 0x00 0x100>;
+		interrupts = <0x00 0x150 0x04>;
+		clocks = <0x02 0xc7 0x02 0xaf>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0xc9 0x0b 0xc9 0x0c>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x13e>;
+		status = "disabled";
+	};
+
+	serial@feb90000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfeb90000 0x00 0x100>;
+		interrupts = <0x00 0x151 0x04>;
+		clocks = <0x02 0xcb 0x02 0xb0>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0xc9 0x0d 0xc9 0x0e>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x13f>;
+		status = "disabled";
+	};
+
+	serial@feba0000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfeba0000 0x00 0x100>;
+		interrupts = <0x00 0x152 0x04>;
+		clocks = <0x02 0xcf 0x02 0xb1>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0xca 0x07 0xca 0x08>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x140>;
+		status = "okay";
+	};
+
+	serial@febb0000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfebb0000 0x00 0x100>;
+		interrupts = <0x00 0x153 0x04>;
+		clocks = <0x02 0xd3 0x02 0xb2>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0xca 0x09 0xca 0x0a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x141>;
+		status = "disabled";
+	};
+
+	serial@febc0000 {
+		compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart";
+		reg = <0x00 0xfebc0000 0x00 0x100>;
+		interrupts = <0x00 0x154 0x04>;
+		clocks = <0x02 0xd7 0x02 0xb3>;
+		clock-names = "baudclk\0apb_pclk";
+		reg-shift = <0x02>;
+		reg-io-width = <0x04>;
+		dmas = <0xca 0x0b 0xca 0x0c>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x142>;
+		status = "disabled";
+	};
+
+	pwm@febd0000 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebd0000 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x143>;
+		clocks = <0x02 0x54 0x02 0x53>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+	};
+
+	pwm@febd0010 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebd0010 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x144>;
+		clocks = <0x02 0x54 0x02 0x53>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+	};
+
+	pwm@febd0020 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebd0020 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x145>;
+		clocks = <0x02 0x54 0x02 0x53>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+	};
+
+	pwm@febd0030 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebd0030 0x00 0x10>;
+		interrupts = <0x00 0x15a 0x04 0x00 0x15b 0x04>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x146>;
+		clocks = <0x02 0x54 0x02 0x53>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+	};
+
+	pwm@febe0000 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebe0000 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x147>;
+		clocks = <0x02 0x57 0x02 0x56>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+	};
+
+	pwm@febe0010 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebe0010 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x148>;
+		clocks = <0x02 0x57 0x02 0x56>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+	};
+
+	pwm@febe0020 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebe0020 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x149>;
+		clocks = <0x02 0x57 0x02 0x56>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+	};
+
+	pwm@febe0030 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebe0030 0x00 0x10>;
+		interrupts = <0x00 0x15c 0x04 0x00 0x15d 0x04>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x14a>;
+		clocks = <0x02 0x57 0x02 0x56>;
+		clock-names = "pwm\0pclk";
+		status = "okay";
+		phandle = <0x182>;
+	};
+
+	pwm@febf0000 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebf0000 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x14b>;
+		clocks = <0x02 0x5a 0x02 0x59>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+	};
+
+	pwm@febf0010 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebf0010 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x14c>;
+		clocks = <0x02 0x5a 0x02 0x59>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+	};
+
+	pwm@febf0020 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebf0020 0x00 0x10>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x14d>;
+		clocks = <0x02 0x5a 0x02 0x59>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+	};
+
+	pwm@febf0030 {
+		compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm";
+		reg = <0x00 0xfebf0030 0x00 0x10>;
+		interrupts = <0x00 0x15e 0x04 0x00 0x15f 0x04>;
+		#pwm-cells = <0x03>;
+		pinctrl-names = "active";
+		pinctrl-0 = <0x14e>;
+		clocks = <0x02 0x5a 0x02 0x59>;
+		clock-names = "pwm\0pclk";
+		status = "disabled";
+	};
+
+	tsadc@fec00000 {
+		compatible = "rockchip,rk3588-tsadc";
+		reg = <0x00 0xfec00000 0x00 0x400>;
+		interrupts = <0x00 0x18d 0x04>;
+		clocks = <0x02 0xaa 0x02 0xa9>;
+		clock-names = "tsadc\0apb_pclk";
+		assigned-clocks = <0x02 0xaa>;
+		assigned-clock-rates = <0x1e8480>;
+		resets = <0x02 0xc1 0x02 0xc0>;
+		reset-names = "tsadc\0tsadc-apb";
+		#thermal-sensor-cells = <0x01>;
+		rockchip,hw-tshut-temp = <0x1d4c0>;
+		rockchip,hw-tshut-mode = <0x00>;
+		rockchip,hw-tshut-polarity = <0x00>;
+		pinctrl-names = "gpio\0otpout";
+		pinctrl-0 = <0x14f>;
+		pinctrl-1 = <0x150>;
+		status = "okay";
+		phandle = <0x48>;
+	};
+
+	saradc@fec10000 {
+		compatible = "rockchip,rk3588-saradc";
+		reg = <0x00 0xfec10000 0x00 0x10000>;
+		interrupts = <0x00 0x18e 0x04>;
+		#io-channel-cells = <0x01>;
+		clocks = <0x02 0x9d 0x02 0x9c>;
+		clock-names = "saradc\0apb_pclk";
+		resets = <0x02 0xbe>;
+		reset-names = "saradc-apb";
+		status = "okay";
+		vref-supply = <0x151>;
+		phandle = <0x17b>;
+	};
+
+	mailbox@fec60000 {
+		compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox";
+		reg = <0x00 0xfec60000 0x00 0x200>;
+		interrupts = <0x00 0x3d 0x04 0x00 0x3e 0x04 0x00 0x3f 0x04 0x00 0x40 0x04>;
+		clocks = <0x02 0x4c>;
+		clock-names = "pclk_mailbox";
+		#mbox-cells = <0x01>;
+		status = "disabled";
+	};
+
+	mailbox@fec70000 {
+		compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox";
+		reg = <0x00 0xfec70000 0x00 0x200>;
+		interrupts = <0x00 0x45 0x04 0x00 0x46 0x04 0x00 0x47 0x04 0x00 0x48 0x04>;
+		clocks = <0x02 0x4d>;
+		clock-names = "pclk_mailbox";
+		#mbox-cells = <0x01>;
+		status = "disabled";
+	};
+
+	i2c@fec80000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfec80000 0x00 0x1000>;
+		clocks = <0x02 0x92 0x02 0x8a>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x143 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x152>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+	};
+
+	i2c@fec90000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfec90000 0x00 0x1000>;
+		clocks = <0x02 0x93 0x02 0x8b>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x144 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x153>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+
+		XC7160b@1b {
+			compatible = "firefly,xc7160";
+			reg = <0x1b>;
+			clocks = <0x02 0x100>;
+			clock-names = "xvclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <0x154>;
+			power-domains = <0x4b 0x1b>;
+			power-gpios = <0xd4 0x0d 0x01>;
+			reset-gpios = <0xe5 0x1d 0x00>;
+			pwdn-gpios = <0xd4 0x0c 0x00>;
+			firefly,clkout-enabled-index = <0x00>;
+			rockchip,camera-module-index = <0x00>;
+			rockchip,camera-module-facing = "back";
+			rockchip,camera-module-name = "NC";
+			rockchip,camera-module-lens-name = "NC";
+
+			port {
+
+				endpoint {
+					remote-endpoint = <0x155>;
+					data-lanes = <0x01 0x02 0x03 0x04>;
+					phandle = <0x2b>;
+				};
+			};
+		};
+	};
+
+	i2c@feca0000 {
+		compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c";
+		reg = <0x00 0xfeca0000 0x00 0x1000>;
+		clocks = <0x02 0x94 0x02 0x8c>;
+		clock-names = "i2c\0pclk";
+		interrupts = <0x00 0x145 0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x156>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+	};
+
+	spi@fecb0000 {
+		compatible = "rockchip,rk3066-spi";
+		reg = <0x00 0xfecb0000 0x00 0x1000>;
+		interrupts = <0x00 0x14a 0x04>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		clocks = <0x02 0xa7 0x02 0xa2>;
+		clock-names = "spiclk\0apb_pclk";
+		dmas = <0xca 0x0d 0xca 0x0e>;
+		dma-names = "tx\0rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x157 0x158 0x159>;
+		num-cs = <0x02>;
+		status = "disabled";
+	};
+
+	otp@fecc0000 {
+		compatible = "rockchip,rk3588-otp";
+		reg = <0x00 0xfecc0000 0x00 0x400>;
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+		clocks = <0x02 0x96 0x02 0x95 0x02 0x97 0x02 0x99>;
+		clock-names = "otpc\0apb\0arb\0phy";
+		resets = <0x02 0x12a 0x02 0x129 0x02 0x12b>;
+		reset-names = "otpc\0apb\0arb";
+
+		cpu-code@2 {
+			reg = <0x02 0x02>;
+			phandle = <0x27>;
+		};
+
+		id@7 {
+			reg = <0x07 0x10>;
+			phandle = <0x25>;
+		};
+
+		cpu-version@1c {
+			reg = <0x1c 0x01>;
+			bits = <0x03 0x03>;
+			phandle = <0x26>;
+		};
+
+		cpub0-leakage@17 {
+			reg = <0x17 0x01>;
+			phandle = <0x21>;
+		};
+
+		cpub1-leakage@18 {
+			reg = <0x18 0x01>;
+			phandle = <0x23>;
+		};
+
+		cpul-leakage@19 {
+			reg = <0x19 0x01>;
+			phandle = <0x1f>;
+		};
+
+		log-leakage@1a {
+			reg = <0x1a 0x01>;
+			phandle = <0x38>;
+		};
+
+		gpu-leakage@1b {
+			reg = <0x1b 0x01>;
+			phandle = <0x4e>;
+		};
+
+		npu-leakage@28 {
+			reg = <0x28 0x01>;
+			phandle = <0x98>;
+		};
+
+		codec-leakage@29 {
+			reg = <0x29 0x01>;
+		};
+	};
+
+	mailbox@fece0000 {
+		compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox";
+		reg = <0x00 0xfece0000 0x00 0x200>;
+		interrupts = <0x00 0x4d 0x04 0x00 0x4e 0x04 0x00 0x4f 0x04 0x00 0x50 0x04>;
+		clocks = <0x02 0x4e>;
+		clock-names = "pclk_mailbox";
+		#mbox-cells = <0x01>;
+		status = "disabled";
+	};
+
+	dma-controller@fed10000 {
+		compatible = "arm,pl330\0arm,primecell";
+		reg = <0x00 0xfed10000 0x00 0x4000>;
+		interrupts = <0x00 0x5a 0x04 0x00 0x5b 0x04>;
+		clocks = <0x02 0x7a>;
+		clock-names = "apb_pclk";
+		#dma-cells = <0x01>;
+		arm,pl330-periph-burst;
+		phandle = <0xca>;
+	};
+
+	phy@fed60000 {
+		compatible = "rockchip,rk3588-hdptx-phy";
+		reg = <0x00 0xfed60000 0x00 0x2000>;
+		clocks = <0x02 0x2b5 0x02 0x267>;
+		clock-names = "ref\0apb";
+		resets = <0x02 0x485 0x02 0xc003b 0x02 0xc003c 0x02 0xc003d>;
+		reset-names = "apb\0init\0cmn\0lane";
+		rockchip,grf = <0x15a>;
+		#phy-cells = <0x00>;
+		status = "disabled";
+		phandle = <0xd7>;
+	};
+
+	hdmiphy@fed60000 {
+		compatible = "rockchip,rk3588-hdptx-phy-hdmi";
+		reg = <0x00 0xfed60000 0x00 0x2000>;
+		clocks = <0x02 0x2b5 0x02 0x267>;
+		clock-names = "ref\0apb";
+		resets = <0x02 0x48e 0x02 0x485 0x02 0xc003b 0x02 0xc003c 0x02 0xc003d 0x02 0x48c 0x02 0x48d>;
+		reset-names = "phy\0apb\0init\0cmn\0lane\0ropll\0lcpll";
+		rockchip,grf = <0x15a>;
+		#phy-cells = <0x00>;
+		#clock-cells = <0x00>;
+		status = "okay";
+		phandle = <0xb6>;
+	};
+
+	phy@fed80000 {
+		compatible = "rockchip,rk3588-usbdp-phy";
+		reg = <0x00 0xfed80000 0x00 0x10000>;
+		rockchip,u2phy-grf = <0x15b>;
+		rockchip,usb-grf = <0x5b>;
+		rockchip,usbdpphy-grf = <0x15c>;
+		rockchip,vo-grf = <0x15d>;
+		clocks = <0x02 0x2b6 0x02 0x27f 0x02 0x269 0x15e>;
+		clock-names = "refclk\0immortal\0pclk\0utmi";
+		resets = <0x02 0x28 0x02 0x29 0x02 0x2a 0x02 0x2b 0x02 0x482>;
+		reset-names = "init\0cmn\0lane\0pcs_apb\0pma_apb";
+		status = "okay";
+		orientation-switch;
+		svid = <0xff01>;
+		sbu1-dc-gpios = <0xd4 0x0d 0x00>;
+		sbu2-dc-gpios = <0xd4 0x07 0x00>;
+
+		dp-port {
+			#phy-cells = <0x00>;
+			status = "okay";
+			phandle = <0xcd>;
+		};
+
+		u3-port {
+			#phy-cells = <0x00>;
+			status = "okay";
+			phandle = <0x51>;
+		};
+
+		port {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			endpoint@0 {
+				reg = <0x00>;
+				remote-endpoint = <0x15f>;
+				phandle = <0x122>;
+			};
+
+			endpoint@1 {
+				reg = <0x01>;
+				remote-endpoint = <0x160>;
+				phandle = <0x123>;
+			};
+		};
+	};
+
+	phy@feda0000 {
+		compatible = "rockchip,rk3588-mipi-dcphy";
+		reg = <0x00 0xfeda0000 0x00 0x10000>;
+		rockchip,grf = <0x161>;
+		clocks = <0x02 0x108 0x02 0x2b6>;
+		clock-names = "pclk\0ref";
+		resets = <0x02 0xc0043 0x02 0x3e 0x02 0x3f 0x02 0xc0044>;
+		reset-names = "m_phy\0apb\0grf\0s_phy";
+		#phy-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x28>;
+	};
+
+	phy@fedb0000 {
+		compatible = "rockchip,rk3588-mipi-dcphy";
+		reg = <0x00 0xfedb0000 0x00 0x10000>;
+		rockchip,grf = <0x162>;
+		clocks = <0x02 0x109 0x02 0x2b6>;
+		clock-names = "pclk\0ref";
+		resets = <0x02 0xc0045 0x02 0x43 0x02 0x44 0x02 0xc0046>;
+		reset-names = "m_phy\0apb\0grf\0s_phy";
+		#phy-cells = <0x00>;
+		status = "disabled";
+		phandle = <0x29>;
+	};
+
+	csi2-dphy0-hw@fedc0000 {
+		compatible = "rockchip,rk3588-csi2-dphy-hw";
+		reg = <0x00 0xfedc0000 0x00 0x8000>;
+		clocks = <0x02 0x10c>;
+		clock-names = "pclk";
+		resets = <0x02 0x17 0x02 0x16>;
+		reset-names = "srst_csiphy0\0srst_p_csiphy0";
+		rockchip,grf = <0x163>;
+		rockchip,sys_grf = <0xb3>;
+		status = "okay";
+		phandle = <0x2a>;
+	};
+
+	phy@fee00000 {
+		compatible = "rockchip,rk3588-naneng-combphy";
+		reg = <0x00 0xfee00000 0x00 0x100>;
+		#phy-cells = <0x01>;
+		clocks = <0x02 0x2bd 0x02 0x185 0x02 0x166>;
+		clock-names = "refclk\0apbclk\0phpclk";
+		assigned-clocks = <0x02 0x2bd>;
+		assigned-clock-rates = <0x5f5e100>;
+		resets = <0x02 0x20005 0x02 0x4d6>;
+		reset-names = "combphy-apb\0combphy";
+		rockchip,pipe-grf = <0x5d>;
+		rockchip,pipe-phy-grf = <0x164>;
+		status = "okay";
+		phandle = <0xde>;
+	};
+
+	phy@fee20000 {
+		compatible = "rockchip,rk3588-naneng-combphy";
+		reg = <0x00 0xfee20000 0x00 0x100>;
+		#phy-cells = <0x01>;
+		clocks = <0x02 0x2bf 0x02 0x187 0x02 0x166>;
+		clock-names = "refclk\0apbclk\0phpclk";
+		assigned-clocks = <0x02 0x2bf>;
+		assigned-clock-rates = <0x5f5e100>;
+		resets = <0x02 0x20007 0x02 0x4d8>;
+		reset-names = "combphy-apb\0combphy";
+		rockchip,pipe-grf = <0x5d>;
+		rockchip,pipe-phy-grf = <0x165>;
+		rockchip,pcie1ln-sel-bits = <0x100 0x01 0x01 0x00>;
+		status = "okay";
+		phandle = <0x57>;
+	};
+
+	pinctrl {
+		compatible = "rockchip,rk3588-pinctrl";
+		rockchip,grf = <0x166>;
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+		phandle = <0x167>;
+
+		gpio@fd8a0000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xfd8a0000 0x00 0x100>;
+			interrupts = <0x00 0x115 0x04>;
+			clocks = <0x02 0x284 0x02 0x285>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			gpio-ranges = <0x167 0x00 0x00 0x20>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0xe5>;
+		};
+
+		gpio@fec20000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xfec20000 0x00 0x100>;
+			interrupts = <0x00 0x116 0x04>;
+			clocks = <0x02 0x7d 0x02 0x7e>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			gpio-ranges = <0x167 0x00 0x20 0x20>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0x170>;
+		};
+
+		gpio@fec30000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xfec30000 0x00 0x100>;
+			interrupts = <0x00 0x117 0x04>;
+			clocks = <0x02 0x7f 0x02 0x80>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			gpio-ranges = <0x167 0x00 0x40 0x20>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+		};
+
+		gpio@fec40000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xfec40000 0x00 0x100>;
+			interrupts = <0x00 0x118 0x04>;
+			clocks = <0x02 0x81 0x02 0x82>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			gpio-ranges = <0x167 0x00 0x60 0x20>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0x172>;
+		};
+
+		gpio@fec50000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xfec50000 0x00 0x100>;
+			interrupts = <0x00 0x119 0x04>;
+			clocks = <0x02 0x83 0x02 0x84>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			gpio-ranges = <0x167 0x00 0x80 0x20>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0xd4>;
+		};
+
+		pcfg-pull-up {
+			bias-pull-up;
+			phandle = <0x16b>;
+		};
+
+		pcfg-pull-none {
+			bias-disable;
+			phandle = <0x168>;
+		};
+
+		pcfg-pull-none-drv-level-2 {
+			bias-disable;
+			drive-strength = <0x02>;
+			phandle = <0x16d>;
+		};
+
+		pcfg-pull-up-drv-level-1 {
+			bias-pull-up;
+			drive-strength = <0x01>;
+			phandle = <0x16c>;
+		};
+
+		pcfg-pull-up-drv-level-2 {
+			bias-pull-up;
+			drive-strength = <0x02>;
+			phandle = <0x169>;
+		};
+
+		pcfg-pull-none-smt {
+			bias-disable;
+			input-schmitt-enable;
+			phandle = <0x16a>;
+		};
+
+		auddsm {
+
+			auddsm-pins {
+				rockchip,pins = <0x03 0x01 0x04 0x168 0x03 0x02 0x04 0x168 0x03 0x03 0x04 0x168 0x03 0x04 0x04 0x168>;
+				phandle = <0x119>;
+			};
+		};
+
+		bt1120 {
+
+			bt1120-pins {
+				rockchip,pins = <0x04 0x08 0x02 0x168 0x04 0x00 0x02 0x168 0x04 0x01 0x02 0x168 0x04 0x02 0x02 0x168 0x04 0x03 0x02 0x168 0x04 0x04 0x02 0x168 0x04 0x05 0x02 0x168 0x04 0x06 0x02 0x168 0x04 0x07 0x02 0x168 0x04 0x0a 0x02 0x168 0x04 0x0b 0x02 0x168 0x04 0x0c 0x02 0x168 0x04 0x0d 0x02 0x168 0x04 0x0e 0x02 0x168 0x04 0x0f 0x02 0x168 0x04 0x10 0x02 0x168 0x04 0x11 0x02 0x168>;
+				phandle = <0x58>;
+			};
+		};
+
+		can0 {
+
+			can0m0-pins {
+				rockchip,pins = <0x00 0x10 0x0b 0x168 0x00 0x0f 0x0b 0x168>;
+				phandle = <0x11a>;
+			};
+		};
+
+		can1 {
+
+			can1m0-pins {
+				rockchip,pins = <0x03 0x0d 0x09 0x168 0x03 0x0e 0x09 0x168>;
+				phandle = <0x11b>;
+			};
+		};
+
+		can2 {
+
+			can2m0-pins {
+				rockchip,pins = <0x03 0x14 0x09 0x168 0x03 0x15 0x09 0x168>;
+				phandle = <0x11c>;
+			};
+		};
+
+		gmac1 {
+
+			gmac1-miim {
+				rockchip,pins = <0x03 0x12 0x01 0x168 0x03 0x13 0x01 0x168>;
+				phandle = <0xe6>;
+			};
+
+			gmac1-rx-bus2 {
+				rockchip,pins = <0x03 0x07 0x01 0x168 0x03 0x08 0x01 0x168 0x03 0x09 0x01 0x168>;
+				phandle = <0xe8>;
+			};
+
+			gmac1-tx-bus2 {
+				rockchip,pins = <0x03 0x0b 0x01 0x168 0x03 0x0c 0x01 0x168 0x03 0x0d 0x01 0x168>;
+				phandle = <0xe7>;
+			};
+
+			gmac1-rgmii-clk {
+				rockchip,pins = <0x03 0x05 0x01 0x168 0x03 0x04 0x01 0x168>;
+				phandle = <0xe9>;
+			};
+
+			gmac1-rgmii-bus {
+				rockchip,pins = <0x03 0x02 0x01 0x168 0x03 0x03 0x01 0x168 0x03 0x00 0x01 0x168 0x03 0x01 0x01 0x168>;
+				phandle = <0xea>;
+			};
+		};
+
+		hdmi {
+
+			hdmim0-tx0-cec {
+				rockchip,pins = <0x04 0x11 0x05 0x168>;
+				phandle = <0xd0>;
+			};
+
+			hdmim0-tx0-hpd {
+				rockchip,pins = <0x01 0x05 0x05 0x168>;
+				phandle = <0xd1>;
+			};
+
+			hdmim0-tx0-scl {
+				rockchip,pins = <0x04 0x0f 0x05 0x168>;
+				phandle = <0xd2>;
+			};
+
+			hdmim0-tx0-sda {
+				rockchip,pins = <0x04 0x10 0x05 0x168>;
+				phandle = <0xd3>;
+			};
+		};
+
+		i2c0 {
+
+			i2c0m2-xfer {
+				rockchip,pins = <0x00 0x19 0x03 0x16a 0x00 0x1a 0x03 0x16a>;
+				phandle = <0x5e>;
+			};
+		};
+
+		i2c1 {
+
+			i2c1m0-xfer {
+				rockchip,pins = <0x00 0x0d 0x09 0x16a 0x00 0x0e 0x09 0x16a>;
+				phandle = <0x11d>;
+			};
+		};
+
+		i2c2 {
+
+			i2c2m0-xfer {
+				rockchip,pins = <0x00 0x0f 0x09 0x16a 0x00 0x10 0x09 0x16a>;
+				phandle = <0x11e>;
+			};
+		};
+
+		i2c3 {
+
+			i2c3m0-xfer {
+				rockchip,pins = <0x01 0x11 0x09 0x16a 0x01 0x10 0x09 0x16a>;
+				phandle = <0x125>;
+			};
+		};
+
+		i2c4 {
+
+			i2c4m3-xfer {
+				rockchip,pins = <0x01 0x03 0x09 0x16a 0x01 0x02 0x09 0x16a>;
+				phandle = <0x127>;
+			};
+		};
+
+		i2c5 {
+
+			i2c5m0-xfer {
+				rockchip,pins = <0x03 0x17 0x09 0x16a 0x03 0x18 0x09 0x16a>;
+				phandle = <0x128>;
+			};
+		};
+
+		i2c6 {
+
+			i2c6m3-xfer {
+				rockchip,pins = <0x04 0x09 0x09 0x16a 0x04 0x08 0x09 0x16a>;
+				phandle = <0x152>;
+			};
+		};
+
+		i2c7 {
+
+			i2c7m2-xfer {
+				rockchip,pins = <0x03 0x1a 0x09 0x16a 0x03 0x1b 0x09 0x16a>;
+				phandle = <0x153>;
+			};
+		};
+
+		i2c8 {
+
+			i2c8m0-xfer {
+				rockchip,pins = <0x04 0x1a 0x09 0x16a 0x04 0x1b 0x09 0x16a>;
+				phandle = <0x156>;
+			};
+		};
+
+		i2s0 {
+
+			i2s0-lrck {
+				rockchip,pins = <0x01 0x15 0x01 0x168>;
+				phandle = <0xf5>;
+			};
+
+			i2s0-mclk {
+				rockchip,pins = <0x01 0x12 0x01 0x168>;
+				phandle = <0x126>;
+			};
+
+			i2s0-sclk {
+				rockchip,pins = <0x01 0x13 0x01 0x168>;
+				phandle = <0xf6>;
+			};
+
+			i2s0-sdi0 {
+				rockchip,pins = <0x01 0x1c 0x02 0x168>;
+				phandle = <0xf7>;
+			};
+
+			i2s0-sdo0 {
+				rockchip,pins = <0x01 0x17 0x01 0x168>;
+				phandle = <0xf8>;
+			};
+		};
+
+		i2s1 {
+
+			i2s1m0-lrck {
+				rockchip,pins = <0x04 0x02 0x03 0x168>;
+				phandle = <0xf9>;
+			};
+
+			i2s1m0-sclk {
+				rockchip,pins = <0x04 0x01 0x03 0x168>;
+				phandle = <0xfa>;
+			};
+
+			i2s1m0-sdi0 {
+				rockchip,pins = <0x04 0x05 0x03 0x168>;
+				phandle = <0xfb>;
+			};
+
+			i2s1m0-sdi1 {
+				rockchip,pins = <0x04 0x06 0x03 0x168>;
+				phandle = <0xfc>;
+			};
+
+			i2s1m0-sdi2 {
+				rockchip,pins = <0x04 0x07 0x03 0x168>;
+				phandle = <0xfd>;
+			};
+
+			i2s1m0-sdi3 {
+				rockchip,pins = <0x04 0x08 0x03 0x168>;
+				phandle = <0xfe>;
+			};
+
+			i2s1m0-sdo0 {
+				rockchip,pins = <0x04 0x09 0x03 0x168>;
+				phandle = <0xff>;
+			};
+
+			i2s1m0-sdo1 {
+				rockchip,pins = <0x04 0x0a 0x03 0x168>;
+				phandle = <0x100>;
+			};
+
+			i2s1m0-sdo2 {
+				rockchip,pins = <0x04 0x0b 0x03 0x168>;
+				phandle = <0x101>;
+			};
+
+			i2s1m0-sdo3 {
+				rockchip,pins = <0x04 0x0c 0x03 0x168>;
+				phandle = <0x102>;
+			};
+		};
+
+		i2s2 {
+
+			i2s2m1-lrck {
+				rockchip,pins = <0x03 0x0e 0x03 0x168>;
+				phandle = <0x103>;
+			};
+
+			i2s2m1-sclk {
+				rockchip,pins = <0x03 0x0d 0x03 0x168>;
+				phandle = <0x104>;
+			};
+
+			i2s2m1-sdi {
+				rockchip,pins = <0x03 0x0a 0x03 0x168>;
+				phandle = <0x105>;
+			};
+
+			i2s2m1-sdo {
+				rockchip,pins = <0x03 0x0b 0x03 0x168>;
+				phandle = <0x106>;
+			};
+		};
+
+		i2s3 {
+
+			i2s3-lrck {
+				rockchip,pins = <0x03 0x02 0x03 0x168>;
+				phandle = <0x107>;
+			};
+
+			i2s3-sclk {
+				rockchip,pins = <0x03 0x01 0x03 0x168>;
+				phandle = <0x108>;
+			};
+
+			i2s3-sdi {
+				rockchip,pins = <0x03 0x04 0x03 0x168>;
+				phandle = <0x109>;
+			};
+
+			i2s3-sdo {
+				rockchip,pins = <0x03 0x03 0x03 0x168>;
+				phandle = <0x10a>;
+			};
+		};
+
+		mipi {
+
+			mipim1-camera1-clk {
+				rockchip,pins = <0x03 0x06 0x04 0x168>;
+				phandle = <0x154>;
+			};
+		};
+
+		pdm0 {
+
+			pdm0m0-clk {
+				rockchip,pins = <0x01 0x16 0x03 0x168>;
+				phandle = <0x10b>;
+			};
+
+			pdm0m0-clk1 {
+				rockchip,pins = <0x01 0x14 0x03 0x168>;
+				phandle = <0x10c>;
+			};
+
+			pdm0m0-sdi0 {
+				rockchip,pins = <0x01 0x1d 0x03 0x168>;
+				phandle = <0x10d>;
+			};
+
+			pdm0m0-sdi1 {
+				rockchip,pins = <0x01 0x19 0x03 0x168>;
+				phandle = <0x10e>;
+			};
+
+			pdm0m0-sdi2 {
+				rockchip,pins = <0x01 0x1a 0x03 0x168>;
+				phandle = <0x10f>;
+			};
+
+			pdm0m0-sdi3 {
+				rockchip,pins = <0x01 0x1b 0x03 0x168>;
+				phandle = <0x110>;
+			};
+		};
+
+		pdm1 {
+
+			pdm1m0-clk {
+				rockchip,pins = <0x04 0x1d 0x02 0x168>;
+				phandle = <0x111>;
+			};
+
+			pdm1m0-clk1 {
+				rockchip,pins = <0x04 0x1c 0x02 0x168>;
+				phandle = <0x112>;
+			};
+
+			pdm1m0-sdi0 {
+				rockchip,pins = <0x04 0x1b 0x02 0x168>;
+				phandle = <0x113>;
+			};
+
+			pdm1m0-sdi1 {
+				rockchip,pins = <0x04 0x1a 0x02 0x168>;
+				phandle = <0x114>;
+			};
+
+			pdm1m0-sdi2 {
+				rockchip,pins = <0x04 0x19 0x02 0x168>;
+				phandle = <0x115>;
+			};
+
+			pdm1m0-sdi3 {
+				rockchip,pins = <0x04 0x18 0x02 0x168>;
+				phandle = <0x116>;
+			};
+		};
+
+		pmic {
+
+			pmic-pins {
+				rockchip,pins = <0x00 0x07 0x00 0x16b 0x00 0x02 0x01 0x168 0x00 0x03 0x01 0x168 0x00 0x11 0x01 0x168 0x00 0x12 0x01 0x168 0x00 0x13 0x01 0x168 0x00 0x1e 0x01 0x168>;
+				phandle = <0x130>;
+			};
+		};
+
+		pwm0 {
+
+			pwm0m0-pins {
+				rockchip,pins = <0x00 0x0f 0x03 0x168>;
+				phandle = <0x62>;
+			};
+		};
+
+		pwm1 {
+
+			pwm1m0-pins {
+				rockchip,pins = <0x00 0x10 0x03 0x168>;
+				phandle = <0x63>;
+			};
+		};
+
+		pwm2 {
+
+			pwm2m0-pins {
+				rockchip,pins = <0x00 0x14 0x03 0x168>;
+				phandle = <0x64>;
+			};
+		};
+
+		pwm3 {
+
+			pwm3m0-pins {
+				rockchip,pins = <0x00 0x1c 0x03 0x168>;
+				phandle = <0x65>;
+			};
+		};
+
+		pwm4 {
+
+			pwm4m0-pins {
+				rockchip,pins = <0x00 0x15 0x0b 0x168>;
+				phandle = <0x143>;
+			};
+		};
+
+		pwm5 {
+
+			pwm5m0-pins {
+				rockchip,pins = <0x00 0x09 0x03 0x168>;
+				phandle = <0x144>;
+			};
+		};
+
+		pwm6 {
+
+			pwm6m0-pins {
+				rockchip,pins = <0x00 0x17 0x0b 0x168>;
+				phandle = <0x145>;
+			};
+		};
+
+		pwm7 {
+
+			pwm7m0-pins {
+				rockchip,pins = <0x00 0x18 0x0b 0x168>;
+				phandle = <0x146>;
+			};
+		};
+
+		pwm8 {
+
+			pwm8m0-pins {
+				rockchip,pins = <0x03 0x07 0x0b 0x168>;
+				phandle = <0x147>;
+			};
+		};
+
+		pwm9 {
+
+			pwm9m0-pins {
+				rockchip,pins = <0x03 0x08 0x0b 0x168>;
+				phandle = <0x148>;
+			};
+		};
+
+		pwm10 {
+
+			pwm10m0-pins {
+				rockchip,pins = <0x03 0x00 0x0b 0x168>;
+				phandle = <0x149>;
+			};
+		};
+
+		pwm11 {
+
+			pwm11m3-pins {
+				rockchip,pins = <0x03 0x1d 0x0b 0x168>;
+				phandle = <0x14a>;
+			};
+		};
+
+		pwm12 {
+
+			pwm12m0-pins {
+				rockchip,pins = <0x03 0x0d 0x0b 0x168>;
+				phandle = <0x14b>;
+			};
+		};
+
+		pwm13 {
+
+			pwm13m0-pins {
+				rockchip,pins = <0x03 0x0e 0x0b 0x168>;
+				phandle = <0x14c>;
+			};
+		};
+
+		pwm14 {
+
+			pwm14m0-pins {
+				rockchip,pins = <0x03 0x12 0x0b 0x168>;
+				phandle = <0x14d>;
+			};
+		};
+
+		pwm15 {
+
+			pwm15m0-pins {
+				rockchip,pins = <0x03 0x13 0x0b 0x168>;
+				phandle = <0x14e>;
+			};
+		};
+
+		sata {
+
+			sata-reset {
+				rockchip,pins = <0x03 0x19 0x00 0x16b>;
+				phandle = <0xec>;
+			};
+		};
+
+		sdio {
+
+			sdiom1-pins {
+				rockchip,pins = <0x03 0x05 0x02 0x168 0x03 0x04 0x02 0x16b 0x03 0x00 0x02 0x16b 0x03 0x01 0x02 0x16b 0x03 0x02 0x02 0x16b 0x03 0x03 0x02 0x16b>;
+				phandle = <0xf3>;
+			};
+		};
+
+		sdmmc {
+
+			sdmmc-bus4 {
+				rockchip,pins = <0x04 0x18 0x01 0x169 0x04 0x19 0x01 0x169 0x04 0x1a 0x01 0x169 0x04 0x1b 0x01 0x169>;
+				phandle = <0xf0>;
+			};
+
+			sdmmc-clk {
+				rockchip,pins = <0x04 0x1d 0x01 0x169>;
+				phandle = <0xed>;
+			};
+
+			sdmmc-cmd {
+				rockchip,pins = <0x04 0x1c 0x01 0x169>;
+				phandle = <0xee>;
+			};
+
+			sdmmc-det {
+				rockchip,pins = <0x00 0x04 0x01 0x16b>;
+				phandle = <0xef>;
+			};
+		};
+
+		spdif0 {
+
+			spdif0m0-tx {
+				rockchip,pins = <0x01 0x0e 0x03 0x168>;
+				phandle = <0x117>;
+			};
+		};
+
+		spdif1 {
+
+			spdif1m0-tx {
+				rockchip,pins = <0x01 0x0f 0x03 0x168>;
+				phandle = <0x118>;
+			};
+		};
+
+		spi0 {
+
+			spi0m0-pins {
+				rockchip,pins = <0x00 0x16 0x08 0x16c 0x00 0x17 0x08 0x16c 0x00 0x10 0x08 0x16c>;
+				phandle = <0x12b>;
+			};
+
+			spi0m0-cs0 {
+				rockchip,pins = <0x00 0x19 0x08 0x16c>;
+				phandle = <0x129>;
+			};
+
+			spi0m0-cs1 {
+				rockchip,pins = <0x00 0x0f 0x08 0x16c>;
+				phandle = <0x12a>;
+			};
+		};
+
+		spi1 {
+
+			spi1m2-pins {
+				rockchip,pins = <0x01 0x1a 0x08 0x16c 0x01 0x18 0x08 0x16c 0x01 0x19 0x08 0x16c>;
+				phandle = <0x12d>;
+			};
+
+			spi1m2-cs0 {
+				rockchip,pins = <0x01 0x1b 0x08 0x16c>;
+				phandle = <0x12c>;
+			};
+		};
+
+		spi2 {
+
+			spi2m2-pins {
+				rockchip,pins = <0x00 0x05 0x01 0x16c 0x00 0x0b 0x01 0x16c 0x00 0x06 0x01 0x16c>;
+				phandle = <0x12f>;
+			};
+
+			spi2m2-cs0 {
+				rockchip,pins = <0x00 0x09 0x01 0x16c>;
+				phandle = <0x12e>;
+			};
+		};
+
+		spi3 {
+
+			spi3m1-pins {
+				rockchip,pins = <0x04 0x0f 0x08 0x16c 0x04 0x0d 0x08 0x16c 0x04 0x0e 0x08 0x16c>;
+				phandle = <0x139>;
+			};
+
+			spi3m1-cs0 {
+				rockchip,pins = <0x04 0x10 0x08 0x16c>;
+				phandle = <0x137>;
+			};
+
+			spi3m1-cs1 {
+				rockchip,pins = <0x04 0x11 0x08 0x16c>;
+				phandle = <0x138>;
+			};
+		};
+
+		spi4 {
+
+			spi4m0-pins {
+				rockchip,pins = <0x01 0x12 0x08 0x16c 0x01 0x10 0x08 0x16c 0x01 0x11 0x08 0x16c>;
+				phandle = <0x159>;
+			};
+
+			spi4m0-cs0 {
+				rockchip,pins = <0x01 0x13 0x08 0x16c>;
+				phandle = <0x157>;
+			};
+
+			spi4m0-cs1 {
+				rockchip,pins = <0x01 0x14 0x08 0x16c>;
+				phandle = <0x158>;
+			};
+		};
+
+		tsadc {
+
+			tsadc-shut {
+				rockchip,pins = <0x00 0x01 0x02 0x168>;
+				phandle = <0x150>;
+			};
+		};
+
+		uart0 {
+
+			uart0m1-xfer {
+				rockchip,pins = <0x00 0x08 0x04 0x16b 0x00 0x09 0x04 0x16b>;
+				phandle = <0x61>;
+			};
+		};
+
+		uart1 {
+
+			uart1m1-xfer {
+				rockchip,pins = <0x01 0x0f 0x0a 0x16b 0x01 0x0e 0x0a 0x16b>;
+				phandle = <0x13a>;
+			};
+		};
+
+		uart2 {
+
+			uart2m0-xfer {
+				rockchip,pins = <0x00 0x0e 0x0a 0x16b 0x00 0x0d 0x0a 0x16b>;
+				phandle = <0x16f>;
+			};
+
+			uart2m1-xfer {
+				rockchip,pins = <0x04 0x19 0x0a 0x16b 0x04 0x18 0x0a 0x16b>;
+				phandle = <0x13b>;
+			};
+		};
+
+		uart3 {
+
+			uart3m1-xfer {
+				rockchip,pins = <0x03 0x0e 0x0a 0x16b 0x03 0x0d 0x0a 0x16b>;
+				phandle = <0x13c>;
+			};
+		};
+
+		uart4 {
+
+			uart4m1-xfer {
+				rockchip,pins = <0x03 0x18 0x0a 0x16b 0x03 0x19 0x0a 0x16b>;
+				phandle = <0x13d>;
+			};
+		};
+
+		uart5 {
+
+			uart5m1-xfer {
+				rockchip,pins = <0x03 0x15 0x0a 0x16b 0x03 0x14 0x0a 0x16b>;
+				phandle = <0x13e>;
+			};
+		};
+
+		uart6 {
+
+			uart6m1-xfer {
+				rockchip,pins = <0x01 0x00 0x0a 0x16b 0x01 0x01 0x0a 0x16b>;
+				phandle = <0x13f>;
+			};
+		};
+
+		uart7 {
+
+			uart7m2-xfer {
+				rockchip,pins = <0x01 0x0c 0x0a 0x16b 0x01 0x0d 0x0a 0x16b>;
+				phandle = <0x140>;
+			};
+		};
+
+		uart8 {
+
+			uart8m1-xfer {
+				rockchip,pins = <0x03 0x03 0x0a 0x16b 0x03 0x02 0x0a 0x16b>;
+				phandle = <0x141>;
+			};
+		};
+
+		uart9 {
+
+			uart9m1-xfer {
+				rockchip,pins = <0x04 0x0d 0x0a 0x16b 0x04 0x0c 0x0a 0x16b>;
+				phandle = <0x142>;
+			};
+		};
+
+		gpio-func {
+
+			tsadc-gpio-func {
+				rockchip,pins = <0x00 0x01 0x00 0x168>;
+				phandle = <0x14f>;
+			};
+		};
+
+		leds {
+
+			led-user {
+				rockchip,pins = <0x03 0x0a 0x00 0x168>;
+				phandle = <0x173>;
+			};
+
+			led-power {
+				rockchip,pins = <0x01 0x1d 0x00 0x168>;
+				phandle = <0x171>;
+			};
+
+			led-user1 {
+				rockchip,pins = <0x03 0x10 0x00 0x168>;
+				phandle = <0x174>;
+			};
+		};
+
+		headphone {
+
+			hp-det {
+				rockchip,pins = <0x01 0x06 0x00 0x168>;
+				phandle = <0x17e>;
+			};
+		};
+
+		hym8563 {
+
+			hym8563-int {
+				rockchip,pins = <0x00 0x08 0x00 0x16b>;
+				phandle = <0x124>;
+			};
+		};
+
+		usb {
+
+			vcc5v0-host-en {
+				rockchip,pins = <0x01 0x0e 0x00 0x168>;
+				phandle = <0x180>;
+			};
+		};
+
+		usb-typec {
+
+			usbc0-int {
+				rockchip,pins = <0x00 0x14 0x00 0x16b>;
+				phandle = <0x11f>;
+			};
+
+			typec5v-pwren {
+				rockchip,pins = <0x01 0x09 0x00 0x168>;
+				phandle = <0x181>;
+			};
+		};
+
+		cam {
+
+			mipidphy0-pwr {
+				rockchip,pins = <0x01 0x09 0x00 0x168>;
+				phandle = <0x184>;
+			};
+		};
+	};
+
+	test-power {
+		status = "okay";
+	};
+
+	vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0xb71b00>;
+		regulator-max-microvolt = <0xb71b00>;
+		phandle = <0x16e>;
+	};
+
+	vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x4c4b40>;
+		regulator-max-microvolt = <0x4c4b40>;
+		vin-supply = <0x16e>;
+		phandle = <0x5f>;
+	};
+
+	vcc5v0-usbdcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usbdcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x4c4b40>;
+		regulator-max-microvolt = <0x4c4b40>;
+		vin-supply = <0x16e>;
+	};
+
+	vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x4c4b40>;
+		regulator-max-microvolt = <0x4c4b40>;
+		vin-supply = <0x16e>;
+		phandle = <0x17f>;
+	};
+
+	vcc-1v1-nldo-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x10c8e0>;
+		regulator-max-microvolt = <0x10c8e0>;
+		vin-supply = <0x5f>;
+		phandle = <0x136>;
+	};
+
+	chosen {
+		bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 root=PARTLABEL=rootfs rootfstype=ext4 rw rootwait overlayroot=device:dev=PARTLABEL=userdata,fstype=ext4,mkfs=1 coherent_pool=1m systemd.gpt_auto=0 cgroup_enable=memory swapaccount=1";
+	};
+
+	cspmu@fd10c000 {
+		compatible = "rockchip,cspmu";
+		reg = <0x00 0xfd10c000 0x00 0x1000 0x00 0xfd10d000 0x00 0x1000 0x00 0xfd10e000 0x00 0x1000 0x00 0xfd10f000 0x00 0x1000 0x00 0xfd12c000 0x00 0x1000 0x00 0xfd12d000 0x00 0x1000 0x00 0xfd12e000 0x00 0x1000 0x00 0xfd12f000 0x00 0x1000>;
+	};
+
+	debug@fd104000 {
+		compatible = "rockchip,debug";
+		reg = <0x00 0xfd104000 0x00 0x1000 0x00 0xfd105000 0x00 0x1000 0x00 0xfd106000 0x00 0x1000 0x00 0xfd107000 0x00 0x1000 0x00 0xfd124000 0x00 0x1000 0x00 0xfd125000 0x00 0x1000 0x00 0xfd126000 0x00 0x1000 0x00 0xfd127000 0x00 0x1000>;
+	};
+
+	fiq-debugger {
+		compatible = "rockchip,fiq-debugger";
+		rockchip,serial-id = <0x02>;
+		rockchip,wake-irq = <0x00>;
+		rockchip,irq-mode-enable = <0x01>;
+		rockchip,baudrate = <0x16e360>;
+		interrupts = <0x00 0x1a7 0x08>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x16f>;
+		status = "okay";
+	};
+
+	ramoops@110000 {
+		compatible = "ramoops";
+		reg = <0x00 0x110000 0x00 0xf0000>;
+		record-size = <0x20000>;
+		console-size = <0x80000>;
+		ftrace-size = <0x00>;
+		pmsg-size = <0x50000>;
+	};
+
+	reserved-memory {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+
+		cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x00 0x800000>;
+			linux,cma-default;
+		};
+
+		drm-logo@00000000 {
+			compatible = "rockchip,drm-logo";
+			reg = <0x00 0x00 0x00 0x00>;
+			phandle = <0x2e>;
+		};
+
+		drm-cubic-lut@00000000 {
+			compatible = "rockchip,drm-cubic-lut";
+			reg = <0x00 0x00 0x00 0x00>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		status = "okay";
+
+		power {
+			label = ":power";
+			linux,default-trigger = "ir-power-click";
+			default-state = "on";
+			gpios = <0x170 0x1d 0x00>;
+			pinctrl-names = "default";
+			pinctrl-0 = <0x171>;
+		};
+
+		user {
+			label = ":user";
+			linux,default-trigger = "ir-user-click";
+			default-state = "off";
+			gpios = <0x172 0x0a 0x00>;
+			pinctrl-names = "default";
+			pinctrl-0 = <0x173>;
+		};
+
+		user1 {
+			label = ":user1";
+			default-state = "off";
+			gpios = <0x172 0x10 0x00>;
+			pinctrl-names = "default";
+			pinctrl-0 = <0x174>;
+		};
+	};
+
+	hdmi0-sound {
+		status = "okay";
+		compatible = "rockchip,hdmi";
+		rockchip,mclk-fs = <0x80>;
+		rockchip,card-name = "rockchip-hdmi0";
+		rockchip,cpu = <0x175>;
+		rockchip,codec = <0x176>;
+		rockchip,jack-det;
+	};
+
+	dp0-sound {
+		status = "okay";
+		compatible = "rockchip,hdmi";
+		rockchip,card-name = "rockchip,dp0";
+		rockchip,mclk-fs = <0x200>;
+		rockchip,cpu = <0x177>;
+		rockchip,codec = <0x178 0x01>;
+		rockchip,jack-det;
+	};
+
+	spdif-tx1-dc {
+		status = "disabled";
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0x00>;
+		phandle = <0x17a>;
+	};
+
+	spdif-tx1-sound {
+		status = "disabled";
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "rockchip,spdif-tx1";
+
+		simple-audio-card,cpu {
+			sound-dai = <0x179>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <0x17a>;
+		};
+	};
+
+	adc-keys {
+		status = "okay";
+		compatible = "adc-keys";
+		io-channels = <0x17b 0x01>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <0x1b7740>;
+		poll-interval = <0x64>;
+
+		recovery-key {
+			label = "F12";
+			linux,code = <0x58>;
+			press-threshold-microvolt = <0x4268>;
+		};
+	};
+
+	es8388-sound {
+		status = "okay";
+		compatible = "firefly,multicodecs-card";
+		rockchip,card-name = "rockchip-es8388";
+		hp-det-gpio = <0x170 0x06 0x01>;
+		io-channels = <0x17b 0x05>;
+		io-channel-names = "hw-ver";
+		hp-con-gpio = <0x170 0x04 0x00>;
+		linein-type = <0x01>;
+		rockchip,format = "i2s";
+		rockchip,mclk-fs = <0x100>;
+		rockchip,cpu = <0x17c>;
+		rockchip,codec = <0x17d>;
+		rockchip,audio-routing = "Headphone\0LOUT2\0Headphone\0ROUT2\0Speaker\0LOUT1\0Speaker\0ROUT1\0Headphone\0Headphone Power\0Headphone\0Headphone Power\0LINPUT1\0Main Mic\0LINPUT2\0Main Mic\0RINPUT1\0Headset Mic\0RINPUT2\0Headset Mic";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x17e>;
+	};
+
+	vcc5v0-host {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-boot-on;
+		regulator-always-on;
+		enable-active-high;
+		gpio = <0x170 0x0e 0x00>;
+		vin-supply = <0x17f>;
+		status = "okay";
+		reset-delay-us = <0x30d40>;
+		startup-delay-us = <0x124f80>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x180>;
+		phandle = <0x5c>;
+	};
+
+	vcc-hub-reset-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_hub_reset";
+		regulator-boot-on;
+		regulator-always-on;
+		enable-active-high;
+		status = "okay";
+		gpio = <0x170 0x08 0x00>;
+	};
+
+	vbus5v0-typec-pwr-en-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus5v0_typec_pwr_en";
+		enable-active-high;
+		status = "okay";
+		gpio = <0x170 0x09 0x00>;
+		regulator-min-microvolt = <0x4c4b40>;
+		regulator-max-microvolt = <0x4c4b40>;
+		vin-supply = <0x17f>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x181>;
+		phandle = <0x120>;
+	};
+
+	pwm-fan {
+		compatible = "pwm-fan";
+		#cooling-cells = <0x02>;
+		fan-supply = <0x16e>;
+		pwms = <0x182 0x00 0xc350 0x01>;
+	};
+
+	vcc3v3-pcie20 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie20";
+		regulator-min-microvolt = <0x325aa0>;
+		regulator-max-microvolt = <0x325aa0>;
+		regulator-always-on;
+		enable-active-high;
+		gpios = <0x170 0x1f 0x00>;
+		startup-delay-us = <0x1388>;
+		vin-supply = <0x16e>;
+	};
+
+	vcc-3v3-sd-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_sd_s0";
+		regulator-min-microvolt = <0x325aa0>;
+		regulator-max-microvolt = <0x325aa0>;
+		gpios = <0x170 0x00 0x01>;
+		enable-active-low;
+		vin-supply = <0x183>;
+		phandle = <0xf2>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	lcd_rst {
+		status = "disabled";
+		compatible = "regulator-fixed";
+		regulator-name = "lcd_rst";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <0x325aa0>;
+		regulator-max-microvolt = <0x325aa0>;
+		enable-active-high;
+		gpio = <0x170 0x01 0x00>;
+		startup-delay-us = <0x7d0>;
+		vin-supply = <0x16e>;
+	};
+
+	lcd_en {
+		status = "disabled";
+		compatible = "regulator-fixed";
+		regulator-name = "lcd_en";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <0x325aa0>;
+		regulator-max-microvolt = <0x325aa0>;
+		enable-active-high;
+		gpio = <0x170 0x0b 0x00>;
+		vin-supply = <0x16e>;
+	};
+
+	firefly_wake {
+		compatible = "firefly-wake";
+		status = "okay";
+	};
+
+	cam_ircut {
+		status = "disabled";
+		compatible = "rockchip,ircut";
+		ircut-open-gpios = <0xd4 0x06 0x00>;
+		ircut-close-gpios = <0xd4 0x07 0x00>;
+		rockchip,camera-module-index = <0x00>;
+		rockchip,camera-module-facing = "back";
+	};
+
+	vcc-mipidcphy0-regulator {
+		status = "disabled";
+		compatible = "regulator-fixed";
+		gpio = <0x170 0x09 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x184>;
+		regulator-name = "vcc_mipidphy0";
+		enable-active-high;
+	};
+};
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 6fa56a4739953ac63067e7d62613751a28ef6047..b08bb8b8c3d6dda72aea6ba06bdf8617630134d6 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -7,6 +7,12 @@ menu "Character devices"
 
 source "drivers/tty/Kconfig"
 
+config RYD_GPIO_CONTROL
+	tristate "Support New RYD GPIO Control (Not use anymore)"
+	default y
+	help
+	  If you say Y here, you will get support for a character device
+
 config TTY_PRINTK
 	tristate "TTY driver to output user messages via printk"
 	depends on EXPERT && TTY
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index 71d76fd62692fe64859ca464984b0bdd8a9454f9..e6a60a86d19aa5b1b65dc6fa1f1aeefe03b700e0 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -48,3 +48,4 @@ obj-$(CONFIG_XILLYBUS)		+= xillybus/
 obj-$(CONFIG_POWERNV_OP_PANEL)	+= powernv-op-panel.o
 obj-$(CONFIG_ADI)		+= adi.o
 obj-$(CONFIG_PIN_MEMORY_DEV)	+= pin_memory.o
+obj-y	+= ryd_gpio_controls.o
diff --git a/drivers/char/ryd_gpio_controls.c b/drivers/char/ryd_gpio_controls.c
new file mode 100644
index 0000000000000000000000000000000000000000..6e44ca3e9699539a965495b0808de9e8d5e00807
--- /dev/null
+++ b/drivers/char/ryd_gpio_controls.c
@@ -0,0 +1,264 @@
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/platform_device.h>
+
+#define D_DIRE_OUT 1
+#define D_DIRE_IN 0
+
+#define D_PULL_NULL 0
+#define D_PULL_LOW 1
+#define D_PULL_UP 2
+/*
+ryd_gpio_control {
+	compatible = "ryd_gpio_control";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	title {
+		gpio = <&gpio8 3 GPIO_ACTIVE_LOW>;
+		pull_cfg =  0=null 1=pulldown 2=pullup
+		dire_in:defaule dire_out
+		sys_create: create sys node
+		export:export gpio
+	}
+	
+};*/
+
+struct gpio_des {
+	char name[20];
+	int gpio;
+	char flags;
+	char dir;
+	char pulldata;
+	char resetdelay;
+	char export;
+	struct device_attribute sysnode;
+};
+
+struct ryd_gpio_des {
+	int gpio_num;
+	struct gpio_des gpio_des_data[30];
+};
+
+static struct platform_driver ryd_gpio_driver;
+
+static ssize_t gpio_state_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t len)
+{
+	int index = 0;
+	int value = buf[0] - 48;
+	if ((value == 0) || (value == 1))
+	{
+		struct ryd_gpio_des *data = dev_get_drvdata(dev);
+		while(index < data->gpio_num)
+		{
+			if(strcmp(attr->attr.name,data->gpio_des_data[index].name) == 0)
+			{
+				if (data->gpio_des_data[index].dir == D_DIRE_OUT)
+				{
+					if (gpio_cansleep(data->gpio_des_data[index].gpio) == 1)
+						gpiod_set_value_cansleep(gpio_to_desc(data->gpio_des_data[index].gpio),value);
+					else
+						gpio_direction_output(data->gpio_des_data[index].gpio,value);
+				}
+				break;
+			}
+			index++;
+		}
+	}
+	
+	return len;
+}
+
+static ssize_t gpio_state_show(struct device *dev, struct device_attribute *attr,char *buf)
+{
+	int index = 0;
+	int value = -1;
+	struct ryd_gpio_des *data = dev_get_drvdata(dev);
+	while(index < data->gpio_num)
+	{
+		if(strcmp(attr->attr.name,data->gpio_des_data[index].name) == 0)
+		{
+			if (gpio_cansleep(data->gpio_des_data[index].gpio) == 1)
+				value = gpiod_get_value_cansleep(gpio_to_desc(data->gpio_des_data[index].gpio));
+			else
+				value = gpio_get_value(data->gpio_des_data[index].gpio);	
+			break;
+		}
+		index++;
+	}
+
+	return sprintf(buf, "%d\n", value);
+}
+
+static int rydgpio_parse_dt(struct device_node *fathernode,struct ryd_gpio_des *data)
+{
+	struct device_node *childnode;
+	enum of_gpio_flags flags;
+	data->gpio_num = 0;
+	for_each_child_of_node(fathernode, childnode) 
+	{
+		data->gpio_des_data[data->gpio_num].gpio = of_get_named_gpio_flags(childnode, "gpio", 0,&flags);
+
+		if (!gpio_is_valid(data->gpio_des_data[data->gpio_num].gpio))
+		{
+			printk("get ryd gpio is error\n");
+			continue;
+		}
+		data->gpio_des_data[data->gpio_num].flags = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
+		data->gpio_des_data[data->gpio_num].dir = D_DIRE_OUT;
+		if (of_property_read_bool(childnode, "dir_in"))
+		{
+			data->gpio_des_data[data->gpio_num].dir = D_DIRE_IN;
+		}
+
+		of_property_read_u8(childnode, "pull_cfg", &(data->gpio_des_data[data->gpio_num].pulldata));
+
+		if (of_property_read_bool(childnode, "sys_create"))
+		{
+			sprintf(data->gpio_des_data[data->gpio_num].name,childnode->name);
+		}
+		else
+		{
+			sprintf(data->gpio_des_data[data->gpio_num].name,"null");
+		}
+
+		data->gpio_des_data[data->gpio_num].resetdelay = 0;
+		if (of_property_read_bool(childnode, "reset_pin"))
+		{
+			of_property_read_u8(childnode, "reset_pin", &(data->gpio_des_data[data->gpio_num].resetdelay));
+		}
+
+		if (of_property_read_bool(childnode, "export"))
+		{
+			data->gpio_des_data[data->gpio_num].export = 1;
+		}
+
+		data->gpio_num++;
+	}
+	return 0;
+}
+
+static int rydgpio_deal(struct platform_device *pdev,struct ryd_gpio_des *data)
+{
+	int index = 0;
+	int ret;
+	while(index < data->gpio_num)
+	{
+		ret = gpio_request(data->gpio_des_data[index].gpio,data->gpio_des_data[index].name);
+		if (ret != 0) {
+			pr_err("gpio_request gpio invalid: %d\n",index);
+		}
+		else
+		{
+			//deal reset
+			if (data->gpio_des_data[index].resetdelay > 0)
+			{
+				if (data->gpio_des_data[index].dir == D_DIRE_OUT)
+				{
+					if (gpio_cansleep(data->gpio_des_data[index].gpio) == 1)
+						gpiod_set_value_cansleep(gpio_to_desc(data->gpio_des_data[index].gpio),!data->gpio_des_data[index].flags);
+					else
+						gpio_direction_output(data->gpio_des_data[index].gpio,!data->gpio_des_data[index].flags);
+				}
+				msleep(data->gpio_des_data[index].resetdelay);
+			}
+
+			if (data->gpio_des_data[index].dir == D_DIRE_OUT)
+			{
+				gpio_direction_output(data->gpio_des_data[index].gpio,data->gpio_des_data[index].flags);
+				if (gpio_cansleep(data->gpio_des_data[index].gpio) == 1)
+					gpiod_set_value_cansleep(gpio_to_desc(data->gpio_des_data[index].gpio),data->gpio_des_data[index].flags);
+				else
+					gpio_direction_output(data->gpio_des_data[index].gpio,data->gpio_des_data[index].flags);
+			}
+
+			if (data->gpio_des_data[index].pulldata == D_PULL_UP)
+			{
+
+			}
+			else if(data->gpio_des_data[index].pulldata == D_PULL_LOW)
+			{
+
+			}
+
+			if (strcmp(data->gpio_des_data[index].name,"null") != 0)
+			{
+				data->gpio_des_data[index].sysnode.attr.name = data->gpio_des_data[index].name;
+				data->gpio_des_data[index].sysnode.attr.mode = S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH;
+				data->gpio_des_data[index].sysnode.show = gpio_state_show;
+				data->gpio_des_data[index].sysnode.store = gpio_state_store;
+				device_create_file(&pdev->dev,&(data->gpio_des_data[index].sysnode));
+			}
+
+			if (data->gpio_des_data[index].export == 1)
+			{
+				if (data->gpio_des_data[index].dir == D_DIRE_IN){
+					gpio_direction_input(data->gpio_des_data[index].gpio);
+					gpio_export(data->gpio_des_data[index].gpio,0);
+				}
+				else 
+					gpio_export(data->gpio_des_data[index].gpio,1);
+			}
+		}
+		index++;
+	}
+	return 0;
+}
+
+static int ryd_gpio_probe(struct platform_device *pdev)
+{
+	struct ryd_gpio_des *platdata;
+	platdata = devm_kzalloc(&pdev->dev, sizeof(struct ryd_gpio_des),GFP_KERNEL);
+
+	if (!platdata)
+		return -ENOMEM;
+
+	printk("start new gpio_probe\n");
+
+	rydgpio_parse_dt(pdev->dev.of_node,platdata);
+	rydgpio_deal(pdev,platdata);
+
+	platform_set_drvdata(pdev, platdata);
+
+	printk("start end gpio_probe\n");
+
+	return 0;
+}
+
+
+static const struct of_device_id ryd_gpio_dt_ids[] = {
+	{.compatible = "ryd_gpio_control",},
+	{}
+};
+
+static struct platform_driver ryd_gpio_driver = {
+	.probe = ryd_gpio_probe,
+	.driver = {
+		.name = "ryd_gpio_control",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(ryd_gpio_dt_ids),
+	},
+};
+
+static int __init ryd_gpio_init(void)
+{
+	int retval;
+	retval = platform_driver_register(&ryd_gpio_driver);
+	return retval;
+}
+
+static void __exit ryd_gpio_exit(void)
+{
+	platform_driver_unregister(&ryd_gpio_driver);
+}
+
+subsys_initcall_sync(ryd_gpio_init);
+module_exit(ryd_gpio_exit);