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From deb9dd8d00b81173425215f82ba9cb3e0db31e5c Mon Sep 17 00:00:00 2001
From: Huisong Li <lihuisong@huawei.com>
Date: Tue, 6 Jun 2023 20:10:28 +0800
Subject: net/hns3: fix IMP reset trigger
[ upstream commit bc49e0b4132a05cc012f5e2e7934fbec6589861c ]
Currently, driver sends the command with an unknown opcode to the
firmware to trigger IMP reset when some hardware error happened.
This unknown opcode cannot be parsed by the firmware.
So this patch fixes the way by writing register to do it.
Fixes: 2790c6464725 ("net/hns3: support device reset")
Cc: stable@dpdk.org
Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
---
drivers/net/hns3/hns3_ethdev.c | 16 ++++------------
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c
index 9af08a7748..6c3ae75c4d 100644
--- a/drivers/net/hns3/hns3_ethdev.c
+++ b/drivers/net/hns3/hns3_ethdev.c
@@ -44,6 +44,7 @@
#define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
#define HNS3_VECTOR0_IMP_RD_POISON_B 5U
#define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
+#define HNS3_VECTOR0_TRIGGER_IMP_RESET_B 7U
#define HNS3_RESET_WAIT_MS 100
#define HNS3_RESET_WAIT_CNT 200
@@ -5575,17 +5576,6 @@ hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
return hns3_cmd_send(hw, &desc, 1);
}
-static int
-hns3_imp_reset_cmd(struct hns3_hw *hw)
-{
- struct hns3_cmd_desc desc;
-
- hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
- desc.data[0] = 0xeedd;
-
- return hns3_cmd_send(hw, &desc, 1);
-}
-
static void
hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
{
@@ -5603,7 +5593,9 @@ hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
switch (reset_level) {
case HNS3_IMP_RESET:
- hns3_imp_reset_cmd(hw);
+ val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
+ hns3_set_bit(val, HNS3_VECTOR0_TRIGGER_IMP_RESET_B, 1);
+ hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
tv.tv_sec, tv.tv_usec);
break;
--
2.23.0
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