##path
export WORK_AREA=${PWD}
export SIM = ${WORK_AREA}/sim
export RTL = ${WORK_AREA}/rtl
export TB  = ${WORK_AREA}/tb

###############################
# compile and simulation
###############################	

help:
	@echo "---------------------------------------------------------------------------------"
	@echo "comp  : run vcs for project compile"  
	@echo "sim   : compile and view waveforms"
	@echo "simg  : compile and view waveforms(-gui)"
	@echo "clean : clear sim folder"
	@echo "---------------------------------------------------------------------------------"

comp: clean
	cd ${SIM} && \
	vcs -full64 -sverilog -debug_access+all \
	-timescale=1ns/1ns \
	-f ./filelist.f \
	-top riscv_soc_tb \
	-l vcs_compile.log \

sim: comp
	cd ${SIM} && \
	./simv +$(test)  

simg: comp
	cd ${SIM} && \
	./simv +$(test) -gui & 
###############################
# Clean
###############################

clean: 
	rm -rf  ./sim/csrc ./sim/simv.daidir ./sim/*.key ./sim/*.log ./sim/simv ./sim/DVEfiles ./sim/*.vpd ./sim/*.old