• 1
• 0
• 0

ic-starter/cocotbext-axi

• 1
• 2
• 0

ic-starter/wb2axip

• 1
• 0
• 0

ic-starter/fusesoc-generators

follow github fusesoc/fusesoc-generators

• 1
• 0
• 0

ic-starter/orpsoc-cores

fork from fusesoc ip hub: orpsoc-cores category

• 1
• 0
• 0

ic-starter/fusesoc-cores

fork of fusesoc ip hub: fusesoc-cores category

• 1
• 0
• 0

ic-starter/riscv-pk

keep following github/riscv/riscv-pk

• 1
• 0
• 0

ic-starter/riscv-openocd

• 1
• 0
• 0

ic-starter/nmigen-soc

fork form github

• 1
• 0
• 0

ic-starter/serv

• 1
• 0
• 0

ic-starter/cocotb-bus

• 1
• 0
• 0

ic-starter/mpsoc_example

• 1
• 0
• 0

ic-starter/riscv-debug-dtm

• 1
• 0
• 0

ic-starter/openroad

opensource place & route flow fork from the-openroad-project and try to sync. with its main line.

• 1
• 0
• 0

ic-starter/Cores-SweRVolf

fork from github/chipsalliance

• 1
• 0
• 0

ic-starter/riscv-isa-manual

• 1
• 0
• 0

ic-starter/riscv-opcodes

• 1
• 0
• 0

ic-starter/riscv-isa-sim

keep following github/riscv/riscv-isa-sim

• 1
• 0
• 0

ic-starter/riscv-asm-manual

• 1
• 0
• 0

ic-starter/riscv-debug-spec

• 1
• 0
• 0

ic-starter/imperas-riscv-tests