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ic-starter/VexRiscv

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.travis.yml 1.83 KB
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language: scala
dist: xenial
notifications:
email:
on_success: never
scala:
- 2.11.12
sbt_args: -no-colors -J-Xss2m
addons:
apt:
sources:
- ubuntu-toolchain-r-test
packages:
- git
- make
- autoconf
- g++
- flex
- bison
jdk:
- openjdk10
jobs:
include:
- stage: prepare cache-verilator
script:
- cp scripts/regression/verilator.mk $HOME/makefile
- cd $HOME
- make verilator_binary
- &test
stage: Test
name: Dhrystone
script:
- make regression_dhrystone -C scripts/regression
- <<: *test
stage: Test
name: Baremetal
script:
- make regression_random_baremetal -C scripts/regression
- <<: *test
stage: Test
name: Machine OS
script:
- make regression_random_machine_os -C scripts/regression
- <<: *test
stage: Test
name: Machine OS
script:
- make regression_random_machine_os -C scripts/regression
- <<: *test
stage: Test
name: Mixed
script:
- make regression_random -C scripts/regression
- <<: *test
stage: Test
name: Linux
script:
- make regression_random_linux -C scripts/regression
- <<: *test
stage: Test
name: Linux
script:
- make regression_random_linux -C scripts/regression
before_install:
- cd ..
- git clone https://github.com/SpinalHDL/SpinalHDL.git -b dev
- cd VexRiscv
- export VERILATOR_ROOT=$HOME/verilator
- export PATH=$VERILATOR_ROOT/bin:$PATH
before_cache:
- rm -fv $HOME/.ivy2/.sbt.ivy.lock
- find $HOME/.ivy2/cache -name "ivydata-*.properties" -print -delete
- find $HOME/.sbt -name "*.lock" -print -delete
cache:
directories:
- $HOME/.ivy2/cache
- $HOME/.sbt
- $HOME/verilator
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