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ic-starter/VexRiscv

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Jack Davine 提交于 2023-12-22 00:36 . Add mill to compile and test VexRiscv
*.class
*.log
*.bak
.*.swp
# sbt specific
.cache/
.history/
.lib/
dist/*
target
lib_managed/
src_managed/
project/boot/
project/plugins/project/
# Scala-IDE specific
.scala_dependencies
.worksheet
.idea
out
# Eclipse
bin/
.classpath
.project
.cproject
.settings
.cache-main
#User
/*.vhd
/*.v
*.cf
*.json
*.vcd
*.fst*
!tester/src/test/resources/*.vhd
obj_dir
*.logTrace
*.yaml
*.memTrace
*.regTrace
*.debugTrace
*.tcl
*.o
*.bin
explor
mill
simWorkspace/
tmp/
/archive.tar.gz
*.out32
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