.DS_Store
**/.DS_Store
log
obj_dir/
build/
*.vcd
.idea/
gen/
lib/
project/target
target/
tmp/
simWorkspace/
tty0tty/module/.tmp_versions/tty0tty.mod
tty0tty/module/.cache.mk
tty0tty/module/.tty0tty.mod.cmd
tty0tty/module/tty0tty.mod

toolchain/forth/nuc.fs.orig
vprj/vhdl/J1Sc/J1Sc.cache/
vprj/vhdl/J1Sc/J1Sc.hw/
vprj/vhdl/J1Sc/J1Sc.ip_user_files/
vprj/vhdl/J1Sc/J1Sc.runs/
vprj/vhdl/J1Sc/J1Sc.sim/
vprj/vhdl/J1Sc/J1Sc.srcs/
vprj/vhdl/J1Sc/J1Sc/J1Sc.cache/
vprj/vhdl/J1Sc/J1Sc/J1Sc.hw/
vprj/vhdl/J1Sc/J1Sc/J1Sc.ip_user_files/
vprj/vhdl/J1Sc/J1Sc/J1Sc.runs/
vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/
vprj/vhdl/J1Sc/J1Sc/J1Sc.srcs/
vprj/vhdl/J1Sc/J1Sc/J1Sc.cache
vprj/verilog/J1Sc/J1Sc.cache/
vprj/verilog/J1Sc/J1Sc.hw/
vprj/verilog/J1Sc/J1Sc.ip_user_files/
vprj/verilog/J1Sc/J1Sc.runs/
vprj/verilog/J1Sc/J1Sc.sim/
vprj/verilog/J1Sc/J1Sc.srcs/
toolchain/forth/shell/__pycache__/
toolchain/forth/shell/dpansf.pyc
toolchain/forth/shell/swapforth.pyc
J1Ico.v_toplevel_coreArea_cpu_mainMem_ramList_0.bin
J1Ico.v_toplevel_coreArea_cpu_mainMem_ramList_1.bin
J1Ice.v_toplevel_coreArea_cpu_mainMem_ramList_0.bin
J1Ice.v_toplevel_coreArea_cpu_mainMem_ramList_1.bin
verbose.log
support/openocd/gen/jinfo