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1026508651/shudian_elec-clock

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time_trans.vhd 654 Bytes
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1026508651 提交于 2022-03-16 23:59 . 初始化 零级模块完成
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity time_trans is
port(
CLK_0:in std_logic;
Change_En: in std_logic;
Change_Sec: in std_logic;
CLK_1: out std_logic;
STD_ONE: out std_logic
);
end time_trans;
architecture main of time_trans is
component count_2500 is
port(
CLK_0:in std_logic;
Change_En: in std_logic;
CLK_1: out std_logic
);
end component count_2500;
signal output1: std_logic;
signal output0: std_logic;
begin
T1:count_2500 port map(CLK_0=>CLK_0,Change_En=>Change_En,CLK_1=>output0);
output1<=output0 or Change_Sec;
CLK_1<=output1;
STD_ONE<=output0;
end main;
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