#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__

/* Automatically generated file; DO NOT EDIT. */
/* ArtInChip Luban-Lite SDK Configuration */

/* Project options */

#define PRJ_DEFCONFIG_FILENAME "d13x_kunlunpi88-nor_baremetal_bootloader_defconfig"

/* -- Important: If following options have been changed, you need save & rerun menuconfig before changing any other options. */

#define PRJ_CHIP "d13x"
#define PRJ_BOARD "kunlunpi88-nor"
#define PRJ_KERNEL "baremetal"
#define PRJ_APP "bootloader"
#define PLATFORM_LUBANLITE

/* Chip options */

#define SOC_THEAD_SMART
#define PRJ_CUSTOM_LDS "application/baremetal/bootloader/ldscript/d13x_bootloader_gcc.ld"
#define AIC_CHIP_D13X
#define CACHE_LINE_SIZE 32
#define CPU_BASE 0x20000000
#define AIC_CMU_DRV
#define AIC_CMU_DRV_V11
#define AIC_CMU_DRV_VER "11"
#define AIC_GPIO_DRV
#define AIC_GPIO_DRV_V11
#define AIC_GPIO_DRV_VER "11"
#define AIC_SYSCFG_DRV
#define AIC_SYSCFG_DRV_V11
#define AIC_SYSCFG_DRV_VER "11"
#define AIC_DMA_DRV
#define AIC_DMA_DRV_V11
#define AIC_DMA_DRV_VER "11"
#define AIC_DMA_CH_NUM 8
#define AIC_DMA_ALIGN_SIZE 8
#define AIC_UART_DRV
#define AIC_UART_DRV_V11
#define AIC_UART_DEV_NUM 8
#define AIC_QSPI_DRV
#define AIC_QSPI_DRV_V11
#define AIC_QSPI_DRV_VER "11"
#define AIC_XSPI_DRV
#define AIC_XSPI_DRV_V10
#define AIC_WRI_DRV
#define AIC_WRI_DRV_V11
#define AIC_WRI_DRV_VER "11"
#define AIC_RTC_DRV
#define AIC_RTC_DRV_V11
#define AIC_RTC_DRV_VER "11"
#define AIC_WDT_DRV
#define AIC_WDT_DRV_V10
#define AIC_WDT_DRV_VER "10"
#define AIC_SDMC_DRV
#define AIC_SDMC_DRV_V11
#define AIC_SDMC_DRV_VER "11"
#define AIC_SID_DRV
#define AIC_SID_DRV_V11
#define AIC_SID_DRV_VER "11"

/* Board options */

/* Interface Related:  */

#define AIC_USING_UART0

/* Uart0 Parameter */

#define AIC_CLK_UART0_FREQ 48000000
#define AIC_DEV_UART0_BAUDRATE 115200
#define AIC_DEV_UART0_DATABITS 8
#define AIC_DEV_UART0_STOPBITS 1
#define AIC_DEV_UART0_PARITY 0
#define AIC_DEV_UART0_MODE_RS232
#define AIC_DEV_UART0_MODE 0
#define AIC_UART0_FLAG 259
#define AIC_DEV_UART0_RX_MODE_POLL
#define AIC_DEV_UART0_RX_MODE 0

/* Using EPWM */


/* Using HRTIMER */


/* Using CAP */


/* Storage Related:  */

#define AIC_USING_QSPI0

/* SPI0 Parameter */

#define AIC_DEV_QSPI0_MAX_SRC_FREQ_HZ 100000000
#define AIC_QSPI0_BUS_WIDTH_4
#define AIC_QSPI0_BUS_WIDTH 4
#define AIC_DEV_QSPI0_DELAY_MODE 2
#define AIC_QSPI0_DEVICE_SPINOR
#define AIC_QSPI0_DEVICE_SPINOR_FREQ 100000000
#define AIC_USING_SDMC1

/* SDMC1 Parameter */

#define AIC_SDMC1_BUSWIDTH4
#define AIC_SDMC1_DRV_PHASE 3
#define AIC_SDMC1_SMP_PHASE 0

/* WLAN Related: */

#define AIC_WIRELESS_LAN

/* Analog Related:  */


/* MutiMedia Related:  */


/* Camera Support */


/* System Related:  */

#define AIC_USING_DMA
#define AIC_USING_RTC

/* RTC Parameter */

#define AIC_RTC_CLK_RATE 3276800
#define AIC_USING_WDT

/* Mem Options */

/* SRAM parameter */

#define AIC_SRAM_TOTAL_SIZE 0x100000
#define AIC_ITCM_SIZE 0x0
#define AIC_DTCM_SIZE 0x0
#define AIC_SRAM_S1_SIZE_0K
#define AIC_SRAM_S1_SIZE 0
#define AIC_SRAM_S1_REG_SIZE 0x00
#define AIC_SRAM1_SW_SIZE 0x0
#define AIC_BOOTLOADER_RESERVE_SIZE 0x40000

/* PSRAM parameter */

#define AIC_PSRAM_SIZE 0x800000
#define AIC_PSRAM_CMA_EN
#define AIC_PSRAM_SW_SIZE 0x300000
#define AIC_PSRAM_SW_EN

/* ELF Sections memory location */

#define AIC_SEC_TEXT_PSRAM
#define AIC_SEC_RODATA_PSRAM
#define AIC_SEC_DATA_PSRAM
#define AIC_SEC_BSS_PSRAM
#define AIC_INTERRUPTSTACK_SIZE 4096

/* Clocks options */

#define AIC_CLK_PLL_INT0_FREQ 480000000
#define AIC_CLK_PLL_INT1_FREQ 1200000000
#define AIC_CLK_PLL_FRA0_FREQ 0
#define AIC_CLK_PLL_FRA2_FREQ 0
#define AIC_CLK_CPU_FREQ 480000000
#define AIC_CLK_AXI0_FREQ 200000000
#define AIC_CLK_AHB0_FREQ 200000000
#define AIC_CLK_APB0_FREQ 100000000

/* Security Related:  */

#define AIC_USING_SID

/* SID Parameter */

#define EFUSE_MAX_WORD 64
#define EFUSE_TIMING_VALUE 0x0402FFD8
#define AIC_USING_SYSCFG

/* Syscfg Parameter */


/* Baremetal options */

#define KERNEL_BAREMETAL
#define DRIVER_HAL_EN
#define DRIVER_BARE_DRV_EN
#define AIC_NORMALSTACK_SIZE 8092
#define ARCH_RISCV
#define ARCH_RISCV_FPU
#define ARCH_RISCV_FPU_D
#define ARCH_RISCV32

/* Bootloader options */

#define AIC_BOOTLOADER

/* Console */

#define AIC_BOOTLOADER_CONSOLE_UART 0

/* Drivers */

#define AIC_BOOTLOADER_SPINOR_SUPPORT
#define AIC_BOOTLOADER_PSRAM_EN

/* PSRAM Parameter */

#define AIC_XSPI_PSRAM_CS0_PINS 0
#define AIC_XSPI_PSRAM_CS1_PINS 0
#define AIC_XSPI_PSRAM_CLK 198000000
#define AIC_BOOT_USB_DRV
#define AIC_BOOT_USBH_DRV
#define AIC_BOOTLOADER_UDISK_SUPPORT

/* Components */

#define AIC_BOOTLOADER_FATFS_SUPPORT

/* Upgrading */

#define AICUPG_UART_ENABLE
#define AICUPG_USB_ENABLE
#define AICUPG_UDISK_ENABLE
#define AICUPG_USB_CONTROLLER_MAX_NUM 1
#define AICUPG_NOR_ARTINCHIP
#define AICUPG_LOG_BUFFER_SUPPORT
#define AICUPG_LOG_BUFFER_ADDR 0x30040000
#define AICUPG_LOG_BUFFER_SIZE 0x3000

/* Commands */

#define AIC_BOOTLOADER_CMD_NOR_BOOT
#define AIC_BOOTLOADER_CMD_SPI_NOR
#define AIC_BOOTLOADER_CMD_MTD
#define AIC_BOOTLOADER_CMD_MEM
#define AIC_BOOTLOADER_CMD_PART

/* Debug */


/* Local packages options */

/* Third-party packages options */


/* BenchMark Tests */

#define AIC_PRINT_FLOAT_CUSTOM
#define LPKG_USING_FDTLIB

/* ArtInChip packages options */

#define LPKG_USING_ENV

/* Drivers options */

/* AIC Bare Driver */

#define AIC_MTD_BARE_DRV
#define AIC_CONSOLE_BARE_DRV
#define AIC_CONSOLE_SYSNAME "tinySPL"
#define AIC_PRINTF_BARE_DRV
#define AIC_USING_UMM_HEAP
#define AIC_UMM_HEAP_BARE_DRV
#define AIC_SPINOR_DRV

/* Peripheral */

#define LPKG_USING_SFUD
#define BOOTLOADER_SFUD_USING_FLASH_INFO_TABLE

/* Touch Panel Support */

/* Gt911 touch panel options */


/* Ft7411 touch panel options */


/* GSL1680 touch panel options */


/* RTP touch panel options */


/* St16xx touch panel options */


/* External Audio Codec Support */


/* Drivers debug */

#define AIC_LOG_LEVEL_WARN
#define AIC_LOG_LEVEL 4

/* Drivers examples */

#define AIC_SPINOR_DRV_TEST
#define AIC_MTD_BARE_TEST

#endif