//2024-6-26 姜青羊
//z-scan设计

module z_scan (
                    sob,
                    zid,
                    zid_vld,

                    clk,
                    rstn
                );

input  wire         sob;
input  wire         clk,rstn;

output reg          zid_vld;
output reg [5:0]    zid;

always @(posedge clk or negedge rstn) begin
    
end
    
endmodule